Independent University, Bangladesh

Department of Electrical and Electronic Engineering BAETE Accredited

Name: MD. Shybur Rahaman.

ID: 1811099.

Sec: 01.

Course Title : Digital Logic Design Lab

Course Code : EEE 232L / ETE 232L (New); ECR 205L (Old)
Instructor : Md. Tawhid Islam Opu
Experiment No. 03
Experiment Name : Verification of universality of NAND gate and NOR gate.

Objective:
 To verify the universality of NAND and NOR gates.
.

APPARATUS:
 IC Type 7400 Quadruple 2-input NAND gates
 IC Type 7402 Quadruple 2-input NOR gates
 Power supply,
 Connecting wires,
 Breadboard etc.

Theory:

#Qus : What is Universal gate?

Ans: Universal gate can be implemented by any Boolean function. Universal gate are
“NAND”, “NOR” gate. Because they are able to be combined to produce any others gates like
AND, OR, NOT gates. That’s the Universality of NAND and NOR gates.
#AND gate :

And gate operate when 2 input are high position then output high. Otherwise output
is always low.
Truth Table

(0.0=0) (0.1=0)

(1.0=0) (1.1=1)
#OR gate:

In this gate when 2 input are low position only then output is low, otherwise always
output is high state.

Truth table

(0+0=0) (0+1=1)

(1+0=1) (1+1=1)
#NOT gate:

NOT gate operate when the output will be the inverse of input.

Truth Table

(0=1)

(1=0)
NAND gate as a universal gate:
To prove that any Boolean function can be implemented using only NAND gates, we will show that
the AND, OR, and NOT operations can be performed using only these gates.
#NAND gate:

Pin Diagram:

(0.0=1) (0.1=1)

(1.0=1) (1.1=0)
#Implementing NOT using NAND gate:
All NAND input pins connect to the input signal A gives an output A as shown in fig (a)

NOT gate using NAND gate

Truth Table

(0=1)

(1=0)
#Implementing AND using NAND gate:
An AND gate can be replaced by NAND gates as shown in the figure (b). The AND is replaced by a
NAND gate with its output complemented by a NAND gate inverter.

AND gate using NAND gate

Truth Table

(0.0=0) (0.1=0)

(1.0=0) (1.1=1)
#Implementing OR using NAND gate:
An OR gate can be replaced by NAND gates as shown in the figure(c).The OR gate is replaced
by a NAND gate with all its inputs complemented by NAND gate inverters.

OR gate using NAND gate

Truth Table

(0.0=0) (0.1=1)

(1.0=1) (1.1=1)
NOR gate as a universal gate:
To prove that any Boolean function can be implemented using only NOR gates, we will show that the AND,
OR, and NOT operations can be performed using only these gates. The following fig shows the circuit for
implementation.

#NOR gate:

Pin Diagram:

(0+0=1) (0+1=0)

(1+0=0) (1+1=0)
#Implementing NOT using NOR gate:

All NOR input pins connect to the input signal A gives an output A as shown in fig (a)

NOT gate using NOR gate

Truth Table

(0=1)

(1=0)
#Implementing AND using NOR gate:
An AND gate can be replaced by NOR gates as shown in the figure (b). The AND is replaced by a NOR
gate with its output complemented by a NOR gate inverter.

AND gate using NOR gate

Truth Table

(0+0=0) (0+1=0)

(1+0=0) (1+1=1)
#Implementing OR using NOR gate:
An OR gate can be replaced by NOR gates as shown in the figure(c).The OR gate is replaced by a NOR gate

with all its inputs complemented by NOR gate inverters.

OR gate using NOR gate

Truth Table

(0+0=0) (0+1=1)

(1+0=1) (1+1=1)
#Question:

i. Implement XOR gate using NAND gate, provide schematic diagram & Verify Truth
Table.

XOR gate Truth Table

Schematic diagram:

(0.0=0) (0.1=1)

(1.0=1) (1.1=0)
 ii. Implement XNOR gate using NOR gate, provide schematic diagram & Verify Truth
Table.

XNOR gate Truth Table

Schematic diagram:

(0+0=1) (0+1=0)

(1+0=0) (1+1=1)
 LAB REPORT RUBRICS

Student Name MD. Shybur Rahaman. Student ID 1811099.

Course Title Digital Logic Design Lab . Course Code EEE 232L .
Term Spring Summer Autumn Year 2021.
Experiment Verification of universality of NAND gate and Experiment
03.
Name NOR gate. Number
Submission
21/10/2021. Due Date 21/10/2021.
Date
Tick () on the appropriate box (any one from 1 to 5)
Rubrics (weight) Accomplished Intermediate Developing Intermediate Novice
(5) (4) (3) (2) (1)
Understanding Defined experiment Intermediate Defined Intermediate Defined
experiment’s requirements and between experiment between novice experiment
requirements assume circuit developing requirements and and developing. requirements and
(5%) specifications, if any, and assume circuit assume circuit
properly. accomplished. specifications, if specifications, if
any, moderately. any, poorly.

Building Circuit Conducted Intermediate Conducted Intermediate Conducted

and conducting experiment properly between experiment between novice experiment
experiment (5%) by building developing & moderately by and developing. poorly by
simulation circuit accomplished. building building
using required simulation circuit simulation
specification. using required circuit using
specification. required
specification.

Result and Analyzed and Intermediate The results are Intermediate The results are
analysis (5%) interpreted the results between analyzed to some between novice analyzed poorly
properly using the developing extent according and developing. due to
converter parameters. and to specified incomplete
accomplished. requirements. simulation.

Remarks / Answered the given Intermediate Answered Intermediate Answered the

Answering questions correctly between partially the between novice given questions
Question (5%) and describe the developing given questions and developing. incorrectly and
remarks properly. and and describe the describe the
accomplished. remarks remarks poorly.
moderately.

Sub Total
Deduction for late
submission / any
other issue
Total (20%)
20% of Total