University of Bahrain

College of Information technology

Department of Computer Engineering

Test (2)

Student Name
I.D. No.
Section

Course Title: Digital Logic

Course number: ITCE 202-ITCE 250
Semester: 1
Academic Year: 2011/2012
Duration : 1 hour
Date: 29th December 2011

Read the following before you start:

1. Write your name, ID and section number
2. Answer all questions.
3. Write your answers on the attached sheets only.

Question Mark Mark attained

1 25

2 25
3 25

4 25

Total 100
 ITCE 202-ITCE 250 Test 2 29th December 2011

Question [1]: [25 mark]

a. Design a two bit-word comparator that accepts as inputs two words A= A1A0 and B =
B1B0 and generates three outputs F1 (if A> B), F2 (if A=B ) and F3 (if A <B).

1- Give the truth table of the comparator.

2- Design the comparator with a decoder and extra gates.

b. Design a Full-adder by using two multiplexers and extra gates.

1- Give the truth table of a Full adder.
2- Implement the Full adder by using two 2-1 multiplexers, use the same variable for the
two multiplexers' selection lines.

2
 ITCE 202-ITCE 250 Test 2 29th December 2011

Question [2] : [25 mark]

Consider the truth table of a BCD to 7-Segment code converter described in the table
below. Assuming that for any values of “wxyz”> “1001”, the output “abcdefg” = “0000000”,
do the following implementations:

1. Implement the output function (e) using 4-to-1 Mux and any additional logic
gates.
2. Determine the size of a ROM to implement the circuit. Draw the required ROM
showing its internal structures.

BCD Input 7-segment output

w x y z a b c d e f g
0 0 0 0 1 1 1 1 1 1 0
0 0 0 1 0 1 1 0 0 0 0
0 0 1 0 1 1 0 1 1 0 1
0 0 1 1 1 1 1 1 0 0 1
0 1 0 0 0 1 1 0 0 1 1
0 1 0 1 1 0 1 1 0 1 1
0 1 1 0 1 0 1 1 1 1 1
0 1 1 1 1 1 1 0 0 0 0
1 0 0 0 1 1 1 1 1 1 1
1 0 0 1 1 1 1 1 0 1 1

3
 ITCE 202-ITCE 250 Test 2 29th December 2011

Question [3]: [25 mark]

a. Write the truth table of a J-K FF, and
derive the characteristic (next-state)
equation.

b. Complete the timing diagram of the J-K FF assuming initially Q=0.

4
 ITCE 202-ITCE 250 Test 2 29th December 2011

Question [4]: [25 mark]

Given the following circuit:

a. Write the expression of F in terms of (X,Y,A,B,C and D).

b. Re-implement the circuit using all Multiplexers.

c. Re-implement the circuit using one multiplexers.

5
Question [1]: [25 mark]

a) Using a suitable decoder and 3 logic gates, design a logic circuit that adds two 2-
bit numbers, N1=A1A0 and N2=B1B0, Where N1 is the MS and N2 is the LS.
Carry in is zero (no carry in) (for example N1=10, N2=11, N1+N2=101=CoutS2S1,
Cout=Carry out=1, S2=Sum2=0, S1=Sum1=1) (Hint: Construct the truth table to
find the logic expressions of Cout, S2 and S1 in decimal minterms notation, then
design the required circuit)

b) Design a circuit for Cout using multiplexer and some logic gates as required. Use
A1 and A0 as select inputs.
 University of Bahrain
College of Information technology
Department of Computer Engineering

Test (2)

Student Name
I.D. No.
Section

Course Title: Digital Logic

Course number: ITCE 202-250
Semester: 1
Academic Year: 2014/2015
Duration : 1 hour
Date: 9th December 2014

Read the following before you start:

1. Write with PEN
2. Write your name, ID and section number
3. Answer all questions.
4. Write your answers on the attached sheets only.

Question Mark
1 ( 20 Mark)
2 ( 18 Mark)
3 ( 20 Marks)
4 ( 18 Mark)
5 ( 24 Mark)
Total (100)
 ITCE 202-250 Test 2 9th December 2014

Question [1]: ( 20 Mark)

Implement the following Boolean function:
f ( A, B, C ) = Σm(0,3,4,7) 3-to-8 3-to-8
Using a 3-to-8 line decoder and: Decoder Decoder

EN EN

a. an extra OR gate.

b. an extra NAND gate.

c. an extra AND gate.

d. an extra NOR gate.

2
 ITCE 202-250 Test 2 9th December 2014

Question [2]: ( 18 Marks)

Implement the following function with a 4-to-1 Multiplexer and a minimum number of logic
gates:

F(a,b,c,d) = Σm(,0,1,4,7,8,9,10,15,)

3
 ITCE 202-250 Test 2 9th December 2014

Question [3]: ( 20 Marks)

A ROM that stores the values of the following arithmetic function is to be designed:

F= 2(a+b) where a and b are 2-bit binary numbers.

a- Give the size of the ROM

b- Draw the internal structure of the ROM showing the last 3 memory lines.

4
 ITCE 202-250 Test 2 9th December 2014

Question [4]: ( 18 Marks)

x 2-1

MUX a Sum F1

y Half Adder

w b Cout F2

Write the equations of the inputs a and b of the given Half Adder, then give the
equations of F1 and F2.

5
 ITCE 202-250 Test 2 9th December 2014

Question [5]: ( 24 Marks)

a. Complete the timing diagram for the given Flip-Flop. (Assume the initial state of the F-F is
equal to zero).

J Q
FF

K Q’

clock

b. Convert a J-K to S-R Flip-Flop showing all steps.

6
 University of Bahrain
College of Information technology
Department of Computer Engineering

Test (2)

Student Name
I.D. No.
Section
List Number

Course Title: Digital Logic

Course number: ITCE 250
Semester: 1
Academic Year: 2016/2017
Duration: 1:15 hour
Date: 28th December 2016

Read the following before you start:

1. Write your name, ID, section number, and list number
2. Answer all questions.
3. Write your answers on the attached sheets only.

Question Mark Mark attained

1 25

2 25
3 25

4 25

Total 100

1
ITCE 250 Test 2 28th December 2016

Question [1]: [25 mark]

Implement the following Boolean function
f(A, B, C, D) = ∑ 𝑚(0,1,2,6,7,8,10,13,14)

a. Using a decoder and a NAND logic gate [10 marks]

b. Using a 4-to-1 Multiplexer and any additional logic gates, with BC as control lines.
[15 marks]

2
ITCE 250 Test 2 28th December 2016

Question [2]: [25 mark]

a. Show how a full adder can be constructed using two half adders and gates. In your
solution give: [14 marks]
i. The truth table of the full adder
ii. Derive the output functions from the truth table using k maps
iii. Draw the final circuit, using the block diagram of the half adder.

3
ITCE 250 Test 2 28th December 2016

b. Realize the following function: F= A'BC' + BD + AC + B'CD' [16 marks]

i. Using only 2-input NAND gates
ii. Using only 2-input NOR gates

4
ITCE 250 Test 2 28th December 2016

Question [3]: [25 mark]

c. Implement the following Boolean function using 3-state buffers and active high 3-
to-8 decoder: [10 marks]

F(X, Y, Z) = ∑ 𝑚(0,1,5,6,7)

5
ITCE 250 Test 2 28th December 2016

d. Implement the output functions (a, b, c, d, e, f, and g) of the BCD to 7-Segment

code convert listed in Table 1 using ROM, assuming that for any values of “wxyz”>
“1001”, the output “abcdefg” = “1111111”. Draw the circuit showing all details.
[15 marks]

Table 1: BCD to 7-Segment Code

BCD (I/P) 7-Seg (O/P)

wxyz abcdefg
0000 0000001
0001 1001111
0010 0010010
0011 0000110
0100 1001100
0101 0100100
0110 0100000
0111 0001111
1000 0000000
1001 0000100

6
ITCE 250 Test 2 28th December 2016

Question [4]: [25 mark]

a. Derive the next state equation of an S-R flip flop. [5 marks]

b. Complete the timing diagram of the S-R flip flop shown in the figure. [20 mark]

PreN

SET
S Q
CLK

R CLR Q

ClrN

Clock

PreN

ClrN