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ELL 201: Digital Electronics

Lecture 14

Prof. Manan Suri (EE)

manansuri@ee.iitd.ac.in
http://web.iitd.ac.in/~manansuri/

M. Suri, ELL201, (copyright IITD) "Intended for

Academic Fair Use Only"
Recap: Sequential Logic
Feed back from the memory element !

• Different types of memory elements can exist

• Ex – Latches, Flip-flops etc
• These elements can be synchronous or asynchronous
• Synchronous: Driven by a Clock
• Asynchronous: Not driven directly by Clock

M. Suri, ELL201, (copyright IITD) "Intended for

Academic Fair Use Only"
Recap: Basic Blocks - Latches and Flip-Flops

M. Suri, ELL201, (copyright IITD) "Intended for

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Recap: SR Latch (using NOR)
• One of the most basic storage element
• Name comes from a door-latch!
• You either latch the door open or close
• Once you latch it, the door stays in that state
• First Variety of Latch → Set – Reset Latch (SR)
• SR Latch can be built using NOR & NAND gates

Cross couple the two NOR Gates (internal feedback)

Characteristic table of SR Latch?

Memory !!

M. Suri, ELL201, (copyright IITD) "Intended for

Academic Fair Use Only"
Recap: S’R’ Latch (using NAND)
Characteristic table of SR Latch using NAND Gates?

Memory !!

Complementary of NOR based SR Latch

Also known as S’R’ Latch

M. Suri, ELL201, (copyright IITD) "Intended for

Academic Fair Use Only"
Recap: SR Latch with Enable (using NAND)

Whenever En = 0, output of 1st level NAND gates will be 1

When both 2nd level NAND inputs are 1, 1 → No Change
Irrespective of S, R values → nothing happens in the Latch

M. Suri, ELL201, (copyright IITD) "Intended for

Academic Fair Use Only"
Recap: D-Latch
D stands for – Data Latch
Take SR Latch with enable circuit
Instead of 3 inputs (S,R & En) → Make it just a 2 input system
Use single D (Data) Input with a Not gate

S,R can never be (1,1) or (0,0) in this configuration

How do you obtain the memory or no change state then?
By using Enable!!

M. Suri, ELL201, (copyright IITD) "Intended for

Academic Fair Use Only"
Recap: Timing Diagrams
• Displays all Inputs and Outputs on a common time X-axis
• Visually takes care of propagation delays
• Helps to systematically plot the circuit characteristics

M. Suri, ELL201, (copyright IITD) "Intended for

Academic Fair Use Only"
Recap: Triggering Mechanisms
• Is having a Clock Enough ? During full clock cycle possibility to switch → Make fast
clocks? Not that easy → any other ideas? → Just exploit the clock edges !!

• Edge-Triggered Units → Nomenclature nightmare → Edge triggered latches → Flip-

Flops

• Latches by definition are Level Triggered; Flip-Flops are 99% Edge triggered

M. Suri, ELL201, (copyright IITD) "Intended for

Academic Fair Use Only"
Recap: Edge Triggered Latches (Flip-Flops)
• Edge triggering using basic pulse detector circuits

M. Suri, ELL201, (copyright IITD) "Intended for

Academic Fair Use Only"
Recap: Edge Triggered SR-latch = SR Flip-Flop

M. Suri, ELL201, (copyright IITD) "Intended for

Academic Fair Use Only"
Tentative Timeline
(Note: timeline may change during the semester without any prior notice → details are only of indicative nature)

Lec. No Content
1 Intro + Logistics + Course Policy + Motivation etc
2 Why digital, Number Systems + Conversions etc.
3 Fractional, Complements, Addn, Subtraction
4 Logic Gates, Boolean Algebra, Minterm, Maxterm, SOP, POS
5
KMaps, Minimization, XoR Gate
6
7 XOR Gate, Adders (half/full) + Parity bit circuits + 4-bit adder + subtraction +
8 overflow detection + BCD adder, Ripple Carry, CLA, 4-bit, 16-bit, 64-bit, Timing
9 Analysis, etc.
10
Mux + Decoders + Encoders
11
12 Quiz-1

13
14
15 Sequential Logic - Latches. Flip flops, varieties, counters, registers, digital CMOS,
16 Verilog intro
17
18
Mid Sem Break
19
20 FSM intro, Moore, Mealy, Examples, Conversions etc.
21
22
Memory, Advanced topics, etc.
23
24 Quiz - 2
Major Exam
M. Suri, ELL201, (copyright IITD) "Intended for
Academic Fair Use Only"
Level Triggered (Latch) Vs Edge Triggered (Flip-Flop)

M. Suri, ELL201, (copyright IITD) "Intended for

Academic Fair Use Only"
Level Triggered (Latch) Vs Edge Triggered (Flip-Flop)

M. Suri, ELL201, (copyright IITD) "Intended for

Academic Fair Use Only"
Level Triggered (Latch) Vs Edge Triggered (Flip-Flop)

M. Suri, ELL201, (copyright IITD) "Intended for

Academic Fair Use Only"
Level Triggered (Latch) Vs Edge Triggered (Flip-Flop)

M. Suri, ELL201, (copyright IITD) "Intended for

Academic Fair Use Only"
Level Triggered (Latch) Vs Edge Triggered (Flip-Flop)

M. Suri, ELL201, (copyright IITD) "Intended for

Academic Fair Use Only"
Level Triggered (Latch) Vs Edge Triggered (Flip-Flop)

M. Suri, ELL201, (copyright IITD) "Intended for

Academic Fair Use Only"
Level Triggered (Latch) Vs Edge Triggered (Flip-Flop)

M. Suri, ELL201, (copyright IITD) "Intended for

Academic Fair Use Only"
Level Triggered (Latch) Vs Edge Triggered (Flip-Flop)

M. Suri, ELL201, (copyright IITD) "Intended for

Academic Fair Use Only"
Level Triggered (Latch) Vs Edge Triggered (Flip-Flop)

M. Suri, ELL201, (copyright IITD) "Intended for

Academic Fair Use Only"
Level Triggered (Latch) Vs Edge Triggered (Flip-Flop)

M. Suri, ELL201, (copyright IITD) "Intended for

Academic Fair Use Only"
Level Triggered (Latch) Vs Edge Triggered (Flip-Flop)

M. Suri, ELL201, (copyright IITD) "Intended for

Academic Fair Use Only"
Level Triggered (Latch) Vs Edge Triggered (Flip-Flop)

M. Suri, ELL201, (copyright IITD) "Intended for

Academic Fair Use Only"
Level Triggered (Latch) Vs Edge Triggered (Flip-Flop)

M. Suri, ELL201, (copyright IITD) "Intended for

Academic Fair Use Only"
Level Triggered (Latch) Vs Edge Triggered (Flip-Flop)

M. Suri, ELL201, (copyright IITD) "Intended for

Academic Fair Use Only"
Level Triggered (Latch) Vs Edge Triggered (Flip-Flop)

M. Suri, ELL201, (copyright IITD) "Intended for

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Level Triggered (Latch) Vs Edge Triggered (Flip-Flop)

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Master-Slave Configuration of D – Latch

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Master-Slave Configuration of D – Latch D Latch/FF
Qm Qs
Clk D Qn+1
0 X Qn
1 0 0
1 1 1
1 2 3 4 5 6 7 8
CLK

Qm

Qs

Qp

Qn

M. Suri, ELL201, (copyright IITD) "Intended for

Academic Fair Use Only"
Master-Slave Configuration of D – Latch D Latch
Qm Qs
Clk D Qn+1
Insert NOT here 0 X Qn
1 0 0
1 1 1
1 2 3 4 5 6 7 8
CLK

Qm Master Slave D Latch

is – ve edge triggered
flip-flop !!
Qs

Qp
Latch  → Flip Flop

Qn

How can you make + ve edge triggered? → flip clk

M. Suri, ELL201, (copyright IITD) "Intended for
Academic Fair Use Only"
JK-Flip Flop
• There are several kinds of FFs in the world of digital electronic systems
• D-FF is considered very effective – number of gates and silicon area is low
• Using D-FF and some added combinational logic → build other kinds of FF– ex JK, T
• What is the limitation of SR- FF → State 1,1 (0,0) is unused
• Utilize the invalid state of SR, S’R’ → JK flip-flop !
• Let’s assign new functionality for the condition 1,1. → Complement functionality or toggle!

Same as SR FF, only difference is the condition 1,1

M. Suri, ELL201, (copyright IITD) "Intended for

Academic Fair Use Only"
JK-Flip Flop
• There are several kinds of FFs in the world of digital electronic systems
• D-FF is considered very effective – number of gates and silicon area is low
• Using D-FF and some added combinational logic → build other kinds of FF– ex JK, T
• What is the limitation of SR- FF → State 1,1 (0,0) is unused
• Utilize the invalid state of SR, S’R’ → JK flip-flop !
• Let’s assign new functionality for the condition 1,1. → Complement functionality or toggle!

Inputs Outputs Remarks

J K C Q Q’
0 0 Q Q’ No Change
0 1 0 1 RESET
1 0 1 0 SET
1 1 Q’ Q Toggle

Same as SR FF, only difference is the condition 1,1

M. Suri, ELL201, (copyright IITD) "Intended for

Academic Fair Use Only"
JK-Flip Flop – Build using D-Flip Flop?

Build a full truth table from the characteristic table – defined in terms of Q, Qnext

M. Suri, ELL201, (copyright IITD) "Intended for

Academic Fair Use Only"
JK-Flip Flop – Build using D-Flip Flop?

Build a full truth table from the characteristic table – defined in terms of Q, Qnext

M. Suri, ELL201, (copyright IITD) "Intended for

Academic Fair Use Only"
JK-Flip Flop – Build using D-Flip Flop?

Build a full truth table from the characteristic table – defined in terms of Q, Qnext

M. Suri, ELL201, (copyright IITD) "Intended for

Academic Fair Use Only"
JK-Flip Flop – Build using D-Flip Flop?

Build a full truth table from the characteristic table – defined in terms of Q, Qnext

M. Suri, ELL201, (copyright IITD) "Intended for

Academic Fair Use Only"
JK-Flip Flop – Build using D-Flip Flop?

Build a full truth table from the characteristic table – defined in terms of Q, Qnext

M. Suri, ELL201, (copyright IITD) "Intended for

Academic Fair Use Only"
JK-Flip Flop – Build using D-Flip Flop?

Build a full truth table from the characteristic table – defined in terms of Q, Qnext

M. Suri, ELL201, (copyright IITD) "Intended for

Academic Fair Use Only"
JK-Flip Flop – Build using D-Flip Flop?

Build a full truth table from the characteristic table – defined in terms of Q, Qnext

M. Suri, ELL201, (copyright IITD) "Intended for

Academic Fair Use Only"
JK-Flip Flop – Build using D-Flip Flop?

Build a full truth table from the characteristic table – defined in terms of Q, Qnext

M. Suri, ELL201, (copyright IITD) "Intended for

Academic Fair Use Only"
JK-Flip Flop – Build using D-Flip Flop?

Build a full truth table from the characteristic table – defined in terms of Q, Qnext

M. Suri, ELL201, (copyright IITD) "Intended for

Academic Fair Use Only"
JK-Flip Flop – Build using D-Flip Flop?

Build a full truth table from the characteristic table – defined in terms of Q, Qnext

M. Suri, ELL201, (copyright IITD) "Intended for

Academic Fair Use Only"
JK-Flip Flop – Build using D-Flip Flop?

Build a full truth table from the characteristic table – defined in terms of Q, Qnext

M. Suri, ELL201, (copyright IITD) "Intended for

Academic Fair Use Only"
JK-Flip Flop – Build using D-Flip Flop?

Build a full truth table from the characteristic table – defined in terms of Q, Qnext

M. Suri, ELL201, (copyright IITD) "Intended for

Academic Fair Use Only"
JK-Flip Flop – Build using D-Flip Flop?

Build a full truth table from the characteristic table – defined in terms of Q, Qnext

M. Suri, ELL201, (copyright IITD) "Intended for

Academic Fair Use Only"
JK-Flip Flop – Build using D-Flip Flop?

Build a full truth table from the characteristic table – defined in terms of Q, Qnext

M. Suri, ELL201, (copyright IITD) "Intended for

Academic Fair Use Only"
JK-Flip Flop – Build using D-Flip Flop?

Build a full truth table from the characteristic table – defined in terms of Q, Qnext

M. Suri, ELL201, (copyright IITD) "Intended for

Academic Fair Use Only"
JK-Flip Flop – Build using D-Flip Flop?

Build a full truth table from the characteristic table – defined in terms of Q, Qnext

M. Suri, ELL201, (copyright IITD) "Intended for

Academic Fair Use Only"
JK-Flip Flop – Build using D-Flip Flop?

Build a full truth table from the characteristic table – defined in terms of Q, Qnext

M. Suri, ELL201, (copyright IITD) "Intended for

Academic Fair Use Only"
JK-Flip Flop – Build using D-Flip Flop?

Build a full truth table from the characteristic table – defined in terms of Q, Qnext

In D latch, Q directly follows the input D

M. Suri, ELL201, (copyright IITD) "Intended for

Academic Fair Use Only"
JK-Flip Flop – Build using D-Flip Flop?
In D latch, Q directly follows the input D

J input sets the flip-flop to 1,

K input resets it to 0,
when both inputs are enabled, the output is complemented.

When J = 1 and K = 0, D = Q’ + Q = 1, so the next clock edge sets the output to 1.

When J = 0 and K = 1, D = 0, so the next clock edge resets the output to 0.
When both J = K = 1 and D = Q’, the next clock edge complements the output.
When both J = K = 0 and D = Q, the clock edge leaves the output unchanged.

M. Suri, ELL201, (copyright IITD) "Intended for

Academic Fair Use Only"
JK-Flip Flop – Build using D-Flip Flop?
In D latch, Q directly follows the input D

J input sets the flip-flop to 1,

K input resets it to 0,
when both inputs are enabled, the output is complemented.

When J = 1 and K = 0, D = Q’ + Q = 1, so the next clock edge sets the output to 1.

When J = 0 and K = 1, D = 0, so the next clock edge resets the output to 0.
When both J = K = 1 and D = Q’, the next clock edge complements the output.
When both J = K = 0 and D = Q, the clock edge leaves the output unchanged.

M. Suri, ELL201, (copyright IITD) "Intended for

Academic Fair Use Only"
JK-Flip Flop – Build using D-Flip Flop?
In D latch, Q directly follows the input D

J input sets the flip-flop to 1,

K input resets it to 0,
when both inputs are enabled, the output is complemented.

When J = 1 and K = 0, D = Q’ + Q = 1, so the next clock edge sets the output to 1.

When J = 0 and K = 1, D = 0, so the next clock edge resets the output to 0.
When both J = K = 1 and D = Q’, the next clock edge complements the output.
When both J = K = 0 and D = Q, the clock edge leaves the output unchanged.

M. Suri, ELL201, (copyright IITD) "Intended for

Academic Fair Use Only"
JK-Flip Flop – Build using D-Flip Flop?
In D latch, Q directly follows the input D

J input sets the flip-flop to 1,

K input resets it to 0,
when both inputs are enabled, the output is complemented.

When J = 1 and K = 0, D = Q’ + Q = 1, so the next clock edge sets the output to 1.

When J = 0 and K = 1, D = 0, so the next clock edge resets the output to 0.
When both J = K = 1 and D = Q’, the next clock edge complements the output.
When both J = K = 0 and D = Q, the clock edge leaves the output unchanged.

M. Suri, ELL201, (copyright IITD) "Intended for

Academic Fair Use Only"
JK-Flip Flop – Build using D-Flip Flop?
In D latch, Q directly follows the input D

J input sets the flip-flop to 1,

K input resets it to 0,
when both inputs are enabled, the output is complemented.

When J = 1 and K = 0, D = Q’ + Q = 1, so the next clock edge sets the output to 1.

When J = 0 and K = 1, D = 0, so the next clock edge resets the output to 0.
When both J = K = 1 and D = Q’, the next clock edge complements the output.
When both J = K = 0 and D = Q, the clock edge leaves the output unchanged.

M. Suri, ELL201, (copyright IITD) "Intended for

Academic Fair Use Only"
JK-Flip Flop – Build using D-Flip Flop?
In D latch, Q directly follows the input D

J input sets the flip-flop to 1,

K input resets it to 0,
when both inputs are enabled, the output is complemented.

When J = 1 and K = 0, D = Q’ + Q = 1, so the next clock edge sets the output to 1.

When J = 0 and K = 1, D = 0, so the next clock edge resets the output to 0.
When both J = K = 1 and D = Q’, the next clock edge complements the output.
When both J = K = 0 and D = Q, the clock edge leaves the output unchanged.

M. Suri, ELL201, (copyright IITD) "Intended for

Academic Fair Use Only"
JK-Flip Flop – Build using D-Flip Flop?
In D latch, Q directly follows the input D

J input sets the flip-flop to 1,

K input resets it to 0,
when both inputs are enabled, the output is complemented.

When J = 1 and K = 0, D = Q’ + Q = 1, so the next clock edge sets the output to 1.

When J = 0 and K = 1, D = 0, so the next clock edge resets the output to 0.
When both J = K = 1 and D = Q’, the next clock edge complements the output.
When both J = K = 0 and D = Q, the clock edge leaves the output unchanged.

M. Suri, ELL201, (copyright IITD) "Intended for

Academic Fair Use Only"
JK-Flip Flop – Build using D-Flip Flop?
In D latch, Q directly follows the input D

J input sets the flip-flop to 1,

K input resets it to 0,
when both inputs are enabled, the output is complemented.

When J = 1 and K = 0, D = Q’ + Q = 1, so the next clock edge sets the output to 1.

When J = 0 and K = 1, D = 0, so the next clock edge resets the output to 0.
When both J = K = 1 and D = Q’, the next clock edge complements the output.
When both J = K = 0 and D = Q, the clock edge leaves the output unchanged.

M. Suri, ELL201, (copyright IITD) "Intended for

Academic Fair Use Only"
JK-Flip Flop – Build using D-Flip Flop?
In D latch, Q directly follows the input D

J input sets the flip-flop to 1,

K input resets it to 0,
when both inputs are enabled, the output is complemented.

When J = 1 and K = 0, D = Q’ + Q = 1, so the next clock edge sets the output to 1.

When J = 0 and K = 1, D = 0, so the next clock edge resets the output to 0.
When both J = K = 1 and D = Q’, the next clock edge complements the output.
When both J = K = 0 and D = Q, the clock edge leaves the output unchanged.

M. Suri, ELL201, (copyright IITD) "Intended for

Academic Fair Use Only"
JK-Flip Flop – Build using D-Flip Flop?
In D latch, Q directly follows the input D

J input sets the flip-flop to 1,

K input resets it to 0,
when both inputs are enabled, the output is complemented.

When J = 1 and K = 0, D = Q’ + Q = 1, so the next clock edge sets the output to 1.

When J = 0 and K = 1, D = 0, so the next clock edge resets the output to 0.
When both J = K = 1 and D = Q’, the next clock edge complements the output.
When both J = K = 0 and D = Q, the clock edge leaves the output unchanged.

M. Suri, ELL201, (copyright IITD) "Intended for

Academic Fair Use Only"
JK-Flip Flop – Build using D-Flip Flop?
In D latch, Q directly follows the input D

J input sets the flip-flop to 1,

K input resets it to 0,
when both inputs are enabled, the output is complemented.

When J = 1 and K = 0, D = Q’ + Q = 1, so the next clock edge sets the output to 1.

When J = 0 and K = 1, D = 0, so the next clock edge resets the output to 0.
When both J = K = 1 and D = Q’, the next clock edge complements the output.
When both J = K = 0 and D = Q, the clock edge leaves the output unchanged.

M. Suri, ELL201, (copyright IITD) "Intended for

Academic Fair Use Only"
JK-Flip Flop – Build using D-Flip Flop?
In D latch, Q directly follows the input D

J input sets the flip-flop to 1,

K input resets it to 0,
when both inputs are enabled, the output is complemented.

When J = 1 and K = 0, D = Q’ + Q = 1, so the next clock edge sets the output to 1.

When J = 0 and K = 1, D = 0, so the next clock edge resets the output to 0.
When both J = K = 1 and D = Q’, the next clock edge complements the output.
When both J = K = 0 and D = Q, the clock edge leaves the output unchanged.

M. Suri, ELL201, (copyright IITD) "Intended for

Academic Fair Use Only"
Thank you

M. Suri, ELL201, (copyright IITD) "Intended for

Academic Fair Use Only"