강의과목: 반도체소자공학

Semiconductor Physics and Devices

- Basic Principles: 3rd edition
Donald A. Neamen

반도체 물성과 소자 - Ch.0

조 채 용 교수

나노응용공학과 3년
2015년 2학기 강의
물리관 509호
화, 목요일 (09:00-10:15)
Department of Nano Fusion Technology
Pusan National University * e-mail: crcho@pusan.ac.kr
Outline
Ch.0 반도체와 집적회로
Ch.1 고체의 결정구조
Ch.2 양자역학의 입문
Ch.3 고체양자이론의 입문
Ch.4 평형상태의 반도체
Ch.5 캐리어 전송 현상
Ch.6 반도체내의 비평형 과잉캐리어
Ch.7 pn 접합
Ch.8 pn 접합 다이오우드
Ch.9 금속-반도체 이종접합 및 반도체 이종접합
Ch.11 MOSFET의 기초
Ch.14 광소자
Department of Nano Fusion Technology
Pusan National University
 Ch. 0

Department of Nano Fusion Technology

Pusan National University
 Ch. 0

Department of Nano Fusion Technology

Pusan National University
 Ch. 0

Department of Nano Fusion Technology

Pusan National University
 Ch. 0

Department of Nano Fusion Technology

Pusan National University
 Ch. 0

Department of Nano Fusion Technology

Pusan National University
 3D 낸드 격차 벌리는 삼성전자…3세대 세계 최초 양산 (2015. 8.11:전자신문)
◇ 세계 최초 3세대(48단) '256기가비트 3차원 V낸드' 본격 양산
◇ 2세대 32단 보다 데이터 저장 용량 2배, 소비전력 30% 절감
◇ 향후 2배이상 대용량 SSD 제품 출시로 '테라 SSD 대중화' 가속

Department of Nano Fusion Technology

Pusan National University
-256Gb V낸드는 데이터를 저장하는 3차원 셀(Cell)을 기존 32단보다 1.5배 더 쌓아 올려 48단으로 구성.

-셀을 형성할 단층을 48단으로 쌓은 뒤 약 18억개 원형 홀을 수직으로 뚫은 다음 총 853억개 이상 셀을

고속 동작시킴. 이 때 각 셀마다 3개 데이터(3비트)를 저장할 수 있어 총 2560억개 데이터를 읽고 씀.

-3차원 원통형 CTF(3D Charge Trap Flash) 셀 구조, 48단 수직 적층 공정, 3비트 저장기술을 적용.

-기존 32단 양산 설비를 최대한 활용해 제품 생산성을 약 40%나 높여 원가 경쟁력도 대폭 강화.

-이번 256Gb V낸드 칩 하나만으로 스마트폰에 적용하는 32기가바이트(GB) 용량 메모리카드를 만들 수

있음.

-기존 128Gb 칩으로 구성한 솔리드스테이트드라이브(SSD103)와 크기는 같으면서 용량은 갑절 높일 수

있음.

-지난 달 2테라바이트(TB) SSD 제품 출시. 테라급 SSD 대중화를 앞당기기 위해 3세대 V낸드 생산 투자
를 계획대로 추진할 예정.

-전영현 삼성전자 메모리사업부 사장은 “3세대 V낸드 양산으로 글로벌 기업과 소비자에게 더욱 편리한
대용량 고효율 스토리지 솔루션을 제공할 수 있게 됐다”.

Department of Nano Fusion Technology

Pusan National University
A Brief Introduction to NAND Flash

NAND Flash memory stores data in an array of memory

cells made from floating gate transistors. Insulated by an
oxide layer are two gates, the Control Gate (CG, top) and
the Floating Gate (FG, bottom). Electrons flow freely
between the CG and the Channel (see diagram to the right)
when a voltage is applied to either entity, attracted in the
direction to which the voltage is applied. To program a cell,
a voltage is applied at the CG, attracting electrons upwards.
The floating gate, which is electrically isolated by an
insulating layer, traps electrons as they pass through on
their way to the CG. They can remain there for up to years
at a time under normal operating conditions. To erase a cell,
a voltage is applied at the opposite side (the Channel) while
the CG is grounded, attracting electrons away from the
floating gate and into the Channel. To check the status of a
cell, a high voltage is applied to the CG. If the floating gate
holds a charge (electrons are trapped there), the threshold
voltage of the cell is altered, affecting the signal emanating
from the CG as it travels through to the Channel. The
precise amount of current required to complete the circuit
determines the state of the cell. All of this electrical activity
effectively wears out the physical structure of the cell over
time.
Department of Nano Fusion Technology
Pusan National University
Thus, each cell has a finite lifetime, measured in terms of Program/Erase (P/E) cycles and affected
by both process geometry (manufacturing technique) and the number of bits stored in each cell. The
complexity of NAND storage necessitates some extra management processes, including bad block
management, wear leveling, garbage collection (GC), and Error Correcting Code (ECC), all of which
is managed by the device firmware through the SSD controller.

SLC vs. 2-bit MLC vs. 3-bit MLC NAND

NAND technology has been naturally progressing with the needs and expertise of the industry. In
the simplest terms, the data stored in NAND flash is represented by electrical charges that are
stored in each NAND cell. The difference between Single-Level Cell (SLC) and Multi-Level Cell
(MLC) NAND is in how many bits each NAND cell can store at one time. SLC NAND stores only 1
bit of data per cell. As their names imply, 2-bit MLC NAND stores 2 bits of data per cell and 3-bit
MLC NAND stores 3 bits of data per cell.

http://www.samsung.com/global/business/semiconductor/minisite
/SSD/global/html/whitepaper/whitepaper03.html

Department of Nano Fusion Technology

Pusan National University