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Lecture 1_Introduction

Semiconductor Processing

Prof. Sarah Eunkyung Kim


Department of Semiconductor Engineering
Seoul National University of Science and Technology
Note
Evaluation/Grade:

 Exam : Mid-Term Exam (45%) + Final Exam (45%)


− 교과서는 원서를 사용하며, 시험문제는 영어로 제출
− 시험 범위: 중간고사 (week 2~7) / 기말고사 (week 10~14)

 Assignment (10%)

 Attendance (0%)

[중요]

- 중간고사와 기말고사를 치르지 않았거나 두 시험 중 하나라도 0점이면 “F” 학점

- 출석 2/3 이하이면 학사규정 상 “F” 학점

- 커닝 및 수업 방해 등 학습태도가 나쁜 경우 “F” 학점

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Note
Reference Books:

 Silicon VLSI Technology, Plummer

 Silicon Processing for the VLSI Era, Wolf

 S. E. Kim, Lecture note (All figures and tables are from the books, otherwise it is noted.)
− 제공하는 강의 노트는 교과서가 아님!

− 강의 노트(PDF)는 e-class 로 제공함

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Schedule
Week Date Topic Comments

1 02/26 Introduction
- Device fabrication flow
2 03/4 - Plasma Basic & Vacuum
- Silicon Wafer Manufacturing
3 03/11 - Wafer Cleaning
4 03/18 Oxidation
5 03/25 Diffusion

6 04/01 Ion Implantation

7 04/08 Review 활동학습 문제풀이 토론 형식

8 04/15 Assignment 개교기념일 / 과제 제출

9 04/25 Mid-Term Exam

10 04/29 Lithography

11 05/06 VOD (Etching) 공휴일

12 05/13 Etching Review / Thin Film Deposition 1

13 05/20 Thin Film Deposition 2

14 05/27 Metallization
15 06/03 Final Exam
Assignment
 과제 제출 마감일 : 4월 24일 11:00PM
− 마감시간 이후는 제출 불허

 과제 제출 방법 : e-class 과제 Tab

 과제 작성 형식
− 분량: 최대 A4 용자 2장
− Format (Word 기준으로): Font =12 point / 줄 간격=1.5
− 페이지 맨 위에 반드시 이름과 학번 기입

 과제 내용
− 2주차 ~ 7주차 강의 내용 중 하나를 선택
− 선택한 주제 관련하여 보고서 작성
Contents
 Semiconductor Fabrication Flow

 Wafer Size

 Cleanroom Class

 Transistor and Integrated Circuit

 History of IC

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Electronics

Smartphones & Mobiles Automobile Aerospace & Defense

Accelerometer Gyroscope Microphone Barometric Sensor

Electronic
Biomedical
Home
equipment
Appliances

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Semiconductor Device Fabrication

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Semiconductor Unit Processing

 Repetition of various unit processes such as

• Cleaning

• Oxidation

• Ion Implantation
Die (or Chip)
• Diffusion

• Lithography Wafer
• Etching

• Thin Film Deposition

− Physical vapor deposition, Chemical Vapor Deposition, Electroplating, etc.)

• Chemical Mechanical Polishing

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반도체 8대 공정 ?

반도체 단위 공정 반도체 8대 공정 (온라인에서……)

① 세정 (Cleaning) 1) 웨이퍼 공정

② 이온 주입 (Ion Implantation) 2) 산화 공정

③ 확산 (Diffusion) 3) 포토리소그래피 공정

④ 산화 (Oxidation) 4) 식각 공정

⑤ 리소그래피 (Lithography) 5) 박막 공정

⑥ 식각 (Etching) 6) 금속배선 공정

⑦ 박막 증착 (Thin Film Deposition) 7) EDS(Electrical Die Sorting) 공정

⑧ 화학적 기계적 연마 8) 패키징 공정


(Chemical Mechanical Polishing)

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Semiconductor Fabrication Flow

0. Semiconductor Material and Device Basics

6. System Assembly

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반도체 8대 공정 ?

2) 산화 공정
1) 웨이퍼 공정 8) 패키징 공정
3) 포토리소그래피 공정
4) 식각 공정
5) 박막 공정

6) 금속배선 공정 6) EDS(Electrical Die Sorting) 공정

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Semiconductor Fabrication Flow

Chip (Die) Packaged die


Bare Wafer

transistor
Interconnect

[Cross-sectional view]

(Source: Lecture by M. Horowitz, J. Plummer, R. Howe, MOS Transistors, CMOS Logic Circuits, and Cheap, Powerful Computers)
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Wafer Size
Wafer diameter

Number of Chips (* estimation base on 1.5 x 1.5 cm chip size)

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Cleanroom Class

 Definition: Number of particles (which are larger than 0.5 µm diameter) per ft3

 United States federal standard

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3 Factors in Semiconductor Processing

Circuit Design
& Architecture

Materials Fabrication
(Si, GaAs, SiC…) (Processing)

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Transistors and Integrated Circuits (IC)

 Transistor is an electronic device  Integrated circuits are a very small single


used to control the flow of structure assembly of electronic
electricity. (the smallest unit) components containing many circuits and
functions on a chip. (an entire circuit built
into a single component)

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History of Transistor and Integrated Circuit

① Vacuum tube
 1874: Solidstate rectifier by Braun
 1906: Triode vacuum tube by DeForest

② 1947 First transistor (Bardeen, Shockley, and Brattain at Bell Labs)


 1947: Bipolar transistor bu Brattain and Bardeen
 1956: Bardeen, Brattain, Shockley – Nobel Prize

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History of Transistor and Integrated Circuit
③ 1954 Bipolar Junction Transistor (Gordon Teal at Texas Instruments)

④ 1958 First Integrated Circuit (Jack Kilby at Texas Instruments)

- 2000 Nobel Prize


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History of Transistor and Integrated Circuit
⑤ 1959 Planar transistor
(Robert Noyce at Fairchild Semiconductor)

⑥ 1959 Metal Oxide Semiconductor field Effect Transistor, MOSFET (Mohamed Atalla
and Dawon Kahng at Bell labs)

⑦ 1961 First Planar IC (Robert Noyce at Fairchild Semiconductor)

⑧ 1963 Complementary Metal Oxide Semiconductor, CMOS


(C. T. Sah and Frank Wanlass at Fairchild Semiconductor)

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History of Transistor and Integrated Circuit

⑨ 1969 Intel's first commercial MOS device (1101 256-bit RAM)


[1968 Intel was founded by Robert Noyce and Gordon Moore.]

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Gordon Moore’s Prediction

"Cramming more components onto integrated circuits" (Electronics Magazine, 19 April 1965)

“The complexity for min. component costs has increased at a rate of roughly a factor of
two per year .....”

The number of transistors on a chip doubles about every 18 months…

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Transistor per Die

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Moore’s Law

(Source: https://en.wikipedia.org/wiki/Transistor_count)
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CMOS (Complementary Metal Oxide Semiconductor)

 “C" refers to the fact that the design uses pairs of transistors (NMOS and PMIOS) for
logic functions, only one of which is switched on at any time.

 “MOS" refers the nature of the fabrication process to build CMOS.

 CMOS chips include microprocessor, microcontroller, SRAM, and other digital logic
circuits

 The main advantage of CMOS over NMOS:

• Is the much smaller power dissipation

• Produces much less heat than other


forms of logic
(Ref: http://en.wikipedia.org/wiki/CMOS)

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MOSFET Structure

(2) Voltage Difference

(1) Applied Voltage

source drain
gate

M metal
O gate oxide

T n+
S
n+

p-Si
n-channel
FE electric field
(3) Current Flows

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Transistor and Interconnect Structure

[MIM Capacitor]

Metal
Interconnect
Insulator (Dielectric)

Metal or Semiconductor

Contact

Transistor

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Transistor and Interconnect Structure

(Source: Samsung Exynos, 14nm FinFET, TECHINSIGHTS, 2015)


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Semiconductor Device Structure

(Ref. : Mark Bohr, Intel Senior Fellow, Intel Developer Forum 2012) 29

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