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EE202-S24 w02 2 Sinusoids-And-Phasors
EE202-S24 w02 2 Sinusoids-And-Phasors
phasors
Week 2 – Lecture 2:
Sinusoids and Phasors
Abdurrahman Gümüş
Assistant Professor
Electrical and Electronics Engineering
February 29, 2024
Monday Thursday
10:30 – 12:00 office hour 14:00 – 15:00 problem solving session (Z41)
15:00 – 16:30 office hour
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EE202-S24_w02_1_sinusoids-and-
phasors
Phasors
We transform the sinusoid from the time domain to the phasor domain
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EE202-S24_w02_1_sinusoids-and-
phasors
Phasors
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EE202-S24_w02_1_sinusoids-and-
phasors
Inductor:
Since
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EE202-S24_w02_1_sinusoids-and-
phasors
Phasor transformation
Since
Inductor:
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EE202-S24_w02_1_sinusoids-and-
phasors
Capacitor:
Voltage across capacitor is
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Capacitor:
Phasor diagram for the capacitor Current and voltage are 90° out of phase
I leads V
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EE202-S24_w02_1_sinusoids-and-
phasors
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Impedance
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EE202-S24_w02_1_sinusoids-and-
phasors
Impedance
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Impedance
ZL = 0 and ZC → ∞
ZL → ∞ and ZC = 0
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EE202-S24_w02_1_sinusoids-and-
phasors
Impedance
ZL = 0 and ZC → ∞
ZL → ∞ and ZC = 0
Impedance
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EE202-S24_w02_1_sinusoids-and-
phasors
Impedance
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Impedance
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EE202-S24_w02_1_sinusoids-and-
phasors
Admittance
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Admittance
G≠1∕R
as it is in resistive circuits
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EE202-S24_w02_1_sinusoids-and-
phasors
For KVL, let v1, v2, … , vn be the voltages around a closed loop
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Phasors REMINDER
The idea of phasor representation is based on Euler’ s identity
We may regard cosϕ and sinϕ as the real and imaginary parts of ejϕ
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EE202-S24_w02_1_sinusoids-and-
phasors
Phasors REMINDER
For a sinusoid v(t) = Vm sin(ωt + φ)
where
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EE202-S24_w02_1_sinusoids-and-
phasors
Phasors REMINDER
We transform the sinusoid from the time domain to the phasor domain
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We know
Because
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EE202-S24_w02_1_sinusoids-and-
phasors
If i1, i2, … ,in are the currents leaving or entering a closed surface in a
network at time t
If I1, I2, …, In are the phasor forms of the sinusoids i1, i2, …, in
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Once we have shown that both KVL and KCL hold in the
frequency domain,
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EE202-S24_w02_1_sinusoids-and-
phasors
Impedance Combinations
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Impedance Combinations
Voltage division
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EE202-S24_w02_1_sinusoids-and-
phasors
Impedance Combinations
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Impedance Combinations
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EE202-S24_w02_1_sinusoids-and-
phasors
Impedance Combinations
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Impedance Combinations
where
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EE202-S24_w02_1_sinusoids-and-
phasors
Example
Determine vo(t)
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Example
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EE202-S24_w02_1_sinusoids-and-
phasors
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Voltage division
Converting back to
time domain
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EE202-S24_w02_1_sinusoids-and-
phasors
Example:
Find v(t) and i(t)
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vs = 10 cos4t
ω=4
Total impedance
Current
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EE202-S24_w02_1_sinusoids-and-
phasors
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Phase Shifters
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EE202-S24_w02_1_sinusoids-and-
phasors
Phase Shifters
Total impedance
where
Phase shift
Phase Shifters
In (a),
Since the output voltage Vo across the resistor
is in phase with the current,
Vo leads (positive phase shift) Vi
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EE202-S24_w02_1_sinusoids-and-
phasors
Phase Shifters
In (b),
- Output is taken across the capacitor
- Current I leads the input voltage V by some θ
- But output voltage vo(t) across the capacitor
lags (negative phase shift) the input voltage vi(t)
Values from
example:
Series RC shift circuits
(a) leading output
(b) lagging output
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EE202-S24_w02_1_sinusoids-and-
phasors
Phase Shifters
For this reason, these simple RC circuits are used only when small
amounts of phase shift are required
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Phase Shifters
When RC networks are cascaded, they provide a total phase shift equal
to the sum of the individual phase shifts
In practice, the phase shifts due to the stages are not equal, because the
succeeding stages load down the earlier stages
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EE202-S24_w02_1_sinusoids-and-
phasors
Phase Shifters
When RC networks are cascaded, they provide a total phase shift equal
to the sum of the individual phase shifts
In practice, the phase shifts due to the stages are not equal, because the
succeeding stages load down the earlier stages
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