LSI LOGIC DESIGN

CHAPTER 6
Layout Design

JUNE 30, 2020

PHAM TUONG HAI
QUALITY ASSESSMENT & TRAINING DEPARTMENT
RENESAS DESIGN VIETNAM CO., LTD.
RENESAS ELECTRONICS CORPORATION
CHAPTER 6. Layout Design

6.1. Overview of Layout Design.

6.2. Cell and Library.

6.3. Understand about Layout Design.

6.4. Chip Design Planning.

6.5. Block and TOP Level Layout Design.

6.6. Process Defect and Yield.

Page 2
6.1 Overview of Layout Design

Page 3
LSI Design Flow
System spec

System design Layout Design

Chip Design Planning
Logic design
Layout Design (PnR) Bump/Pad & IO
Integration
Test design
Post-Layout Verification
Logic Timing Physical
Layout design Verification Verification Verification

DRC LVS EM / RDROP ESD

(Design (Layout (Electro Migration (Electro-
Rule vs & Static
Check) Schematic) Voltage Drop) Discharge)
Mask making

Page 4
Overview of Layout Design Verilog Gate-level netlist
(with DFT circuit)

Layout Design
IP CELL
libraries libraries Chip Design Planning
Macro
libraries Layout Design (PnR) Bump/Pad & IO
Integration

Post-Layout Verification
Design Specifications Logic Physical
Timing
- Technology (45mn, 28nm, …) Verification Verification
Verification
- Chip size, Operating cond.
- Frequency (CPU, GPU, …)
- Power supply, consumption DRC LVS EM / RDROP ESD
- Reliability requirements (Design (Layout (Electro Migration (Electro-
Rule vs & Static
- …
Check) Schematic) Voltage Drop) Discharge)

Chip Design Database

To Manufacturing Processes
Page 5
6.2 Cell and Library

Page 6
What is a Cell?
A cell is macro or functional unit that performs common operations and is used
to build more complex logic blocks.

Examples:
- Standard cells: Inverter, NAND, NOR, Flip-Flop, Latches and Buffers.
- Macro cells: ADC (Analog to Digital converter), DAC,
THS (Thermal sensor), USB, PCI
PLL (Clock pulse generator)

Page 7
What is a (Cell) Library?
A cell library often refers to a collection of cells:
- Standard cell library (Primitive cell Library)
- I/O cell library
- Memory (Compiled memory, Fixed size memory)
- Analog (ADC, DAC, PLL, USB, THS)

Cell library consists of :

- Schematics (Transistor level circuit. Usually, not released)
- Frontend model (Verilog, VHDL, Liberty(.DB), other support libraries)
- Backend Model (LEF, ASTRO/Milkyway, GDS(Layout), CDL)
LEF and ASTRO are cell information which shows locations of ports,
cell size, wiring prohibition area, … used for Place-and-Route.
LEF is often used for Cadence P&R tool
ASTRO/MILKYWAY is often used for Synopsys P&R tool
GDS is a design database format for design transfer
CDL is format of design circuit netlist, used for LVS verification (Layout-
versus-Schematic), or ESD verification, …

Page 8
Example of Library Model (INVERTER)
Verilog (.v) Liberty (.lib) LEF (.lef)
`ifdef TS_OFF cell(TCAINVXC){ MACRO TCAINVXC
`else area : 3.0; CLASS CORE ;
`timescale 1ps/1ps cell_leakage_power : a; FOREIGN TCAINVXC 0.000 0.000 ;
`endif cell_footprint : INVX_; SIZE 0.840 BY 2.520 ;
SYMMETRY Y X ;
`celldefine pin(YB){
ORIGIN 0.0 0.0 ;
`ifdef verifault function : "!(A)"; SITE CORE009 ;
`suppress_faults max_fanout : 50; PIN A DIRECTION INPUT ;
`enable_portfaults max_capacitance : b; USE SIGNAL ;
`endif capacitance : 0.000000; AntennaGateArea 0.14 LAYER M1 ;
direction : output; AntennaPartialMetalArea 0.104 LAYER M1 ;
`ifdef FAST_FUNC internal_power() { PORT
`delay_mode_zero related_pin : "A"; LAYER M1 ;
`else fall_power(pwr_tin_oload_3x3){ RECT 0.170 0.970 0.350 1.550 ;
`delay_mode_path index_1 (“ , , "); END
`endif index_2 (“ , , "); END A
PIN YB DIRECTION OUTPUT ;
values(“ , , ", \
USE SIGNAL ;
module TCAINVXC( A,YB ); "- , , ", \ AntennaPartialMetalArea 0.242200 LAYER M1 ;
output YB; “ , , "); AntennaDiffArea 0.331200 LAYER M1 ;
input A; } PORT
reg notifier; rise_power(pwr_tin_oload_3x3){ LAYER M1 ;
index_1 (“ , , "); RECT 0.490 0.380 0.630 2.110 ;
not (YB,A); index_2 (“ , , "); END
values(“ , , ", \ END YB
`ifdef FAST_FUNC “ , , ", \ ………
`else “ , , ");
……. }
….
Actual numbers are deleted form original .lib

Page 9
Example of Library Model (INVERTER) (cont’d)
PnR Layout view Logic symbol) CDL model (.cdl) (aaa~ddd is MOS size)

.SUBCKT TCAINVXC A YB
XI2 A YB VDD VSS / TCXINV wn=aaa u wp=bbb u
XI0 A YB VDD VSS / TCXINV wn=ccc u wp=ddd u
.ENDS

(0.840, 2.520) Detailed layout Schematic view (Circuit)

(0,0)

Page 10
6.3 Understand about Layout Design

Page 11
Layout Methodology
1) Individual design method
Design with interactive mode EDA tool (interactive design).
Eg: applied in custom layout design, standard cell / Analog layout design, ...

2) Master slice method (Gate Array Method) P&R

Common master layout with buried transistors is ready and automatic wiring tool is
applied to do layout.
The development cost is small thanks to the buried gate-array.
Since base wafers are already prepared, the manufacturing period is short.

3) Cell-based method P&R

P&R area of cell/module are changeable.
It is necessary to minimize the chip size.

4) Hierarchical cell-based method P&R

A hierarchical design of method (3) where logic is split from the top down, and layout is
done from the bottom-up.

Page 12
Standard Cell Structure of Cell-based Method

The width of the cell is changeable.

(integral multiples in X wiring grid)

The height of the cell is normally constant (in

a specific library of a specific technology, and
is integral multiples in Y wiring grid)

The signal port is “on grid”.

(for route-ability)

Power supply ports are in fixed locations in

the cell (normally at top and bottom of the
cell). Y location is same to all cells.

Metal wirings can run over cells.

Page 13
Cell-based Method
Cells can be arbitrarily placed - Automatic P&R is applied - Multi-layer metals are used.

Analog IOs and digital IOs are separated to

avoid the digital noise.

Bonding PAD

IO cell (free placement)

Internal cell row

(Standard cell placement area, flat
placement)
IP modules areas (memory and
analog, etc.., free placement)

Al.
(wiring can run in free channels and
through over cells)

Page 14
 Hierarchical Cell-based Method
The standard cell placement area is done layout hierarchically depending on the hierarchical logical
structure of the gate level netlist - Automatic P&R is applied.

Hierarchical logic B Hierarchical logic A

Bonding PAD

IO cell (free placement)

Internal cell row

(Standard cell placement area, flat
placement)
IP modules areas (memory and
analog, etc., free placement)

All areas are for the wiring areas.

(wiring can run in free channels and
Hierarchy block A and B are done PnR separately and though over cells)
are called into TOP design as a cell (Macro, block)

Page 15
6.4 Chip Design Planning

Page 16
Package Types
SiP (System in Package)
Wire Bonding Memory

SoC chip

SOC
SoC: System On a Chip
SiP (System in Package)
Au Stud Bump + Wire Bonding Memory

Package routing

Au Stud Bump SOC (flip chip)

PoP (Package on Package) Memory

Au Stud Bump SOC (flip chip)

Page 17
 Example of package routing for Flip Chip PAD
Flip Chip PAD Design
“STAGGER” Pad placement SoC using Stagger PAD

P
A
PAD is arranged D
around the chip

(Layout view) PAD arrangement in Chip Layout

“STRAIGHT” Pad placement

Page 18
Flip Chip BUMP Design Example of Package routing for Flip Chip Bump design

“STAGGER” Bump placement

IO cell Bump Redistribution layer

“STRAIGHT” Bump placement

Chip Layout view Bump structure

Page 19
Chip Size and BUMP/PAD Planning (1) Package type and size is decided

PKG

Ball
mother board
(4)
Block size is estimated to
Chip
feedback to chip size decision

(3)
(2)
Analog Hard macro is planned.
Bump/Pad is roughly arranged. Chip size is targeted.
Package routing is planned
(Package routing is trialed and
feedback to bump/pad arrangement)

Bumps Eg. Chipsize:

10mm[]

Analog
macros Wiring area
e.g.. About 10mm

Page 20
BUMP Assignment - Block Placement - Power Arrangement
After chip size is decided and position of Analog macros are planned:
è Make BUMP assignment and Block placement
è Arrange Power areas and their position

Page 21
Early Power Analysis Big voltage drop:
- More PG bumps?
Power consumption for each block is estimated. - Block position?
- PG supply?
Rough power analysis (IR drop, power distribution, …) is executed.
- How to reduce drop?
è Bump assignment may be adjusted
è Power structure and Power supplying plan are made
Ch ip
CO RE

83mA 83mA 245mA 245mA

53mA
47mA
162mA 53mA

245mA 245mA
80mA 80mA

15mA

72mA

15mA

hamsa

Fig VDD/VSS Core bump Image Fig temporary IR-Drop

Page 22
6.5 Block and TOP Level Layout Design

Page 23
PnR (Placement & Routing) General Flow

(from FE design)

By applying “Timing design

Floor planning constraints” to PnR tool, the
Power supply design reduction of layout design TAT
(turn around time) is realized.

Layout Extraction
* for Signal Integrity and Timing Check
In actual design activity,
several ECOs will happen.
(average 4~8 times re-layout)
Post-Layout Verification

Page 24
PnR General Flow (cont’d)
IO integration
IO placement file
Auto routing I/O placement
P&R (Pad placement)
Place and Route

Analog macros
placement file
PG mesh

Auto placement P/G connection & Floor planning

P/G mesh wiring

Page 25
Floor Planning
In case of Hierarchical PnR design:

- Chip TOP Floor Planning: decide size (area)

and shape for each child block.

- Each block is applied the whole design cycle

(FP à place à route à timing and signal
integrity check) .

- Block interface model is made for each block.

Block size and shape is updated to/from TOP
design.

- TOP design will use block interface model for

its design cycle (FP à Place à Route à
Timing and Signal integrity check).
Top Floor Plan:
- Hierarchical blocks, Hard macros,
and I/O cells are placed.
- The remained area (in gray) is
reserved for logic cells on TOP level.

Page 26
Power Supply Design
“Power supply design” targets to establish power routing to keep specifications of design rule (for
voltage drop, electro-migration, etc..) and to supply sufficient current to each cell, considering to
minimize the chip size.
<Design approach>
I/O
1) Manual design
The designer decides number of wire straps and
their width, then uses layout editor and the P&R
tool to draw PG mesh manually.

Block 2 2) Semi-automatic design

Block 1
Use Angel@Ring (Renesas in-house tool) and pre-
determined power routing cells.
HM
3) Automatic power design tool
Developed and implemented to EDA tools
EDA tools will decide PG mesh pattern, number
of wire straps, metal width, … and do the PG
routing automatically

Page 27
PnR - Placement
TOP Placement Block placement
- IO, Analog macros, and RAM/ROM are placed
- RAM/ROM, Analog macros are placed
- Block shapes are decided.
- Module ports are placed
- Power/Ground grid is designed.
- Power/Ground grid is implemented.
- Position to place pins for each block is planed.

Page 28
PnR - Placement Optimization
Prerequisite: Design after floor-planning.
In a timing-driven design, placement and optimization step performs:
- Logic standard-cells are automatically placed by EDA tool.
- A virtual ideal-clock-tree is build for timing optimization.
- Connections are virtually routed
- Logic can be optimized and standard cells can be changed and/or moved to other places to resolve routing
congestion, reduce timing violations, or to perform power optimization.
- Design rule check (DRC) and timing check are performed and violations are resolved automatically, e.g.. by
replacing or moving cells .
Example of Cell density map

Page 29
PnR - Clock Design
Analyze clock structure
Clock distribution module

CPGM Insert main clock buffers of the clock tree

cpgmona

Manually place clock cells of clock

distribution modules

Page 30
PnR - Timing Driven Design
§ Timing driven design means that Automatic P&R tool designs layout
considering timing constraints specified at logic design.

§ Timing constraint means that timing (path delay value, setup time, hold time)
between clock port and data port of flip-flop.

Constraint of Setup time: Data should reach by (the reach time of clock- ts)
Constraint of Hold time: Data should not change by (the reach time of clock + th)

Page 31
PnR - Timing Driven Design (cont’d)

Page 32
Layout Extraction (for Signal Integrity and Timing Check)
RC extraction means that the extraction of wiring loads (stray capacitance and resistance) from layout after P&R.

The parasitic capacitance changes depending on peripheral wiring (with/ without adjacent wire, top and bottom,
coarse or dense).

Page 33
Timing Verification
Timing verification is done based on post layout delay data extracted from post layout wire load.
Minimum accuracy error to actual LSI (Si) is required.

RC
Layout Timing verification
Wire load data Wire load delay data
extraction (RC information) (SDF)
Static Timing

c
Analysis (STA)
Layout Delay Library
Calculation information
If necessary,
Layout data Cell type & Function Dynamic Timing
(GDSII) (Tools: PrimeTime, Cell delay model Analysis (DTA)
SignalStorm,…) Ideal wire load model
(Tools: PrimeTime,
NC-Verilog, etc.. )
P&R tool Post-Layout
Gate level Netlist
Clock design
(Verilog netlist)
Timing driven design Timing
verification result

Timing Gate-level netlist Constraints Timing

NG
(setup timing, hold
constraints (with DFT circuit) for PnR ECO timing, transition, …)

Page 34
6.6 Process Defect and Yield

Page 35
Patten Defect and Yield
Interconnect
ð bad die
short !!

2.0 um
defect ~0.1um
0.4um
Even if we have 1 defect/wafer/step, Important steps > 100

A lot of bad die !!

bad die

・・・・・・

Process Step #1 #2

Page 36
 Patten Defect and Yield (cont’d)
𝑵𝒖𝒎𝒃𝒆𝒓 𝒐𝒇 𝑮𝒐𝒐𝒅 𝑫𝒊𝒆𝒔
𝒀𝒊𝒆𝒍𝒅 = ×𝟏𝟎𝟎
𝑻𝒐𝒕𝒂𝒍 𝑵𝒖𝒎𝒃𝒆𝒓 𝒐𝒇 𝑫𝒊𝒆𝒔

To analogy, in defect size on a wafer:

1 piece of foreign particle such
as a tip of hair dropped in the
area of 216mx216m.

Fatal defect ~0.1um

0.4um
Even if we have 1 defect/wafer/step… Bad chip

Yield ~70%
Important steps
~100

Page 37
Contamination Reduction
Human is one of the origin of contamination.
To reduce the contamination from human, we put a special cloth
and all wafer process steps are done in the clean room.

From SILICON VLSI TECHNOLOGY

Page 38
Yield Expression
If the good chips can be gotten randomly in a wafer, the yield is
expressed by the following formula.

Y = exp[-(S x D)]

Where S is the area of the chip (cm2) and D is a defect density(/cm2)

Example:
D = 1 /cm2
S = 6.0 mm x 6.0 mm = 36 mm2 = 0.36 cm2
Y = exp[-(0.36 x 1)] = 0.6976 ð Yield = 69.8%

Page 39
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