Work sheet for 5th year students

1. The circuit of the given figure 2 realizes the function.

a. Y = (A’ + B’) C + (DE)’

b. Y = A’ + B’ + C’ + D’ + E’
c. Y = AB + C +DE
d. Y = AB + C (D + E)
2. The Boolean theorem observed by interchanging the position of the logical operator or the
values of 0 and 1 is called______________
a. Quadruples
b. Doubles
c. Duals
d. Algebraic theorem
3. As the number of flip flops are increased, the total propagation delay of
a. Ripple counter increases but that of synchronous counter remains the same
b. Both ripple and synchronous counters increase
c. Both ripple and synchronous counters remain the same
d. Ripple counter remains the same but that of synchronous counter increases
4. The counter in the given figure 3 below is
a. Mod 3
b. Mod 6
c. Mod 7
d. Mod 8
 5. A J-K flip-flop with J = 1 and K = 1 has a 10 kHz clock input. The Q output is
a. Constantly HIGH
b. Constantly LOW
c. A 10kHz square wave
d. A 5kHz square wave
6. A pulse is applied to each input of an exclusive-OR gate. One pulse goes HIGH at t=0 and
goes back LOW at t=1 millisecond. The other pulse goes HIGH at t= 0.8 millisecond and
goes back LOW at t=3 millisecond. The output pulse can be described as
a. It goes HIGH at t=0 and back LOW at t= 3 millisecond.
b. It goes HIGH at t=0 and back LOW at t= 0.8 millisecond.
c. It goes HIGH at t=1 millisecond and back LOW at t= 3 millisecond
d. b and c
7. a method of generating carry for fast addition is called __________
a. Decoder carry
b. Multiplexer carry
c. Look ahead carry
d. All
8. The minimized equation for the following logic function using K-map is_____

F (A, B, C, D) = ∑
m
(0 , 1 ,2 , 3 ,5 ,7 , 8 , 9 , 11,14 )

a. AB’CD + BC’ + BD’ + A’D’ + AC’D’

b. AB’C’D + A’C + B’D’ + A’C + A’B
c. AB’C’D + A’C + B’D’ + A’C +A’B
d. BCD + ABC + B’C’D + A’B’D
9. In 16 –bit 2’s complement representation, the decimal number -28 is
a. 1111 1111 0001 1100
b. 0000 0000 1110 0100
c. 1111 1111 1110 0100
d. 1000 0000 1110 0100
10. Original ASCII coding scheme uses_____ bits for coding 128 different characters
a. 6
b. 7
c. 8
d. 16
11. In the circuit in the figure below, S2, S1, S0 are select lines and X7 to X0 are input lines.
S0 and X0 are LSBs. The output Y is
a. 𝑨⊕𝑩
b. A+B
c. (A⊕B)’
d. C.(A.B)

12. In the figure show below a 4-bit serial in parallel out right shift register. The initial contents
as shown are 0110. After 3 clock pulses the contents will be
a. 0000
b. 1010
c. 0101
d. 1111

13. If the initial state of a 4-bit up counter is 0110, what state will it be after 15 clock pulses?
a. 1111
b. 1001
c. 0101
d. 0001
14. Which of the following digital logic circuits can be used to add more than 1 – bit
simultaneously?
a. Full – adder
b. Ripple – carry adder
c. Half – adder
d. Serial adder
15. What will be the output from a D flip – flop if the clock is low and D = 0?

a. 0
b. 1
c. No change
d. Toggle between 0 and 1
16. A priority encoder has four inputs I0, I1, I2, and I3 where I3 has the highest priority and I0
has the least priority. If I2 = 1, what will be the output?

a. 00
b. 01
c. 10
d. 11
17. Which of these flip – flops cannot be used to construct a serial shift register?
a. D – flip flop
b. SR flip – flop
c. T flip – flop
d. JK flip – flop
18. What input should be given to “S” when SR flip – flop is converted to JK flip – flop?

a. K.Q
b. K.Q
c. J.Q
d. J.Q
19. which of the following is true about D flip-flop
a. D=HIGH a SET state
b. D=LOW a RESET state
c. Q follows D at the clock edge.
d. To convert S-R flip-flop into a D flip-flop an inverter will be added.
e. None of the above
20. Which of the following is true about operation of a priority encoder?
a. It generates a binary code based on the bit position of the highest priority input.
b. It is commonly used in systems that handle interrupt requests.
c. It determines which device has the highest priority and needs immediate
attention.
d. a and b
e. All
21. _____ is a digital circuit that is capable of storing only a single bit.
a. Flip-flop
b. NOR gate
c. XOR gate
d. Register
22. A logical sum of multiple logical products is called as:
a. NAND operation
b. OR operation
c. POS
d. SOP
23. Identifiy the logic ciruit equation from the given

24. In 1st Complement a number to be subtracted is known as………

a. Subtrahend
b. Minuend
c. carry
d. none

25. The address / data bus in 8085 is __________

a. Multiplexed
b. Demultiplexer
c. decoded
d. loaded

26. The type of register in which data is entered into it only one bit at a time, but has all data
bits available as output, is

a. serial in serial out register

b. parallel in serial out register
c. serial in parallel out register
d. parallel in parallel out register
27. The type of register, in which we have access only to left most and right most flip flop is

a. shift left and shift right registers

b. serial in serial out register
c. parallel in serial out register
d. serial in parallel out register

28. If a counter is connected using 6 flip flop then the maximum number of states that the
counter can count are

a. 6
b. 8
c. 256
d. 64

29. Binary ladder network is better than resistive divider for D/A conversion ,because

a. It requires lesser number of resistors

b. it requires resistor having two values only
c. It is cheaper
d. It gives better accuracy

30. Why the decimal number system is also called as positional number system?

a. Since the values of the numbers are decided by multiplying the values.
b. Since the values of the numbers are decided by the weight of the values.
c. Since the values of the numbers are decided by adding the values.
d. Since the values of the numbers are decided by the position of the values.

31. A digit in base R will have a range from ____________

a. 1 to R-1
b. 0 to R-1
c. 1 to R+1
d. 0 to R+1

32. Which method is used to convert a number from an octal base to decimal base?

a. Direct conversion method

b. Decimal equivalent method
c. Octal equivalent method
d. Positional notation method
33. If a three variable switching function is expressed as the product of maxterms by
f(A,B,C) =II(0,3,5,6) then it can also be expressed as the sum of minterms by

a. II(1,2,4,7)
b. ∑(0,3,5,6)
c. ∑(1,2,4,7)
d. ∑(1,2,3,7)

34. In the case of a 100 kHz clock frequency, we can enter 16 bits serially into a shift register
in:

a. 180 micro-sec
b. 170 micro-sec
c. 160 micro-sec
d. 150 micro-sec

35. It is a very useful combinational circuit used in communication systems

a. Parity bit Checker

b. Parity bit Generator
c. Parity bit
d. Both (A) and (B)

36. It compares two n-bit values to determine whether one of them is greater or if they are
equal

a. Calculator
b. Multiplexer
c. Comparator
d. None of the above