VLSI

VLSI Testing
Testing

Lecture
Lecture 2:
2: Yield
Yield &
& Quality
Quality

Dr. Vishwani D. Agrawal

James J. Danaher Professor of Electrical and
Computer Engineering
Auburn University, Alabama 36849, USA
vagrawal@eng.auburn.edu
http://www.eng.auburn.edu/~vagrawal

IIT Delhi, July 24, 2012, 4:00-5:00PM

Copyright 2001, Agrawal & Bushnell Lecture 2 Yield & Quality 1

 Contents
Contents
 Yield and manufacturing cost
 Clustered defect yield formula
 Defect level
 Test data analysis
 Example: SEMATECH chip
 Summary
 Problems to solve

Copyright 2001, Agrawal & Bushnell Lecture 2 Yield & Quality 2

 VLSI
VLSI Chip
Chip Yield
Yield
 A manufacturing defect is a finite chip area with
electrically malfunctioning circuitry caused by
defects created by the fabrication process.
 A chip with no manufacturing defect is called a good
chip.
 Fraction (or percentage) of good chips produced in a
manufacturing process is called the yield. Yield is
denoted by symbol Y.
 Cost of a chip:
Cost of fabricating and testing a wafer
———————————————————————
Yield x Number of chip sites on the wafer

Copyright 2001, Agrawal & Bushnell Lecture 2 Yield & Quality 3

 Clustered
Clustered VLSI
VLSI Defects
Defects

Good chips
Faulty chips

Defects
Wafer
Unclustered defects Clustered defects (VLSI)
Wafer yield = 12/22 = 0.55 Wafer yield = 17/22 = 0.77

Copyright 2001, Agrawal & Bushnell Lecture 2 Yield & Quality 4

 Yield
Yield Parameters
Parameters
 Defect density (d ) = Average number of defects per
unit of chip area
 Chip area (A)
 Clustering parameter (α)
 Negative binomial distribution of defects,
p (x ) = Prob (number of defects on a chip = x )
 (+x ) (Ad /) x
= ─────── . ──────────
x !  () (1+Ad /) +x
where Γ is the gamma function
= 0, p (x ) is a delta function (maximum clustering)
= ∞ , p (x ) is Poisson distribution (no clustering)
Copyright 2001, Agrawal & Bushnell Lecture 2 Yield & Quality 5
 Yield
Yield Equation
Equation
Y = Prob ( zero defect on a chip ) = p (0)


Y = ( 1 + Ad /  )

Example: Ad = 1.0, α = 0.5, Y = 0.58

– Ad
Unclustered defects: α = ∞, Y = e

Example: Ad = 1.0, α = ∞, Y = 0.37

too pessimistic !
Copyright 2001, Agrawal & Bushnell Lecture 2 Yield & Quality 6
Defect
Defect Level
Level or
or Reject
Reject Ratio
Ratio
 Defect level (DL) is the ratio of faulty chips among
the chips that pass tests.
 DL is measured as parts per million (ppm).
 DL is a measure of the effectiveness of tests.
 DL is a quantitative measure of the manufactured
product quality. For commercial VLSI chips a DL
greater than 500 ppm is considered unacceptable.

Copyright 2001, Agrawal & Bushnell Lecture 2 Yield & Quality 7

 Determination
Determination of
of DL
DL

 From field return data: Chips failing in the field

are returned to the manufacturer. The number of
returned chips normalized to one million chips
shipped is the DL.
 From test data: Fault coverage of tests and chip
fallout rate are analyzed. A modified yield model
is fitted to the fallout data to estimate the DL.

Copyright 2001, Agrawal & Bushnell Lecture 2 Yield & Quality 8

 Modified
Modified Yield
Yield Equation
Equation
 Three parameters:
 Fault density, f = average number of stuck-at
faults per unit chip area
 Fault clustering parameter, β
 Stuck-at fault coverage, T
 The modified yield equation:

Y (T ) = (1 + TAf / ) – 
Assuming that tests with 100% fault coverage
(T = 1.0) remove all faulty chips,
–
Y = Y (1) = (1 + Af / )
Copyright 2001, Agrawal & Bushnell Lecture 2 Yield & Quality 9
 Defect
Defect Level
Level
Y (T ) – Y (1)
DL (T ) = ———————
Y (T )


(  + TAf )
= 1 – ——————

(  + Af )
Where T is the fault coverage of tests, Af is the
average number of faults on the chip of area A, β
is the fault clustering parameter. Af and β are
determined by test data analysis.

Copyright 2001, Agrawal & Bushnell Lecture 2 Yield & Quality 10

Example:
Example: SEMATECH
SEMATECH Chip
Chip
 Bus interface controller ASIC fabricated and
tested at IBM, Burlington, Vermont
 116,000 equivalent (2-input NAND) gates
 304-pin package, 249 I/O
 Clock: 40MHz, some parts 50MHz
 0.8m CMOS, 3.3V, 9.4mm x 8.8mm area
 Full scan, 99.79% fault coverage
 Advantest 3381 ATE, 18,466 chips tested at
2.5MHz test clock
 Data obtained courtesy of Phil Nigh (IBM)

Copyright 2001, Agrawal & Bushnell Lecture 2 Yield & Quality 11

 Test
Test Coverage
Coverage from
from
Fault
Fault Simulator
Simulator
Stuck-at fault coverage, T

Vector number

Copyright 2001, Agrawal & Bushnell Lecture 2 Yield & Quality 12

 Measured
Measured Chip
Chip Fallout
Fallout
Measured chip fallout, 1 – Y (T )

Vector number

Copyright 2001, Agrawal & Bushnell Lecture 2 Yield & Quality 13

 Model
Model Fitting
Fitting
Chip fallout vs. fault coverage
Chip fallout and computed 1 – Y (T )

Y (1) = 0.7623

Measured chip fallout

Y (T ) for Af = 2.1 and  = 0.083

Stuck-at fault coverage, T

Copyright 2001, Agrawal & Bushnell Lecture 2 Yield & Quality 14

 Computed
Computed DL
DL
237,700 ppm (Y = 76.23%)
Defect level in ppm

Stuck-at fault coverage (%)

Copyright 2001, Agrawal & Bushnell Lecture 2 Yield & Quality 15

 Summary
Summary
 VLSI yield depends on two process parameters, defect
density (d ) and clustering parameter (α).
 Yield drops as chip area increases; low yield means
high cost.
 Fault coverage measures the test quality.
 Defect level (DL) or reject ratio is a measure of chip
quality.
 DL can be determined by an analysis of test data.
 For high quality: DL << 500 ppm, fault coverage ~ 99%

Copyright 2001, Agrawal & Bushnell Lecture 2 Yield & Quality 16

 Two
Two Problems
Problems to
to Solve
Solve
1. Using the expression for defect level on Slide 10,
derive test coverage (T ) as a function of fault
clustering parameter (β), defect level (DL), and
average number of faults (Af ) on a chip.

2. Find the defect level for:

 Fault density, f = 1.45 faults/sq. cm
 Fault clustering parameter, β = 0.11
 Chip area = 1 cm2
 Fault Coverage, T = 95%

Copyright 2001, Agrawal & Bushnell Lecture 2 Yield & Quality 17

 Solution
Solution of
of Problem
Problem 1
1
Defect level, DL, is given on Slide 10, as follows:

DL = 1 – [(β + TAf )/(β + Af )]β

where T is the fault coverage, Af is the average number of

faults on a chip of area A, and β is a fault clustering
parameter. Further manipulation of this equation leads to
the following result:

(1 – DL)1/β = (β + TAf )/(β + Af )

or T = [{(β + Af )(1 – DL)1/β – β}/(Af )] × 100 percent

Copyright 2001, Agrawal & Bushnell Lecture 2 Yield & Quality 18

 Solution
Solution of
of Problem
Problem 2
2
Defect level, DL, as given on Slide 10, is:

DL(T ) = 1 – [(β + TAf )/(β + Af )]β

Substituting,
 Fault density, f = 1.45 faults/sq. cm
 Fault clustering parameter, β = 0.11
 Chip area = 1 cm2
 Fault Coverage, T = 95%
We get,

DL(T ) = 0.00522 or 5,220 parts per million

Copyright 2001, Agrawal & Bushnell Lecture 2 Yield & Quality 19