Memory, CPU Chips & Buses

Computer Organization

Lecture #7
Jahan Zeb
 Noninverting Buffer

(a) A noninverting buffer

(b) Effect of (a) when control is high
(c) Effect of (a) when control is low
(d) An inverting buffer
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 Memory Chips
 Two possible organizations
for a 4Mbit chip: 512K*8 and
4096K*1
 Term ‘asserted’ is used for
signals rather then saying it
goes high or low
 CS: Chip Select, WE: Write
Enable, OE: Output Enable
 RAS : Row Address Strobe
 CAS : Column Address Strobe

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RAMs & ROMs
 RAM: SRAMs, DRAMs
 SRAM contents are retained as long as power is kept on, made
of basic D flip-flops
 DRAM is an array of cells, each bit must be refreshed to prevent
data leakage
 DRAM
 FPM (Fast Page Mode) DRAM, organized as a matrix of bits i.e.
rows/column addresses
 EDO (Extended Data Output) DRAM, improves memory
bandwidth by having another memory reference before the
completion of first
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 RAMs & ROMs (cont…)

 SDRAM (Synchronized DRAM), is hybrid of static and

dynamic RAM and driven by a single synchronous clock
 ROM  PROM (Programmable ROM), can be
programmed once
 EPROM (Erasable PROM), can be erased as well
 EEPROM, can be erased by applying pulses to it instead
of exposure to ultraviolet light
 Flash memory, erasable without removing it from the
circuit and rewritable

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Comparison of Various Memory Types

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CPU Chips (Logical Pinout)

 Set of pins for communication

 Address, Data and Control pins
 Connection to memory, I/O devices through parallel wires >> bus
 Presenting/accepting signals
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Computer Buses

 Early computers have a single System bus

 Modern computers have buses between CPU-Memory and for I/O devices
 Well-defined rules about how bus works and which devices attached to it has
to obey are called Bus Protocol
 Devices which can initiate bus transfer are active and known as masters,
passive ones are known as slaves
 Bus Driver, Bus Receiver, Bus Transceiver
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Examples of bus masters and slaves

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Bus Width

Growth of an Address bus over time

 Trade-off between maximum memory size and system cost
 Bandwidth can be increased by decreasing bus cycle time or increasing
bit/transfer
 Signals at different lines travel at slightly different speeds, bus skew
problem arises
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 Bus Clocking
 Bus activities takes processing time, known as bus
cycles
 Synchronous Bus has a master clock
 Asynchronous Bus does not have a master clock, bus
cycles can of any length and need not to be the same

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Read Timing on a Synchronous Bus

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Synchronous Buses (cont…)

Specification of some critical times

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Asynchronous Buses

Operation of an Asynchronous Bus

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