Chapter Ten Large-Signal Transistor Circuits

Contents of this Chapter:

10.0 Introduction
10.1 The Common-Emitter Amplifier
10.2 The Common-collector or Emitter-Follower
Connection
10.3 Two-Transistor Combinations
10.4 The FET Switch

Chair Professor Rui-Xiang Yin (South China University of Technology)

 Chapter Ten Large-Signal Transistor Circuits
10.0 Introduction

Classification of transistor circuits:

(1) large-signal circuits

The variations of voltages and currents are sufficiently great to require
that the full, nonlinear device characteristics be considered.

(2) small-signal circuits

The signal components of voltages and currents are sufficiently small to
permit the use of local linear models of device behavior.
The boundary is occasionally fuzzy, and depends on the accuracy with
which one needs to know or predict the operating characteristics of a
particular circuit. In this chapter. we explore circuits of the large-signal
variety, admitting at the outset that we are willing to sacrifice some
accuracy in the representation of device characteristics in order to carry
out a simple analysis of circuit performance.

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 Chapter Ten Large-Signal Transistor Circuits
10.1 The Common-Emitter Amplifier ( 共射极放大器）
10.1.1 A Graphical Approach

1. Input terminals: Operating point

From our discussion in Chapter 9, we know that between the base and emitt
er terminals, the transistor has the v-i characteristic of a semiconductor diod
e. Figure (a) below shows a typical n-p-n silicon transistor input characterist
ic illustrating this diode behavior.

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 Chapter Ten Large-Signal Transistor Circuits
Four input load lines are shown on the input characteristic, each drawn with
slope -1/RS, and each one intercepting the vBE axis at a different value of the so
urce voltage. In the example shown, we have used a value of RS = 20 kΩ. The f
our load lines will be used below to trace the operation of the circuit as if the i
nput voltage were changing by 0.4 V steps from vs1to vs2 to vs3 and finally to vs

4
vS
vBE  vS  iB RS iB  for vBE
RS

The intersection of each load line with the input characteristic gives the ope
rating point for that value of input voltage. Thus in our example, the base c
urrent is zero when vS is equal to vs1 (cutoff), and increases to 10μA, 30μA,
and finally to 50μA as vs increases to vs2, vs3, and vs4.

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 Chapter Ten Large-Signal Transistor Circuits
2. Output terminals: operating point
To find the output operating point corresponding
to each value of vs, we must locate the intersection
of the output load line with the transistor characte
ristic corresponding to the correct value of base c
urrent. Thus, for vs, which yielded iB =0, we find t
he intersection between the output load line and t
he output characteristic for iB =0. This intersectio
n occurs at ic and vCE=VCC. and corresponds to the
transistor being in cutoff for vs =vs1. The remaini
ng three operating points are found similarly.
We note that to turn the transistor on, it is necessary to have v s exceed the 0.6 V d
iode threshold voltage of the base-emitter junction. Once this threshold is exceed
ed, the base current increases steadily in response to an increase in vs. As the base
current increases, the output operating point moves up the load line from the cut
off characteristic (iB = 0) into the active-gain region. Eventually, vCE decreases unt
il the collector-base junction becomes forward-biased, resulting in saturation wit
h aChair
small,Professor Rui-Xiang
nearly constant v . Yin (South China University of Technology)
 Chapter Ten Large-Signal Transistor Circuits
3. Common-Emitter Amplifier Transfer Characteristic

For vs< 0.6 V, the transistor is cutoff. As vs increases, vCE drops from its cutoff
value of VCC toward its saturation value of about 1 V. The slope of the transfer
characteristic in the active-gain region is about -15, and corresponds to the vol
tage gain of the amplifier. That slope is labeled with the notation -FRL/RS.
Let's look the circuit simulation

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 Chapter Ten Large-Signal Transistor Circuits
10.1.2 Large-Signal Model for the Bipolar Junction Transistor
In the active-gain region of the BJT, B-E junction is forward bias, which look
s like a diode, and B-C junction is reverse bias. And the current of collector,
iC, is controlled by the base current, iB, therefore, a transistor may be modele
d as (a)

If the forward-bias diode model is used, the large-signal transistor model is

shown as (b)
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 Chapter Ten Large-Signal Transistor Circuits
Common-emitter amplifier with large-signal model
Substituting the large-signal model for the transistor in the amplifier, we
yield the common-emitter amplifier with large-signal model

If VBE <0.6V , the ideal diode is reverse biased and the transistor is cutoff. If i
B > 0, the ideal diode is forward biased, becoming a short circuit, and vBE beco
mes equal to 0.6 V. Thus for iB > 0,
vS  0.6
iC   F iB   F
RS
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 Chapter Ten Large-Signal Transistor Circuits
Using KVL, we find that

 F RL
vCE  VCC  iC RL  VCC  (vS  0.6)
RS
Note that the slope is -(FRL/RS), called voltage gain. For our example, RL= 3
k, RS = 20 k, and F = 100 (from the characteristics). This slope has the
value of -15, as estimated in Section 10.1.1 from the graphical analysis.
The validity of above formula is limited to the active-gain region, which req
uires vs>0.6V and vCE>VCE, sat. Therefore, the valid range of input voltage, v
S , for active-region operation is
RS
0.6V  vS  0.6V  (VCC  VCE , sat )
 F RL
Any larger value of us produces saturation, while any smaller value produces
cutoff.
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 Chapter Ten Large-Signal Transistor Circuits
10.1 .3 An Example
A transistor switch is used to light the 500Ω lamp when vA= 1 V. The lamp
has a nominal resistance of 500Ω and requires a current of 15 mA or more
for proper illumination.

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 Chapter Ten Large-Signal Transistor Circuits
The large-signal equivalent of the transistor amplifier

For vA=0 (<0.6V), the transistor is cutoff. iB=0 and iC=0, the lamp is off.
For vA=1V (>0.6V), the base current can be calculated as
v A  0.6V
iB   0.4mA
RA
Then the collector current or the lamp current is iC   F iB  20mA

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 Chapter Ten Large-Signal Transistor Circuits
The current through the bulb, iC, is larger than the 15 mA needed to light the l
amp. However, we must be careful to check whether our assumption about sat
uration is correct.
 F RL
vCE  VCC  (v A  0.6V )  0
RA
It is slightly less than VCE, sat . The transistor has just barely entered the
saturation region. Therefore, we should revise our assumption, and analyze the
circuit assuming saturation.
If the transistor is saturated, then the collector current is given by
VCC  VCE , sat
I C , sat   18mA
RL
which is still greater than the 15 mA required. Thus the circuit switches betwee
n cutoff and saturation in response to 1 V signal, will light the lamp.

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 Chapter Ten Large-Signal Transistor Circuits
10.2 The Common-collector or Emitter-Follower Connection

The input signal, vs, is connected to the base and the output
signal is from the emitter. If the transistor is in the active-ga
in region, the circuit can be modeled as

Note: This model is only valid where vCE>VCE,sat and iB>0.

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 Chapter Ten Large-Signal Transistor Circuits
The transfer characteristic of the emitter-follower amplifier
From the large-signal model we can write a KCL
i0  iB   F iB  (1   F )iB

According to the Ohm's law in resistance RE, we have

v0  i0 RE  (1   F )iB RE

In the input loop we write the KVL equation

vS  iB RB  0.6V  v0  0
Combining the equations, we yield transfer
characteristic of the emitter-follower amplifier in active-
gain region.
(1   F ) RE
v0  (vS  0.6)
RB  (1   F ) RE
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 Chapter Ten Large-Signal Transistor Circuits
When input voltage is sufficient low, the transistor will enter cutoff region. In
this case, base current and collector current will be zero, and then the output
voltage maintains zero.
When input voltage is sufficient high, the transistor will enter saturation
region. In this case, collector current will reach the maximum value and then
the output voltage maintains maximum. Following figure shows the skeleton
of transfer characteristic.

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 Chapter Ten Large-Signal Transistor Circuits
The maximum range of input voltage for active-gain region
1. The minimum allowable input voltage
In the active-gain region, we have

v0  i0 RE  (1   F )iB RE vS  iB RB  0.6  v0  0
By eliminating v0 ,we obtain the dependence of iB on vS

vS  0.6
iB 
RB  (1   F ) RE

To satisfy the condition iB>0, the input voltage must be greater than 0.6V

vS  0.6 V

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 Chapter Ten Large-Signal Transistor Circuits
2. The maximum allowable input voltage
In the boundary between active-gain and saturation regions, the collector-
emitter voltage maintains a minimum value, saturation voltage VCE, sat.

(1   F ) RE
vCE ,min  VCE , sat  VCC  (vS  0.6 )
RB  (1   F ) RE

Therefore, in order to ensure the transistor in active-gain region, the input

voltage should satisfy

RB  (1   F ) RE
vS  0.6  (VCC  VCE ,sat )
(1   F ) RE

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 Chapter Ten Large-Signal Transistor Circuits
The voltage gain of the emitter-follower
From the relation between input voltage and output voltage
(1   F ) RE
v0  (vS  0.6)
RB  (1   F ) RE
v0 (1   F ) RE
we can calculate the voltage gain Av  
vS RB  (1   F ) RE
It is less than unity for any combination of RB, RE, and βF. In most instances, how
ever, RB is much less than (1+βF)RE, so that the voltage gain is very nearly, but n
ot quite, unity. Thus, in an approximate sense, the output at the emitter follows t
he input with unity gain. This is the origin of the name emitter follower.
Although the emitter follower does not produce voltage gain, it does produce c
urrent gain of magnitude βF, and therein lies its usefulness.

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 Chapter Ten Large-Signal Transistor Circuits
10.2.2 A Transistorized Current Source
Split the input and output sub-circuits of
the transistor.

According our analysis for the emitter-follower, we find

(1   F ) R3 R2
v3  ( VCC  VBE )
R1 || R2  (1   F ) R3 R1  R2

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 Chapter Ten Large-Signal Transistor Circuits
The Output Current
Recall the current distributive relation
of the transistor in active-gain state,
F
iL   F i3 
1 F
1 R2
 ( VCC  VBE )
R3 R1  R2
Where, we accept the conditions

R1 || R2 (1   F ) R3 and  F 1
Using the Ohm's law we have
The result shows that the output current is constant and independent
v3
of iRL. Therefore,  F ) Rbehaves
(1 circuit R2
 the 3
( a current
VCC  VBE )
source.
2  (1   Fis)based
3
Remember, R3 above
R1 || Rdiscussion R3 R1on that
R2 the transistor is in
active gain region.
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 Chapter Ten Large-Signal Transistor Circuits
The Load Range for the Current Source
If RL is too large, however, the transistor will enter saturation state, and t
he circuit is no longer valid current source.
By KVL, we have
VCC  iL RL  vCE  v3  0
To avoid saturation, the emitter-collector
voltage should satisfy
VCC  iL RL  v3  vCE  VCE , sat
Therefore, the load resistance must satisfy

VCC  v3  VCE , sat

RL  R1
iL VCC  VBE  VCE , sat
R1  R2
Substituting for iL and v3, we get the p RL  R3
eak point of RL R2
VCC  VBE
R1  R2
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 Chapter Ten Large-Signal Transistor Circuits
Let us give an actual example. Suppose VCC=12V, R1=500, R2=R3=100 and
VBE=0.7V, VCE,sat=0. In this case, The value of current source is

1 R2
iL  ( VCC  VBE )  0.013 A
R3 R1  R2

R1
VCC  VBE  VCE , sat
R  R2
RL max  1 R3
R2
VCC  VBE
R1  R2
 823

Look at the demonstration

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 Chapter Ten Large-Signal Transistor Circuits
10.2.3 A Regulated DC Power Supply
A DC power supply includes a rectifier and a regulator, which converts ac vo
ltage (sine wave) to a stable DC voltage. In Chapter 8 we have introduced a si
mple example regulator circuit using zener diode. We have noted that if the l
oad is too heavy, the circuit may work improperly. Here we will discuss a tra
nsistorized circuit. Let's consider following circuit.

If the output voltage of rectifier is larger than the zener voltage, the zener diod
e works in breakdown state and the voltage between its terminals is fixed as VZ.
Substituting equivalent model for the zener diode we can plot an equivalent of
the circuit as the right figure.
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 Chapter Ten Large-Signal Transistor Circuits
Split the input and output loops of the transistor and apply the Thévenin
equivalent

If RZ<<R1, VT VZ and RT RZ. Then the circuit can be simplified as the
right circuit.

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 Chapter Ten Large-Signal Transistor Circuits
The Output Characteristic

According to our analysis on the emitter-

follower, we write the output voltage

(1   F ) RL
vL  (VZ  0.6)
RZ  (1   F ) RL

In practical application, (1+F)RL>>RZ. So

vL  VZ  0.6
Which is independent of VCC. The circuit behaves a DC voltage source.

Now we try to find the Thévenin equivalent of the "source".

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 Chapter Ten Large-Signal Transistor Circuits
Based on above equation for output voltage, we can directly write the open-
circuit voltage of the "source"

VT  VOC  VZ  0.6
Next we let the load is short-circuit, and find the short-circuit current

VZ  0.6
I SC  (1   F )iB  (1   F )
RZ
Thus the Thévenin resistance can be calculated

VOC RZ
RT  
I SC 1   F

Finally, we draw out the Thévenin equivalent of the "source" as follows

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 Chapter Ten Large-Signal Transistor Circuits
The Limit of load Resistance

According to KCL, iZ  i1  iB
To ensure the zener diode working in breakdown region, following inequali
ties must be satisfied
iZ  I Z min
From the circuit we can calculate the currents
VCC  VZ iL V  0.6
i1  iB   Z
R1 1   F (1   F ) RL
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 Chapter Ten Large-Signal Transistor Circuits
Therefore, we have
VCC  VZ VZ  0.6
  I Z min
R1 (1   F ) RL
1 (1   F )(VCC  VZ  I Z min R1 )

RL R1 (VZ  0.6)
The allowable range of load resistance is
R1 (VZ  0.6)
RL 
(1   F )(VCC  VZ  I Z min R1 )
As a practical case, assume VCC=12V, VZ=6.2V, RZ=10, R1=510, IZmin=5mA
and F=50. In this case the regulated output voltage is vL=6.2-0.6=5.6V. The r
ange for load resistance is
510  (6.2  0.6)
RL   17
(1  50)(12  6.2  5  0.51)
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 Chapter Ten Large-Signal Transistor Circuits
10.3 Two-Transistor Combinations
10.3.1 The Emitter-Coupled Pair

1. Circuit structure

(1) Symmetric structure: two transistors are identical; RC1=RC2

(2) Two inputs: v1 and v2 from bases of two transistors respectively.
(3) Multi-type output: vC1 or vC2 or vC1- vC2
(4) Emitter-coupled: emitters of two transistors are connected together.
(5) Current-source bias
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 Chapter Ten Large-Signal Transistor Circuits
2. Fundamental relations
(1) KVL:

v1  v2  vBE1  vBE 2
(2) KCL:
iE1  iE 2  I 0

(3) Characteristic of transistors:

q q
vBE 1 vBE 1
iE1  I ES e kT
iC1   F I ES e kT

q q
vBE 2 vBE 2
iE 2  I ES e kT
iC 2   F I ES e kT

(4) Output voltages

vC1  VCC  iC1 RC1 vC 2  VCC  iC 2 RC 2

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 Chapter Ten Large-Signal Transistor Circuits
3. Large-Signal Model
Because of the emitter-coupled structure, the E-B voltages of two transistors
are effected by input voltages and may not be considered constant voltages.
We use an exponential diode model to construct the large-signal model of
the circuit.

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 Chapter Ten Large-Signal Transistor Circuits
4. Voltage Transfer Characteristic

According to KVL, we have vBE1  (v1  v2 )  vBE 2

Applying this relation to the calculation of collector current iC1

q q
vBE 1 vBE 2  ( v1  v2 )
iC1   F I ES  e kT
  F I ES  e kT

q q q
vBE 2 ( v1  v2 ) ( v1  v2 )
  F I ES  e kT
e kT
 iC 2  e kT

Considering that aF is very close to unity practically, we have

q
( v1  v2 )
I 0  iE1  iE 2  iE1  iE 2  iC 2 (1  e kT
)

I0 I0
iC 2  q
iC1  q
( v1  v2 )  ( v1  v2 )
1 e kT
1 e kT

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 Chapter Ten Large-Signal Transistor Circuits
Then we conclude the output voltages
I 0 RC1 I 0 RC 2
vC1  VCC  q
vC 2  VCC  q
 ( v1  v2 ) ( v1  v2 )
1 e kT
1 e kT

q
( v1  v2 )
1 e kT
vC1  vC1  I 0 RC q
( Assume RC1  RC 2  RC )
( v1  v2 )
1 e kT

vC2

vC1
v1-v2
0

vC1 –vC2
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 Chapter Ten Large-Signal Transistor Circuits
5. Limits on Input Voltages
To avoid the transistors entering cutoff, it should be satisfied that
vBE1>0.5V and vBE2>0.5V
In active-gain region, therefore, the input voltages should satisfy
| v1  v2 || vBE1  vBE 2 | 0.6  0.5  0.1V
This is often called the difference mode limitation of the inputs.
Look at the circuit demo.
To avoid the transistors entering saturation, vC1-v1>0.2V and vC2-v2>0.2V
I 0 RC I 0 RC
VCC  q
 v1  0.2  0 ; VCC  q
 v2  0.2  0
 ( v1  v2 ) ( v1  v2 )
1 e kT
1 e kT

The common mode limitation of the inputs:

1
v1 , v2  VCC  I 0 RC  VCE , sat
2
Let demonstrate the circuit application.
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 Chapter Ten Large-Signal Transistor Circuits
10.3.2 Difference-Mode Amplification 差模放大
According to our above discussion, the output voltages depend only on the di
fference between two input voltages. For this reason, the emitter-coupled pai
r is often called a differential amplifier 差分放大器 . The difference between
v1 and v2 constitutes a difference-mode input signal 差模输入信号 .

I 0 RC
vC1  VCC  q
 ( v1  v2 )
1 e kT

I 0 RC
vC 2  VCC  q
( v1  v2 )
1 e kT

q
( v1  v2 )
1 e kT
vC1  vC 2  I 0 RC q
( v1  v2 )
1 e kT

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 Chapter Ten Large-Signal Transistor Circuits
1. The transfer characteristic
(1) Output from the collector of T1 (2) Output from the collector of T2

Linear-region gain
Linear-region gain
vC1 I R q vC 2 I 0 RC q
A1   0 C  A2   
  v1  v2  4 kT   v1  v2  4 kT
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 Chapter Ten Large-Signal Transistor Circuits
(3) Differential output

Linear-region gain
  vC1  vC 2  I R q
Ad   0 C 
  v1  v2  2 kT

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 Chapter Ten Large-Signal Transistor Circuits
2. The bias current source
The characteristic shows that the linear-region gain is proportional to the
bias current I0. So the gain of the emitter-coupled pair can be adjusted over
a wide range simply by changing the bias current. A practical biasing
current-source is constructed as 10.2.2. A circuit for accomplishing this
current-source biasing is shown as
According to the analysis in 10.2.2, the
bias current can be calculated
1  2 RB 2 
I 0  iC 3   VCC  0.6 
RC 3  RB1  RB 2 
As the bias current changes, the transfer ch
aracteristic changes. In fact, linear-region g
ain depends on the bias current proportiona
lly. Because of this dependence of linear-reg
ion gain on bias current, the emitter-couple
d pair finds wide usage in automatic-gain-c
ontrol (AGC 自动增益控制 ) applications a
nd in modulation circuits.
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 Chapter Ten Large-Signal Transistor Circuits
10.3.3 Common-Mode Rejection 共模抑制
1. Common-Mode Input
We have already commented on the fact that when v 1 and v2 are equal, the
bias current divides equally between the identical transistors T1 and T2 with
the result that the output voltages do not depend on v1 or v2. Voltages that
appear equally at both inputs are called common-mode voltages (as
distinguished from the difference-mode voltages of the preceding section).
1
vcom  (v1  v2 )
2
2. Common-Mode Rejection
The emitter-coupled pair, and the related circuit involving FETs, has the pro
perty that a common-mode voltage applied to the inputs produces no change i
n output. This remarkable cancellation of common-mode signals is called com
mon-mode rejection, Op-amps almost always have an emitter-coupled pair (or
source-coupled pair) as an input circuit to obtain a large common-mode rejec
tion.

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 Chapter Ten Large-Signal Transistor Circuits
3. Common-mode rejection ratio 共模抑制比
In actual devices there is always some degree of imperfection in the match
between two transistors. Therefore, actual devices do not show the perfect
common-mode rejection of our somewhat idealized model. A measure of
the quality of the rejection of common-mode signals is called the common-
mode rejection ratio, abbreviated CMRR (or often, simply CMR), which is
defined the ratio of difference-mode gain to common-mode gain:

Adiff
CMRR  No dimension
Acom
Adiff
CMR  20 log dB ( 分贝）
Acom

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 Chapter Ten Large-Signal Transistor Circuits
10.3.4 Complementary-Symmetry Pairs 互补对称电路
1. Complementary Transistors
One transistor is NPN-type and the other is PNP-type.
2. Symmetry
(1) Symmetrical circuit structure; (2) Identical device (transistors) parameters
3. Complementary-Symmetry Amplifier Circuit
4. Operating principle
(1) When vS=0 (no input signal), T1 an
d T2 are cutoff, then vL=0.

(2) When vS>0.6V, T1 on and T2 off,

then vL follows vS though T1 (Emi
tter-Follower).
(3) When vS<-0.6V, T1 off and T2 on, the
n vL follows vS though T2 (Emitter-F
ollower).
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 Chapter Ten Large-Signal Transistor Circuits
5. Crossover distortion 交越失真
When -0.6V<vS<0.6, T1 and T2 all are not ON, then vL maintains 0 and is inde
pendent of vS. This is called crossover distortion.

6. Waveform example

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 Chapter Ten Large-Signal Transistor Circuits
7. Eliminate crossover distortion: diode biasing
The reason causing the crossover distortion is zero-biasing of the transistors.
If two transistors have forward-bias of 0.6V when input voltage is zero, then
the crossover distortion may be eliminated. Following circuit is an example.
In the circuit, diodes D1 and D2 are all
forward-bias, there is 0.6+0.6 voltage between
two bases of transistors, which provided a
0.6V forward-bias for each transistor. The
crossover-distortion is eliminated.
Note: The resistances R1 and R2 are
necessary to ensure two diodes forward-
bias and conduct-on, which are missed in
the textbook.

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 Chapter Ten Large-Signal Transistor Circuits
8. Eliminate crossover distortion: Unity-gain feedback
A second method illustrates the use of an op-amp in a feedback loop to comp
are the output voltage vL against the input signal vS.

Remember that the open-loop gain of the op-amp is enormous. This means that
the voltage applied to the bases of the two transistors from the op-amp's output
terminal will have magnitude sufficient to turn on either T 1 or T2 as soon as vS a
nd vL differ by as much as 0.1mV. Following is the testing waveform.
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 Chapter Ten Large-Signal Transistor Circuits
10.3.5 A Comment: Understanding Op-Amps
A typical commercial op-amp consists of an emitter-coupled pair (or source-coupled
pair) for initial amplification followed by one or more amplification stages that might be
of a variety of types (common emitters and emitter-coupled pairs being most common).
The output stage very often consists of a complementary-symmetry pair in which a
combination of diode biasing and feedback is used to eliminate crossover distortion. Thus
with the circuits we have already discussed in hand, it becomes possible to understand at
least qualitatively many of the characteristics of actual op-amps. The differential
amplification and excellent common-mode rejection come from the input emitter-coupled
pair. The limitations on allowed common-mode input voltage arise because various
transistors in either the input stage or in subsequent stages can be driven into saturation
or cutoff by excessive variation of the input voltages. The saturation of the op-amp
output near the supply voltages arises from the saturation of one of the transistors in the
complementary-symmetry output pair. The nonzero bias currents at the input terminals
are needed as base currents of the input transistors to assure active-region operation.
The input offset voltage and input offset currents arise from imperfect matching of the
input pair of transistors and from biasing imperfections. Although we have yet to discuss
issues related to input and output resistance and issues related to op-amp speed and
frequency response, with a few basic circuit concepts involving transistors, many quirks
of the "black box" begin to make sense.
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 Chapter Ten Large-Signal Transistor Circuits
10.4 The FET Switch 场效应管开关
The uses of the various kinds of field-effect transistors (FET) are in many ways similar to
the uses of the bipolar junction transistors (BJT). For example, the large-signal transfer c
haracteristic of a common-source amplifier (take an NPN common-emitter amplifier and
replace the transistor with an enhancement mode N-channel FET) will be similar in man
y ways to the transfer characteristic of an NPN common-emitter amplifier. There is a cut
off region, an active-gain region, and a saturation region, and many of the same circuit fu
nctions can be performed. In several important ways, however, FETs are not equivalent t
o BJTs, and it is these features that we wish to emphasize here.
First, the FET behaves like an open circuit at its gate terminal. The MOSFET has an insul
ator between the gate and channel. while the JFET gate is back-biased with respect to the
channel (in normal operation). As a result, the FET in normal operation draws no current
(or almost no current) from a source network and is therefore extremely useful in applica
tions where it is necessary not to load down a source network that has a high Thevenin re
sistance.
Second, the FET output characteristics are rather symmetrical about the origin. That is, for
small signals (|vDS| << |VP|) the FET channel looks like a pure resistance, with no nonlinea
rities or saturation voltage present. As a result, the FET is particularly useful as a low-po
wer voltage-controlled switch for low-level signals. We shall discuss this application furthe
r below, in full recognition that we are of necessity being very incomplete.
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 Chapter Ten Large-Signal Transistor Circuits
10.4.1 The Need For A Graphical Approach
Unlike the BJT. where we could make an extremely simple model of the
For small values of vDS, the output characteristics of an FET are just a voltag
device, in many uses the FET defies the use of simple models made of ordinary
e-controlled
circuit elementsresistor.
(such We change
as diodes thedependent
and value of vDS from asources).
current value near zero, at
Therefore.
one must
which theoften
slopeuse
of an
thealgebraic representation
vDS-iD characteristic of the to
is largest, device characteristics,
a value more negativor
one must be willing to work with graphical methods from graphical
e than VP, at which
representations thedevice
of the vDS-iDcharacteristics.
characteristic lies along the iD= 0 axis, the effec
tive resistance Resistance
Voltage-control of the channel can be made
Characteristic to N-channel
of an change from some minimum v
JFET
alue Ron to some very large value. Thus, by alternating between zero gate vol
tage ( vGS = 0) and pinchoff (vGS< VP) we can use the channel resistance of the
FET as an "ON-OFF" switch.

vGS→RDS=△vDS /△iD (slope)

vGS=0→Ron< RDS <∞← vGS<VP (pinch off)

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 Chapter Ten Large-Signal Transistor Circuits
10.4.2 A Simple FET Chopper 斩波器

(1) Assumptions: |vA|<<|VP| ； RL>>RA>>Ron ； vGS≈vG (because |vL|<<|VP|)

(2) When vG=0, FET is ON, then vL≈ vA

(3) When vG=VP, FET is pinched off, then vL=0

The right figure is a typical operating waveform.

A controlling negative-going square wave is appli
ed to the gate while a signal is present from vA, the
output waveform will be a chopped or sampled ve
rsion of vA.
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 Chapter Ten Large-Signal Transistor Circuits
The connection for the gate
(1) Gate to Ground: Because of the high input resistance of FET, an inductive
voltage in the gate may be serious. Therefore, in order to ensure zero
voltage level in gate when no control signal provided, there must be a
resistance path between gate and ground.
(2) Control signal: The drive signal may be a square waveform, which
amplitude ±A. We may apply a diode limiter circuit (8.4.3) to eliminate
the positive part of the drive signal.

In the circuit, to ensure that the "switch" is off effectively, the amplitude A
of the drive signal should be greater than |VP|.
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 Chapter Ten Large-Signal Transistor Circuits
The application of Chopper

(1) Chopper amplifier 斩波放大器

Very low frequency signal to be amplified, which may not be amplified usi
ng a normal amplifier, is chopped as a high frequency pulse firstly. Then t
he high frequency pulse is amplified. Finally, the amplified pulse is filtere
d to restore low frequency signal (amplified).
(2) Time-division multiplexing communication 时分复用通信
In the communication channel, there are several signals to be communicat
ed. All signals are chopped and occupies individual time respectively. The
refore, the channel is time-shared to each signal.

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 Chapter Ten Large-Signal Transistor Circuits
10.4.3 A Two-Channel Analog Multiplexer 两通道多路 ( 复用 ) 器
A two-channel analog multiplexer selects alternate samples of two low-lev
el source waveforms, vA and vB to appear at the output node vM. The equal
but opposite gate drives for the two FETs are derived from a sine wave, u
sing a comparator (to produce a large-amplitude square wave) and an inv
erter (to produce a square wave of opposite sign). The gate drive wavefor
ms are applied through the diode-referral resistor networks to insure that
vGS is zero during the ON cycle, and not some positive voltage that would i
nject carriers into the channel and produce a signal error.

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 Chapter Ten Large-Signal Transistor Circuits
A de-multiplexer 多路输出选择器 accepts the waveform vM, and applies the
waveform to two alternately switched sample-and-hold networks 采样保持电
路 , one for vA the other for vB. The drive waveforms for the de-multiplexer mu
st be accurately synchronized 同步 with the multiplexer drives vGA and vGB, o
r else the alternate multiplexed samples of vA and vB will not get switched to th
e correct sample-and-hold network at the correct time.

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 Chapter Ten Large-Signal Transistor Circuits

Exercises of Chapter 10

E10.2, E10.3, E10.5, E10.6*, E10.7, E10.8, E10.9, E10.10*

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