0.

13um Mixed Signal RF Process Flow

TSS/FE 2012/12

GF 0.13um Technology

0.13um RF CMOS Overview

Process Modules
STI Formation

Well Formation
Gate Formation Source/Drain Formation Salicide Formation Contact Formation

Metal-1 Formation single damascene

MiM Formation

Mx/VIAx-1 Formation - dual damascene

PASSIVATION & BONDPAD Formation
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STI Formation

Well Formation
Gate Formation Source/Drain Formation Salicide Formation Contact Formation Metal-1 Formation single damascene MiM Formation

Mx/VIAx-1 Formation - dual damascene

PASSIVATION & BONDPAD Formation

STI (Shallow Trench Isolation)

RX (L10) Mask used to define active region. Reverse(L11) Mask used;It is created by foundry and improve STI CMP uniformaity and prevent Nitride residue.
SiN

Si Substrate

Deposit and pattern thin SiN (RX)

Reverse active etch

STI CMP STI Etch

Wet SiN removal STI gap fill deposit SiO2

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STI Formation

Well Formation
Gate Formation

Source/Drain Formation
Salicide Formation Contact Formation Metal-1 Formation single damascene MiM Formation

Mx/VIAx-1 Formation - dual damascene

PASSIVATION & BONDPAD Formation

Well Implants
Deep NWELL(optional) - deep N-well is for better isolation from substrate noise.(L06) Core Multi-Vt transistors:Low/Standard/High Vts,Native device IO 1.8V,2.5V or 3.3V,Native device
Photoresist

Deep NWELL

Deep NWELL

Deep NWELL

Deep NWELL

Deep NWELL

Deep NWELL

Deep NWELL

STI Formation

Well Formation
Gate Formation Source/Drain Formation Salicide Formation Contact Formation Metal-1 Formation single damascene MiM Formation

Mx/VIAx-1 Formation - dual damascene

PASSIVATION & BONDPAD Formation

Gate Formation (1) Dual Gate

Need two gate oxide thickness;Thin for core FETs and Thick for IO FETs The gate oxide is grown in furnace,not deposited.It requires high quality to have good reliability (Gate Oxide Integrity) Dual Gate mask L38

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Gate Formation (2) Poly Gate

The Poly CD control is critical and key to device performance.

1.Poly deposition 2.Poly gate mask(L60) 3. Poly gate etch

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STI Formation Well Formation

Gate Formation
Source/Drain Formation Salicide Formation Contact Formation Metal-1 Formation single damascene MiM Formation Mx/VIAx-1 Formation - dual damascene

PASSIVATION & BONDPAD Formation

NLDD for Core and IO NFETs

1.LDD (Lightly Doped Drain)is used for minimize peak E fields that cause hot carrier and breakdown. 2.The NLDD must be heavily doped to minimize series resistance.
1.Thin NLDD Mask(L61) 2.Thin NLDD Pocket Imp. (P type) 3.Thin NLDD Imp.(N type)

1.Thick NLDD Mask(L62) 2.Thick NLDD Imp.(N type)

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PLDD for Core and IO NFETs

1.Thin PLDD Mask(L64) 2.Thin PLDD Pocket Imp. 3.Thin PLDD Imp.

1.Thick NLDD Mask(L23) 2.Thick NLDD Imp.

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Spacer Formation
1.Spacer deposition 2. Spacer etch (blanket)

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Source / Drain Implantation

1.N source/drain mask(L65) 2.N source/drain imp. 3.N source/drain anneal

1.P source/drain mask(L70) 2.P source/drain imp. 3.P source/drain anneal

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STI Formation

Well Formation
Gate Formation Source/Drain Formation Salicide Formation Contact Formation Metal-1 Formation single damascene MiM Formation

Mx/VIAx-1 Formation - dual damascene

PASSIVATION & BONDPAD Formation
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Salicide Formation
The salicide is used to reduce Poly and diffusion Rs. Technology progression: TiSix -> CoSix-> NiSix.Scaling requires smaller silicide grain size to minimize Rs variations
1. 3.

1.Salicide block deposition 2.Salicide block mask (L68) 3.Salicide block etch
2.

1.1st RTA 2.Post RTA1 Cobalt remove

4.

Cobalt

1.Cobalt deposition

1.2nd RTA
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STI Formation

Well Formation
Gate Formation Source/Drain Formation Salicide Formation Contact Formation Metal-1 Formation single damascene MiM Formation

Mx/VIAx-1 Formation - dual damascene

PASSIVATION & BONDPAD Formation

Contact Formation

1.Etch-stop layer deposition 2.ILD deposition 3.ILD CMP 4.Contact mask (L75) 5.Contact etch 6.Barrier metal deposition 7.W(tungsten) deposition 8.W-CMP

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STI Formation

Well Formation
Gate Formation Source/Drain Formation Salicide Formation Contact Formation Metal-1 Formation single damascene MiM Formation

Mx/VIAx-1 Formation - dual damascene

PASSIVATION & BONDPAD Formation
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M1 Formation- Single damascene

1.Etch-stop layer deposition 2.IMD deposition 3.Etch-stop layer deposition 4.Metal-1 mask (L80) 5.M1 Trench etch 6.Barrier seed deposition 7.Cu fill 8.Cu-CMP

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STI Formation

Well Formation
Gate Formation Source/Drain Formation Salicide Formation Contact Formation Metal-1 Formation single damascene MiM Formation

Mx/VIAx-1 Formation - dual damascene

PASSIVATION & BONDPAD Formation
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MiM (Metal insulator Metal)-Optional

MIM capacitor must be located between MetalTop layer and the metal layer immediately below There are two options for MiM 1-Mask and 2-Mask ;Below is the 1-Mask MiM FuseTop layer(L92) defines the top plate and metal-[n-1] layer defines the bottom plate of the MIM capacito The capacitance is 1.0 fF/um2

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STI Formation

Well Formation
Gate Formation Source/Drain Formation Salicide Formation Contact Formation Metal-1 Formation single damascene MiM Formation

Mx/VIAx-1 Formation - dual damascene

PASSIVATION & BONDPAD Formation
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Integration schemes for Dual Damascene

Mx/VIAx-1 Formation - dual damascene
1.Etch-stop layer deposition 2.IMD Via deposition 3.Etch-stop layer deposition 4.IMD Trench deposition 5.Etch-stop layer deposition 6.VIAx-1 mask (L85, L91, L94, L97, L9R) 7.Dual damascene via etch 8.Mx mask(L88, L93, L96, L9E, L98) 9.Barrier/seed deposition 10.Cu barrier 11.Cu deposition 12.Cu CMP

IMD(LK) IMD(LK)

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STI Formation Well Formation

Gate Formation
Source/Drain Formation Salicide Formation Contact Formation Metal-1 Formation single damascene MiM Formation Mx/VIAx-1 Formation - dual damascene

PASSIVATION & BONDPAD Formation

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Passivation & Bond Pad Formation

1.Passivation-1 deposition (oxide + nitride) 2.L9C MASK + Etch 3.AL deposition 4.L9S MASK + ETCH 5.Passivation-2 deposition 6.L95 MASK + ETCH 7.Alloy

L95 (L9S) L9C

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Schematic Cross section

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Thank you

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