23MYM122

Not AND gate

Prepared by:
Marinas, Meliza Y.
BSECE 4-1

Prepared to:
Engr. Hudson Aries O. Oña
 October 2010

23MYM122
GRADE SHEET

CMOS NAND gate

MASK LAYOUT SCORE

P-WELL

THINOX

POLYSILICON

P-PLUS+

P-PLUS-

CONTACT CUT

METAL

TOTAL

© 2010 Marinas Semiconductor Company 4 www.mscompany.com\23MYM122

 October 2010

23MYM122
NAND GATE
CMOS IMPLEMENTATION
PARAMETER CALCULATIONS

CMOS NAND gate

A. SHEET RESISTANCE, Rs(Ω/ )

LAYER Rs(Ω / ) NO. OF Rs,Ω

METAL 0.03 438 13.14

DIFFUSION 10.00 146 1460

POLYSILICON 15.00 202 3030

N-CHANNEL 1 x 104 8 80000

4
P-CHANNEL 2.5 x 10 8 200000

284503.14/4
TOTAL Rs, Ω =71125.785

© 2010 Marinas Semiconductor Company 5 www.mscompany.com\23MYM122

 October 2010

23MYM122
NAND GATE
CMOS IMPLEMENTATION
PARAMETER CALCULATIONS

CMOS NAND gate

B. AREA CAPACITANCE,
Cg
RELATIVE RELATIVE
AREA VALUE AREA Cg
(∑Vg) (∑Ag)

GATE TO
1 4 4
CHANNEL

DIFFUSION 0.25 36.5 9.125

POLYSILICON 0.1 50.5 5.05

METAL 0.075 109.5 8.2125

26.3875/4
TOTAL, Cg =6.596875

© 2010 Marinas Semiconductor Company 6 www.mscompany.com\23MYM122