Workshop on Fully Layout Technology

2002 / 03 / 23

THE ART OF ANALOG LAYOUT

TEL
03-5101949
/

Workshop on Fully Layout Technology

2002 / 03 / 23

Analog
analog matching guide

Design layout

Workshop on Fully Layout Technology

2002 / 03 / 23

ANALOG LAYOUT
CMOS ANALOG LAYOUT
BIPOLAR ANALOG LAYOUT
BICMOS ANALOG LAYOUT

Workshop on Fully Layout Technology

2002 / 03 / 23

CMOS ANALOG LAYOUT

CMOS Component Layout Guide
CMOS Layout Application

Transistor
Capacitor
Resistor
Bipolar
Mos power transistor

CMOS Layout Case Study

4

Workshop on Fully Layout Technology

2002 / 03 / 23

CMOS LAYOUT STRUCTURE

LV NMOS
(poly)&(active)&(nplus)&(psub)

s
5

LV PMOS
(poly)&(active)&(pplus)&(nwell)

Workshop on Fully Layout Technology

2002 / 03 / 23

CMOS LAYOUT STRUCTURE

Asymmetric HV12V Device Layout

N++

N+

P+

POLY
DIFF

N+

POLY

P+

NWELL

PDD

HV

CONTACT

HV
MT1

DIFF
DRAIN GATESOURCE

NMOS
6

DRAIN GATE SOURCE

PMOS
/

Workshop on Fully Layout Technology

2002 / 03 / 23

CMOS LAYOUT STRUCTURE

Asymmetric HVP30V Device Layout

NWELL+BL

NWELL+HPF
POLY
N+

HV

L
CO
DRAIN

HPF+BL

GATE

SOURCE

HV
DIFF

DRAIN

GATE SOURCE

POLY

PMOS
7

DIFF
P+

NMOS
/

Workshop on Fully Layout Technology

2002 / 03 / 23

CMOS-RESISTOR LAYOUT STRUCTURE

>>Poly register

>>Diff Resistor
CONTACT

>>Nwell Resistor

POLY1

Ndiff
P+
DIFF

NWELL

NWELL
DUMMY
8

DUMMY

Workshop on Fully Layout Technology

2002 / 03 / 23

CMOS-CAPACITOR LAYOUT STRUCTURE

1P1-P2 LAYOUT STRUCTURE

CO

poly1

M1

POLY2

M2
2MOS LAYOUT STRUCTURE

CO
P+

N+
DIFF

poly
1

Workshop on Fully Layout Technology

2002 / 03 / 23

CMOS-CAPACITOR LAYOUT STRUCTURE

3MIN TOPMETAL TOPMETAL-1-MINLAYER

M
5

M4
VIA4

MIM
4METAL POLY STRUCTURE
NWELL
CONTACT

BOTTOM=POLY1+M2
TOP=M1+M3
10

Workshop on Fully Layout Technology

2002 / 03 / 23

CMOS-PNP LAYOUT STRUCTURE

NWELL
CONTACT

DIFF
M1
P+

11

Workshop on Fully Layout Technology

2002 / 03 / 23

CMOS-FUSE LAYOUT STRUCTURE

METAL FUSE

POLY1 FUSE

POLY1 FUSE

CONTACT

M1

M1

POLY1

CONTACT

PASS

POL
Y1
12

STYLE-1

STYLE-2

STYLE -3

Workshop on Fully Layout Technology

2002 / 03 / 23

CMOS LAYOUT APPLICATION -TRANSISTOR

>>MOS Matching Mirror

M2
VIA
M1

P+

POLY
13

CONTACT DIFF
/

Workshop on Fully Layout Technology

2002 / 03 / 23

CMOS LAYOUT APPLICATION -TRANSISTOR

>>1

OUT P
OUT N

14

Workshop on Fully Layout Technology

2002 / 03 / 23

CMOS LAYOUT APPLICATION -TRANSISTOR

>>2

DUMMY POLY

15

Workshop on Fully Layout Technology

2002 / 03 / 23

CMOS LAYOUT APPLICATION-CAPACITOR

>>Unit Capacitor

DUMMY
DUMMY

Well contact

16

poly

Workshop on Fully Layout Technology

2002 / 03 / 23

CMOS LAYOUT APPLICATION-CAPACITOR

>>Unit Capacitor Input Stage Matching
POLY2
POLY1

WELL
CONTACT

M1

17

Workshop on Fully Layout Technology

2002 / 03 / 23

CMOS LAYOUT APPLICATION-RESISTOR

>> Normal Resistor-

18

Workshop on Fully Layout Technology

2002 / 03 / 23

CMOS LAYOUT APPLICATION-RESISTOR

>>Crocess Resistor
M2

VIA

WELLCONTACT
CONTACT

POLY
M1

19

Workshop on Fully Layout Technology

2002 / 03 / 23

CMOS LAYOUT APPLICATION -RESISTOR

>>

DUMMY

20

DUMMY

Workshop on Fully Layout Technology

2002 / 03 / 23

CMOS LAYOUT APPLICATION PNP X 10

P+

NWELL
N+

21

P+

Workshop on Fully Layout Technology

2002 / 03 / 23

CMOS LAYOUT APPLICATION PNP X 9

N+
NWELL
P+
P+

22

Workshop on Fully Layout Technology

2002 / 03 / 23

CMOS LAYOUT APPLICATION-Power MOS Transistor(1)

ESD PROTECTION

STYLE -1
23

ESD PROTECTION

STYLE -2
/

Workshop on Fully Layout Technology

2002 / 03 / 23

CMOS LAYOUT APPLICATION Power MOS Transistor(2)

N+ DIFF

NWELL

P+ DIFF

POLY

24

Workshop on Fully Layout Technology

2002 / 03 / 23

CMOS LAYOUT APPLICATION- Power MOS Transistor

3

N+DIFF
P+DIFF
NDIFF
POLY

25

Workshop on Fully Layout Technology

2002 / 03 / 23

CMOS LAYOUT APPLICATION Power MOS Transistor

4

>>M2 Finger Structure

M2

M1

26

Workshop on Fully Layout Technology

2002 / 03 / 23

CMOS LAYOUT CASE STUDY

>>OP1
NW
OD
P+
N+
P1
P2
CO
M1
M2
VIA

27

Workshop on Fully Layout Technology

2002 / 03 / 23

CMOS LAYOUT CASE STUDY

>>OP2
444
6

IP
IN

3
5

7 8
28

7 8

NW
OD
P+
N+
P1
P2
CO
M1
M2
VIA
/

Workshop on Fully Layout Technology

2002 / 03 / 23

CMOS LAYOUT CASE STUDY-CIRCUIT

29

Workshop on Fully Layout Technology

2002 / 03 / 23

BIPOLAR ANALOG LAYOUT

BIPOLAR Component Layout Guide
BIPOLAR Layout Application

BIPOLAR Layout Case Study

30

Workshop on Fully Layout Technology

2002 / 03 / 23

BIPOLAR LAYOUT STRUCTURE-VNPN

BL
DC
SP
SN
CO
M1
VIA
M2
TO
CAP
IR

STYLE-1

31

STYLE-2

Workshop on Fully Layout Technology

2002 / 03 / 23

BIPOLAR LAYOUT STRUCTURE-LPNP

BL
DC
SP
SN
CO
M1
VIA
M2
TO
CAP
IR

STYLE-1

32

STYLE-2

STYLE-3

Workshop on Fully Layout Technology

2002 / 03 / 23

BIPOLAR CAPACITOR LAYOUT STRUCTURE

>>Sn-cap type
SN

BL
BIPOLAR-RISISTOR LAYOUT STRUCTURE

MT1

TO
cap
IR
33

SP
/

Workshop on Fully Layout Technology

2002 / 03 / 23

BIPOLAR LAYOUT APPLICATION-VNPN

34

Workshop on Fully Layout Technology

2002 / 03 / 23

BIPOLAR LAYOUT APPLICATION-LPNP

STYLE-1

35

STYLE-2

Workshop on Fully Layout Technology

2002 / 03 / 23

BIPOLAR LAYOUT APPLICATION-LPNP

STYLE-3
36

Workshop on Fully Layout Technology

2002 / 03 / 23

BIPOLAR LAYOUT APPLICATION-Power Transistor

EMIT

37

Workshop on Fully Layout Technology

2002 / 03 / 23

BIPOLAR LAYOUT APPLICATION-VNPN

EMIT

38

Workshop on Fully Layout Technology

2002 / 03 / 23

BIPOLAR LAYOUT CASE STUDY

39

Workshop on Fully Layout Technology

2002 / 03 / 23

BIPOLAR LAYOUT CASE STUDY -CIRCUIT

40

Workshop on Fully Layout Technology

2002 / 03 / 23

BIPOLAR LAYOUT CASE STUDY

41

Workshop on Fully Layout Technology

2002 / 03 / 23

BICMOS ANALOG LAYOUT

BICMOS Component Layout Guide
BICMOS Layout Application

BICMOS Layout Case Study

42

Workshop on Fully Layout Technology

2002 / 03 / 23

BICMOS LAYOUT STURCTURE

43

Workshop on Fully Layout Technology

2002 / 03 / 23

BICMOS LAYOUT STURCTURE-VPNP

>>Double Base
CONTACT

DIFF

PW
P+

N+

44

NWELL

Workshop on Fully Layout Technology

2002 / 03 / 23

BICMOS LAYOUT STURCTURE-LPNP

NWELL
NDIFF

N+BL
PDIFF

POLY

45

Workshop on Fully Layout Technology

2002 / 03 / 23

BICMOS LAYOUT STURCTURE-VNPN

>>Double Base-Base

46

Workshop on Fully Layout Technology

2002 / 03 / 23

BICMOS LAYOUT STURCTURE-RESISTOR

>>Base Resistor

47

>P1 resistor

>P2 resistor

Workshop on Fully Layout Technology

2002 / 03 / 23

BICMOS LAYOUT STURCTURE

>>SNK Capasistor

>>P1-P2 Capasistor
N+INP

48

NWELL

N+BL

Workshop on Fully Layout Technology

2002 / 03 / 23

BICMOS LAYOUT APPLICATION-VNPN

>>

49

Workshop on Fully Layout Technology

2002 / 03 / 23

BICMOS LAYOUT APPLICATION-VNPN

Driver

50

Workshop on Fully Layout Technology

2002 / 03 / 23

BICMOS LAYOUT CASE STUDY-CASE 1

>>OP1

M1 M3 M4
M3 M4 M2

Q2

R2

R2

R2

R2

R2

R2 R2 R2

Q1

IN
IP
Q1

R1

R1

R1

DUMMY

DUMMY

51

R1 R1

Q2

M5 M5

Workshop on Fully Layout Technology

2002 / 03 / 23

BICMOS CASE STUDY OP CIRCUIT

52

Workshop on Fully Layout Technology

2002 / 03 / 23

BICMOS LAYOUT CASE STUDY-CASE 2

AMP

G1

M5
M4

M6

M1
M1

M6

DUMMY

DUMMY

R1 R1 R1

M2

COLLECT

M1

Q3
R2 R3

M2
M2
M3
M3

Q2

Q1

R4 R3 R4 R3
R3

R3 R4 R3 R4

DUMMY

DUMMY

M7

M6
M6

DUMMY

DUMMY

R1 R1 R1 R1 R2 R2 R2 R2

DUMMY DUMMY

R1 R1 R1 R1 R1 R1 R1 R2

M4
M5

M1

DUMMY

DUMMY

DUMMY DUMMY DUMMY DUMMY

53

R1 R1

IN

M3
M2

M3

Workshop on Fully Layout Technology

2002 / 03 / 23

BICMOS CASE STUDY AMP CIRCUIT

54