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Published in IET Power Electronics
Received on 1st October 2012
Revised on 31st January 2013
Accepted on 16th February 2013
doi: 10.1049/iet-pel.2012.0545

ISSN 1755-4535

Design and performance evaluation of a bidirectional

isolated dc–dc converter with extended dual-phase-
shift scheme
Huiqing Wen1, Bin Su2, Weidong Xiao3
1
Department of Electrical and Electronic Engineering, Xi’an Jiaotong-Liverpool University, Suzhou 215123,
People’s Republic of China
2
Hangzhou Electric Power Bureau, State Grid Corporation of China, Hangzhou 310012, People’s Republic of China
3
Electrical Power Engineering Program, Masdar Institute of Science and Technology, Abu Dhabi, UAE
E-mail: Huiqing.Wen@xjtlu.edu.cn

Abstract: This study describes the design and performance evaluation of a bidirectional isolated dc–dc converter with an
extended dual-phase-shift (EDPS) scheme. The operation principle and equivalent circuits with consideration of the deadband
are presented. The deadband effect with EDPS is different from the conventional phase-shift (CPS) scheme, and the
corresponding compensation coefficient is determined. Different operation modes are identified with respect to phase-shift
angles of EDPS and load conditions. The safe operational area is also analysed with the comparison of different operation
modes. The output voltage and output power characteristics with open-loop or closed-loop operation are discussed. The
average theoretical 48.5% reduction in the output voltage ripple using EDPS has been achieved. The average reduction in
inductor peak and rms with EDPS are statistically calculated as 37.8 and 26.8%. The measured efficiency has improved from
68.1% using CPS to 81.9% using EDPS for low-power application.

1 Introduction energy in ultra-capacitors and fuel-cell application [8, 9];

Dual-active-bridge (DAB) converter shows significant
advantages over other bidirectional isolated topologies [1–3]
in terms of soft-switching capability, power controllability
and easy implementation. Thus it has been commonly
adopted in distributed electrical generating system [4],
solid-state transformer [5] and hybrid electric vehicle [6] as
one of core components. Fig. 1 shows the topology and
typical waveforms of an isolated bidirectional DAB dc–dc
converter with the conventional phase-shift (CPS) scheme.
High-frequency gate driving pulses with the same switching
frequency and 50% duty ratio are applied to power devices,
such as metal-oxide semiconductor field-effect transistors
(MOSFETs) or insulated gate bipolar transistors, which are
located on the primary and secondary sides of transformer
Tr. The inductor Ls serves as an instantaneous
energy-storage component. VL and iL shown in Fig. 1a
represent the voltage across inductor Ls and the current
flowing through Ls, respectively. The voltage difference
between vT1 and vT2 can be regulated by the phase shift
between the primary and secondary bridges, and determines
the current through the inductor Ls.
Current research on the DAB converter is found to mainly
focus on the following subjects listed below:
1. Various applications: Interfacing photovoltaic generation
systems to homes and office buildings [7]; storing electric
power distribution system in microgrid [10].
2. Power characteristics and stability analysis in steady-state
operation: The power transmission expression analysis and
verification [11]; the dc-bias currents, resulting in the
magnetic-flux saturation of the transformer [12]; the
stability analysis using Lyapunov function method [13].
3. Advanced modulation strategies to restrain current stress
and reactive power produced by CPS [14, 15]: Phase-shift
plus pulse width modulation with the aim to obtain the
optimal selection of phase shift angle and modulation duty
ratio [16, 17]; the triangular modulation [18], the
trapezoidal modulation [19] and the hybrid modulation
according to power loss models and the classification of
output power levels [8, 20]; and the dual-phase-shift (DPS)
modulation [14, 21].
4. Short-timescale transients with CPS: The deadband effect
with CPS [6]; the current variations and the ‘energy
deadband’ [22]; three phenomena including internal power
transfer, phase drift and low system efficiency, with
consideration of ‘minor parameters’ like device voltage
drop and deadband [23].
In this paper, a novel extended dual-phase-shift (EDPS)
scheme is proposed with in-depth investigation of key
design issues. Different from the conventional DPS
scheme [14], the phase shift between diagonal devices on
the same side is exerted on the high-voltage side with

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Fig. 1 Topology and typical waveforms of a dual-active-bridge dc–dc converter with CPS scheme
a Topology
b Typical waveforms
EDPS and only the output voltage of this side is of
three-level. Compared with DPS, EDPS can further reduce
the reactive circulating current and the current stress
especially for middle- and high-power applications.
Besides, EDPS shows the feature of easy-to-implement.
However, the prior studies with the advanced modulation
strategies show significant limitations that can be
summarised as below:
† The prior studies are originated from the ideal power flow
model and neglect the effect of ‘minor parameters’ like
deadband, considering the complexity of the actual power
flow model. The prior research on short-timescale transients
is just focused on CPS.
† Key design issues such as voltage ripple and safe
operational area (SOA) with advanced modulation strategies
are usually neglected.
Fig. 2 Typical waveforms of the dual-active-bridge converter with EDPS scheme
a Forward mode
b Backward mode
IET Power Electron., 2013, Vol. 6, Iss. 5, pp. 914–924
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Thus, the ‘minor parameters’ like deadband effect and key
design issues should be considered in the design and
performance evaluation of EDPS controlled converter. In
order to avoid the limitation discussed above, each
operating stage with its equivalent circuit using EDPS
scheme is investigated with the insertion of the deadband.
The comprehensive design and performance evaluation with
EDPS are provided, which include long-timescale
steady-state operations, such as output voltage and power
with open-loop or closed-loop control, SOA, efficiency, and
short-timescale phenomenon such as the deadband effect.
The corresponding performance with CPS is adopted as
benchmark. With the optimal operating mode of EDPS, the
average 48.5% reduction in the output voltage ripples has
been achieved. The average reduction in peak and rms with
EDPS are statistically calculated as 37.8 and 26.8%. The
measured efficiency has improved from 68.1% using CPS
to 81.9% using EDPS for low-power application.
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This paper is organised as follows: Section 2 presents the
operation principle and the equivalent circuits with
consideration of the deadband. Section 3 illustrated the
steady-state characteristics with EDPS, which include
different operation modes, output voltage and power with
open-loop or closed-loop operation. Section 4 shows two
special design issues, which are SOA and deadband effect.
Section 5 shows the main performance evaluation with
EDPS in terms of output voltage ripple and efficiency.
2 Operation principle of EDPS controlled
converter
To simplify the analysis, the operation of EDPS controlled
converter is explained with the following assumptions: (i)
the converter has reached the steady state; (ii) the
inductance Ls is composed of the leakage inductance of
transformer Tr and additional series inductance; and (iii) the
Fig. 3 Equivalent circuits of EDPS controlled converter for forward operation
a Stage 1 [t0–t1]
b Stage 2 [t1–t2]
c Stage 3 [t2–t3]
d Stage 4 [t3–t4]
e Charge–discharge equivalent circuit in Stage 5 [t4–t5]
f Diode conduct equivalent circuit in Stage 5 [t4–t5]
g Stage 6 [t5–t6]
h Stage 7 [t6–t7]
i Charge–discharge equivalent circuit in Stage 8 [t7–t8]
j Diode conduct equivalent circuit in Stage 8 [t7–t8]
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variation in the input voltage vS1, which is shown in Fig. 1,
is negligible during a switching period.
Two phase shifts are adopted in the EDPS scheme, and the
corresponding phase-shift ratios are D1 and D2. D1 represents
the phase shift between the diagonal control signals of the
high-voltage side, for instance, the gate signals of Q11 and
Q14 for the buck operation; D2 represents the phase shift
between the primary and the corresponding secondary gate
driving signals, for instance, the gate signals of Q11 and
Q21. Typical waveforms of DAB converter with EDPS for
the forward and backward modes are shown in Fig. 2. In
this study, the forward mode for buck operation is
discussed. For other operating modes, the main differences
are reflected on the waveform of inductor current iL. In a
complete switching cycle, the operation with EDPS can be
divided into 17 stages and only 8 stages are analysed here,
considering the symmetry of the circuit. The deadband is
inserted in the typical waveforms in order to analyse its
effect. Fig. 3 illustrates the equivalent circuits for each
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Fig. 4 Complete operating modes of EDPS considering the distribution of reactive current for boost operation
a EDPS_I
b EDPS_II
c EDPS_III

stage, where main energy exchanging components are
highlighted to illustrate the power flow process in each stage.
Stage 1 [t0–t1]: Q11 is turned off and the antiparallel diode
DQ11 is conducting to freewheel the current iL because iL is
in the negative direction. The primary current is
freewheeling through DQ11 and Q13. RQ13 represents the
on-resistance of Q13. The secondary current flows through
Q22 and Q23. The primary voltage vT1shows the diode
conduction voltage and the secondary voltage vT2 is negative.
Stage 2 [t1–t2]: At t1, Q11 will turn on and the primary
current will flow through Q11/Q13 because the voltage drop
across MOSFET when it conducts is lower than the
conduction voltage drop of diode. The current will
commutate from DQ11 to Q11. Thus, Q11 is zero-voltage
soft-switching on at this condition. The secondary current
flows through Q22 and Q23. The primary voltage vT1 is
zero and the secondary voltage vT2 is negative. The
inductor releases the energy and the current changing slope
of iL is


diL /dt = VS2 / NLs (1)
Stage 3 [t2–t3]: Q22 and Q23 are turned off at t2. Their
antiparallel diodes DQ22 and DQ23 are conducting to
freewheel the current iL because iL is in the negative
direction. The primary current flows through Q11/Q13. The
inductor releases the stored energy and the voltage vCS2 is
still increasing. The process and the corresponding
equivalent circuit of this stage are shown in Fig. 3c.
Stage 4 [t3–t4]: At t3, Q21 and Q24 are turned on and the
secondary current commutates from DQ22/DQ23 to Q21/Q24.
The capacitor CS2 discharges and provides energy. This
energy will transfer from the secondary side to the primary
side in this stage. The corresponding slope of iL is given by
Stage 6 [t5–t6]: At t5, Q14 is turned on under zero-voltage
condition. The current iL increases linearly and the
corresponding slope is
 
diL /dt = VS1 − VS2 /N /Ls (3)
Stage 7 [t6–t7]: t6 corresponds to the zero crossing instant of
the inductor current iL. During this interval, the input voltage
vS1 provides the power to the load and compensates the power
loss in inductor L and output capacitor CS2.
Stage 8 [t7–t8]: Q11 is turned off at t7. The capacitor in parallel
with Q11 is charged linearly and the capacitor in parallel with
Q12 is discharged until its voltage drop to the forward
conduction voltage of DQ12. Then, the secondary current
will freewheel through Q14/DQ12. At t8, Q12 is turned on in
zero-voltage condition. VT1 is zero and VT2 is positive. The
corresponding equivalent circuits in this stage are shown in
Figs. 3i and j. The current iL reduces linearly and the slope is


diL /dt = −VS2 / NLs (4)
A similar operation can be analysed for the rest of the stages.
For the backward mode, the main difference is that VT1 is
lagging to VT2 and its typical waveforms are shown in
Fig. 2b. The complete operations for backward mode in a
switching cycle can also be divided into 17 stages and the
power flow analysis is similar to that of the forward mode.
3 Steady-state characteristics with EDPS
3.1 Operating modes with EDPS
Different from CPS, there are possible multiple zero crossing
points of iL in the half switching cycle with EDPS. Figs. 4a–c


diL /dt = −VS2 / NLs (2)
Table 1 Expressions of current at the switching angles with
EDPS (pu)
Stage 5 [t4–t5]: Q13 is turned off at t4. The capacitor in Modes iL(0) iL(δ1) iL(δ2) iL(π)
parallel with Q13 is charged linearly and the capacitor in
parallel with Q14 is discharged until its voltage drop to the d≥1 −dD1 − −dD1 − dD2 −d + dD2 + dD1 +
forward conduction voltage of DQ14. Then, the primary dD2 + d − 1 + d − 1 + 2D2 dD1 − 2D1 + dD2 − d +
current will flow through Q11/DQ14. The transformer 1 1
d<1 D1 + D2 + d D1 + D2 + d − −D1 − D2 − −D1 −
primary voltage includes the input voltage vS1 and the −1 1 − 2dD1 d + 2dD2 + 1 D2 − d + 1
conduction voltage of DQ14.

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illustrate the complete operating modes with EDPS
considering the distribution of reactive current. As shown in
Fig. 4, for boost operation, EDPS _I and EDPS _III have
one zero crossing point of iL in the half switching cycle,
and EDPS _II shows three zero crossing points. Similarly,
the complete operating modes with EDPS for buck
considering the distribution of reactive current can be
obtained. For the extreme mode ‘d = 1’, only EDPS_I exists
and iL will remain constant during the time interval [δ1, δ2].
Table 1 shows the analytical expressions of iL at switching
angles with EDPS. The voltage conversion ratio d is defined
as


d = VT 2 / NVT1
All quantities shown in Table 1 are normalised with the
following base values



Ib = VS1 / 4Ls fs , Pb = VS21 / 4Ls fs
cycle. Fig. 4 also shows that there is only one operating
mode, EDPS_III. Thus, the distribution of load conditions
with EDPS is different from CPS because there is one more
variable to tune iL(0). The operating modes corresponding
to the heavy-load conditions for d > 1, d = 1 and d < 1 are
validated by the experimental waveforms, as shown in Fig. 5.
3.2 Output voltage
Fig. 2 shows the typical waveform of the output voltage vCS2,
which is directly linked with the inductor current waveform.
Considering the current distribution for different operating
modes shown in Fig. 4, the average inductor current in a
(5) switching period can be derived as (7) combining with the
current expressions in Table 1.

 


IS1 = iL (0) + iL d1 D2 + iL d1 + iL d2

 
 
1 − D1 − D2 + iL d2 + iL (p) D1



(6) V S2 D 2 − D1 1 − D1 − D2
= (7)
4NLs fs

where fs is the switching frequency. The variables VS1 , fs and Thus, the delivered power from VS1 is expressed as
Ls affect only the magnitude of Po. Table 1 shows that the
phase-shift pair (D1, D2) determines solely the operating P1 = VS1 IS1
modes and the amount of output power. 



Under heavy load conditions, iL increases from an initial = VS1 VS2 D2 − D1 1 − D1 − D2 / 4NLs fs (8)
negative value in a switching cycle. As shown in Fig. 4,
there are two operating modes, EDPS_I and EDPS_II, The output power can be expressed according to the output
which are corresponding to the heavy load conditions for voltage and load resistance as
boost operation. Under light load conditions, iL increases
from a positive value at the beginning of the cycle, and
drops to a negative value at the end of the half switching Po = VS22 /RL (9)

Fig. 5 Experimental waveform of vT1, vT2, and iL for different steady-state operation modes under the heavy-load conditions
a EDPS_I for d > 1
b EDPS_II for d > 1
c EDPS_III for d = 1
d EDPS_III for d < 1

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Without considering the deadband and voltage drop, the
output voltage and current can be expressed as (10)
according to the ideal power flow model of DAB converter.



 power of DAB converter with EDPS can be obtained as (13)
VS2 = VS1 RL D2 − D1 1 − D1 − D2 / 4NLs fs (10)




IS2 = Io = VS1 D2 − D1 1 − D1 − D2 / 4NLs fs (11)
2
Thus, for the given parameters of fs, Ls, N and VS1 , the output
voltage VS2 is proportional to RL and dependent on the
phase-shift pair (D1, D2). For a given RL, the output voltage
reaches maximum when D1 = 0 and D2 = 0.5. For a given
(D1, D2), the output voltage is directly proportional to RL.
The boundary condition to achieve NVS1 = VS2 is obtained as

 


RL1 = 4N 2 Ls fs / D2 − D1 1 − D1 − D2 (12)
The deadband effect on the output voltage and output power
is analysed in the following section.
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3.3 Output power
The effective active power transfer stage is stage 7 according
to the equivalent circuits shown in Fig. 3. The average output
by combining (10) and (9).
V S1
2
2
Po = D2 − D1 1 − D1 − D2 R L (13)
4NLs fs
According to (13), Po always has the maximum value when
D1 = 0 and D2 = 0.5 whether for a fixed resistance or the
voltage closed-loop operation. For a given phase-shift pair,
VS2 and Po will increase with RL according to (10) and (13).
The initial current iL(0) will also increase with RL according
to expressions shown in Table 1. The EDPS controlled
converter will switch from heavy-load operation to
light-load operation. For the voltage closed-loop operation,
the decreasing RL results in the increase of Po. Thus, in
order to maintain VS2 as constant, the phase-shift pair has to

Fig. 6 Simulated iL using EDPS for open-loop and closed-loop operations

a Closed-loop operation with VS2 = 200 V, RL = 1000 Ω, Po = 40 W
b Closed-loop operation with VS2 = 200 V, RL = 260 Ω, Po = 153.8 W
c Open-loop operation with D1 = 0.1, D2 = 0.3, RL = 200 Ω, Po = 66.8 W
d Open-loop operation with D1 = 0.1, D2 = 0.3, RL = 500 Ω, Po = 166.5 W
e Relationship of iL(0) using EDPS with Po for voltage closed-loop control and VS2 = 200 V
f Relationship of iL(0) using EDPS with Po for open-loop control and D1 = 0.1, D2 = 0.3

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be tuned according to the expression as


 with EDPS are adopted, and the required phase-shift angles
D2 − D1 1 − D1 − D2 / 1/RL
For fixed VS1 and VS2 , Po reaches the maximum value when
D1 = 0 and D2 = 0.5. For this condition, the corresponding
RL is expressed as
RL2 = 16NLs fs VS2 /VS1
Theoretically, further decreasing RL, which is even lower than
RL2, will result in the increasing of Po according to (9).
However, because of the constraint of the maximum output
power, which corresponds to the load resistance RL2, the
output voltage will not maintain a constant and the system
will enter the open loop, which corresponds to D1 = 0 and
D2 = 0.5. When the system is in the voltage closed-loop
operation, Po will increase with the decreasing of the initial
current iL(0) according to the expressions shown in Table 1.
Fig. 6 shows the simulated waveform of iL using EDPS for
open-loop and closed-loop operation. The main parameters
are: VS1 = 20 V, N = 6, Ls = 1.73 μH, fs = 100 kHz. Figs. 6a
and b show the closed-loop operation, where iL(0)
decreases from positive value to negative value with the
increase of Po. In Figs. 6c and d, with the increase of Po,
iL(0) will increase from the negative value to positive value
under the open-loop operation. Thus, the trends are opposite
for the two operations. The relationship of iL(0) using
EDPS with Po for open-loop and voltage closed-loop
operations are illustrated. The voltage closed-loop operation
with constant output voltage VS2 = 200 V is shown in
Fig. 6e. The open-loop operation with a fixed phase-shift
pair of D1 = 0.1, D2 = 0.3 is shown in Fig. 6f.
4 Special design issues with EDPS
4.1 Deadband effect
Deadband are commonly inserted between the interlocked
MOSFETs of the same bridge in order to avoid
shoot-through. However, the deadband will affect the power
flow characteristic of EDPS controlled converter. As shown
in Fig. 2, the deadband td will erase the equivalent pulse
width of MOSFETs in the high-voltage side. Besides,
waveform distortion and other unexpected short-timescale
phenomena can be induced.
Fig. 7 Effect of the deadband using EDPS against output power Po when ‘D1 = 0.02’
a Comparison of the practical phase-shift angle using different deadband parameters against Po
b Relationship of the compensation coefficient k against Po
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In order to investigate the deadband effect in-depth,
different deadband parameters of ‘db = 0.02, 0.03 and 0.04’
(14)
to maintain the same output power as that without
deadband are obtained and shown in Fig. 7a. In this study,
D1 is set to 0.02 and D2 is tuned to maintain the constant
output power. Fig. 7 shows that the maximum output power
is reduced accordingly with the insertion of td. In order to
maintain the same output power as that without td, an
(15) additional compensation phase-shift angle should be
inserted except for the calculated value, which is derived
from the ideal power flow model. A compensation
coefficient k is adopted and defined as
f = f∗ + k × fdb (16)
where φ* is the ideal phase-shift angle. Fig. 7b also illustrates
the relationship of compensation coefficient k against output
power Po. In Fig. 7, the dashed black line shows the
required D2 without the insertion of deadband. The solid
blue, magenta and red lines show the D2 with different
deadband parameters of ‘0.02, 0.03 and 0.04’. Fig. 7a
shows that a bigger phase-shift variable D2 is required
when a larger deadband td is adopted. This conclusion is
also verified by the relationship of the compensation
efficiency k with Po. The compensation coefficient k is
statistically calculated as 2.4. However, the corresponding
average compensation coefficient k using CPS is 1. Besides,
the output voltage in the deadband is determined by the
current direction and the compensation phase shift is
required for ‘iL(0) > 0’.
4.2 SOA design
The inductor peak current iLpeak in a switching period can be
derived from Fig. 4 and the expressions shown in Table 1. For
d > 1, iLpeak corresponds to iL(δ1) or iL(π) for EDPS_I and
EDPS_II, iL(δ1) for EDPS_III. The inductor rms current in
a switching period Irms can be derived similarly. Take
EDPS_II as an example to show the process. First, based
on the dynamics of iL, as shown in Fig. 4, the expressions
of the angle β with EDPS_II are obtained and shown as
⎧

⎨ bEDPS II 1 =
dD1 + dD2 − d + 1p/2
b =
dD2 − dD1 + d − 1 p/[2(d − 1)] (17)
⎩ EDPS II 2
bEDPS II 3 = −dD1 − dD2 + d + 1 p/2
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Fig. 8 SOA design with EDPS

a Relationship of the inductor peak current iLpeak with Ls and fs
b Comparison of the optimised inductor current rms Irms using EDPS with respect to the phase-shift variable D2 for three different output power levels
c Relationship of the optimised inductor rms current Irms with Ls under different switching frequency fs

According to the typical inductor current waveform shown in
Fig. 4, the mathematical expression of the inductor rms
current (per unit) then can be derived as (see (18))
The SOA design is essential to guarantee the safe operation
of power devices such as MOSFETs. One of the major issues
considering the SOA design is the determination of the range
of key parameters such as the leakage inductance Ls and
switching frequency fs. Fig. 8a shows the calculated results
of the inductor peak current iLpeak with EDPS as a function
of Ls and fs through simulation. The range of fs is initially
set as 50–500 kHz considering the application
characteristics of MOSFETs. Fig. 8a shows that iLpeak drops
dramatically with the increase of fs. The inductance Ls also
determines the inductor peak current iLpeak. With a fixed
value of fs, a large inductance of Ls will reduce iLpeak,
however, large Ls will limit the maximum output power of
EDPS controlled converter according to (13).
The rms current of the transformer primary side Irms could
be calculated according to (18). Owing to one more
phase-shift variable using EDPS, Irms can be tuned to
achieve the minimum. Fig. 8b shows the optimised Irms
using EDPS against the phase-shift variable D2 for three
different output power levels. The main parameters are
listed as: VS1 = 20 V, d = 1.5, N = 6, Ls = 1 μH, fs = 50 kHz.
The dash lines show the boundaries of different operating
modes using EDPS. As shown in Fig. 8b, the operating
modes are arranged as ‘EDPS_III’, ‘EDPS_II’ and
‘EDPS_I’ from the left to right. The distinctive features for
these operating modes of EDPS are shown in Fig. 8b.
However, EDPS_II always shows the lowest rms current for
all output power levels.
The relationship of the minimum Irms with EDPS against
the inductance Ls under different switching frequency fs are
derived and shown in Fig. 8c for ‘Po = 200 W’. The rms
current limit of MOSFET is set at 30 A, shown as the
green solid line in Fig. 8c. The derived inductance range
should be between 0.7 and 3.6 μH if the MOSFETs are
operated at 50 kHz. If Ls < 0.7 μH, the inductor rms current
will exceed the threshold of 30 A. If Ls > 3.6 μH, the 200
W output power will not be achievable. As shown in
Fig. 8c, the inductance ranges with fs = 100 kHz and fs =
200 kHz are [0.3 μH, 1.8 μH] and [0.2 μH, 0.9 μH],
respectively, which are significantly narrower than that
with fs = 50 kHz.






2

2

Irms = iL (0) bEDPS II 1 + 1 − bEDPS II 3 + iL d1 bEDPS II 2 − bEDPS II 1 + iL d2 bEDPS II 3 − bEDPS II 2 /3
2



3
3
3 
= 2(d − 1) dD1 + dD2 − d + 1 − d −d + dD2 + dD1 − 2D2 + 1 −d −d + dD2 + dD1 − 2D1 + 1 /(6(d − 1))

(18)

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Fig. 9 Output voltage ripple using EDPS

a Capacitor current ripple distribution with EDPS (boost)
b Capacitor current ripple distribution with EDPS (buck)
c Experimental waveform of iB2 using CPS for ‘d = 1.7’
d Experimental waveform of iB2 using EDPS_II for ‘d = 1.7’
e Comparison of the capacitor voltage ripple ratio using CPS and EDPS_II against Po

5 Performance evaluation the following expression

5.1 Output voltage ripple

 VS − VS2 /N
iL d1 /N + 1 DT = Io (20)
The output voltage ripple is determined by the current flowing NLs
through the output capacitor, which is the combination of the
current iB2 and the load current Io. Fig. 2 shows the typical
waveform of the output voltage vCS2. In stages 4–6, the Thus
output capacitor will release energy and the output voltage
will drop, as shown in Fig. 3. The capacitor current ripple

NIo − iL d1
distribution with EDPS for boost and buck operation is DT = L (21)
illustrated in Figs. 9a and b, respectively. Then, the VS1 − VS2 /N s
capacitor current can be written as
The output voltage ripple is derived as

−Io 0 ≤ t ≤ d1 , d2 ≤ t ≤ p
iC = (19) D2 Ts +DT

iL /N − Io d1 ≤ t ≤ d2 1 iL (t)
DVS2 = − Io dt
CS2D2 Ts N


 
DT iL d1
The duration of the positive capacitor current iC is symbolised = − Io (22)
as ΔT. According to Fig. 9, the capacitor current meets 2CS2 N

922 IET Power Electron., 2013, Vol. 6, Iss. 5, pp. 914–924

& The Institution of Engineering and Technology 2013 doi: 10.1049/iet-pel.2012.0545
 www.ietdl.org

Fig. 10 Comparison of the inductor peak current and the rms current of DAB converter using CPS and EDPS_II against the output power
a Experimental waveforms with CPS
b Experimental waveforms with EDPS_II
c Comparison of the calculated inductor peak current
d Comparison of the calculated inductor rms current

  current of DAB converter using CPS, DPS and EDPS_II
DVS2 DT iL d1
DVS2 % = = − Io (23)
V S2 2VS2 CS2 N rms current are dramatically reduced with the proposed
Substitute (10), (11), (21) and the current expression in
Table 1 to (23), the expression for DVS2 %; can be obtained
as (see (24))
As shown in (24), the output voltage ripple is a function of
CS2, RL, d, N and the phase-shift pair (D1, D2). For the given
parameters of CS2, RL, d, N, the voltage ripple can be
regulated through phase-shift pair, which adds one more
tuning parameter compared with CPS. Figs. 9c and d show
the experimental waveforms of iB2 using CPS and EDPS_II.
The measured ripple rms value of iB2 is smaller than that
of CPS. The current ripple of iB2 with EDPS_II is
discontinuous in the switching period. However, the current
ripple of iB2 with CPS is always fluctuating and continuous.
Fig. 9e shows the comparison of the output voltage ripple
ratio using CPS and EDPS with respect to the output power
Po. Significant reduction of voltage ripple has been
illustrated and the average reduction is statistically
calculated as 48.5%. The minimised output voltage ripple
also reflects the significant reduction in reactive circulating
current by using EDPS.
5.2 Efficiency
Figs. 10a and b show the experimental waveforms of vT1, vT2
and iL using CPS and EDPS_II. Figs. 10c and d show the
comparison of the calculated peak current and the rms
with respect to the output power Po. Both the peak and the
EDPS for the whole output power range. The average
reduction in peak and rms are statistically calculated as 37.8
and 26.8%. The measured efficiency is improved from
68.1% using CPS to 81.9% using EDPS_II for ‘Po = 25 W’.
Figs. 10c and d also show the comparison of the inductor
peak and rms current using DPS and EDPS. This
comparison shows that EDPS can further reduce the
reactive circulating current and the current stress especially
for middle and high power range compared with DPS.
6 Conclusion
This paper presents the operation, design and performance
characteristics of an isolated bidirectional DAB dc–dc
converter with the proposed EDPS scheme. The
comprehensive analysis is provided, which includes the
determination of key parameter such as the leakage
inductance Ls and switching frequency fs, detailed operating
stages analysis with their equivalent circuits, long-timescale
steady-state operations such as output voltage and power
with open-loop or closed-loop control, and short-timescale
phenomenon such as the deadband effect. Compared with
CPS scheme, the EDPS can improve both the static and
dynamic performance of the DAB converter because of the
flexibility of two degrees of freedom tuning. With the
optimal operating mode of EDPS, the average 48.5%
reduction in the output voltage ripples has been achieved.

2
N 2 Ls D21 − D22 + dD1 + dD2 − D1 − D2 + 1 − d
DVS2 % =


 (24)
2CS2 RL D2 − D1 1 − D1 − D2 RL D21 − RL D22 − RL D1 + RL D2 − 4Ls fs N 2

IET Power Electron., 2013, Vol. 6, Iss. 5, pp. 914–924 923

doi: 10.1049/iet-pel.2012.0545 & The Institution of Engineering and Technology 2013
www.ietdl.org
Experiments show that the average reduction in peak and rms
with EDPS are statistically calculated as 37.8 and 26.8%. The
measured efficiency has improved from 68.1% using CPS to
81.9% using EDPS for low-power application.
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IET Power Electron., 2013, Vol. 6, Iss. 5, pp. 914–924
doi: 10.1049/iet-pel.2012.0545