VLSI TEST AND TESTABILITY DFT ADVISOR REPORT

VLSI TEST AND TESTABILITY
DFT ADVISOR REPORT
Siddhi Karadkhedkar (2017H1230067H)

Palem Shaik Sumiya (2017H1230080G)
Anisha Nayak (2017H1230073G)
Area Report
*******************************************************
Cell: mod_12ctr View: INTERFACE Library: work
*******************************************************
Number of ports : 6
Number of nets : 15
Number of instances : 11
Number of references to this view : 0
Total accumulated area :

Number of gates : 27
Number of accumulated instances : 11
Info, Command 'report_area' finished successfully
Verilog Netlist
// Verilog description for cell mod_12ctr,

// Thu Nov 22 05:58:04 2018
//
// LeonardoSpectrum Level 3, 2011a.4
//
module mod_12ctr ( clk, reset, q ) ;
input clk ;
input reset ;
output [3:0]q ;
wire nx100, nx101, nx8, nx28, nx40, nx60, nx113, nx115, nx121;
wire [1:0] \$dummy ;
dff reg_q_0 (.Q (q[0]), .QB (\$dummy [0]), .D (nx60), .CLK (clk)) ;
nor02 ix61 (.Y (nx60), .A0 (q[0]), .A1 (nx101)) ;
nor04 ix41 (.Y (nx40), .A0 (nx113), .A1 (nx115), .A2 (nx100), .A3 (reset)) ;
dff reg_q_3 (.Q (q[3]), .QB (nx113), .D (nx40), .CLK (clk)) ;
dff reg_q_2 (.Q (q[2]), .QB (nx115), .D (nx28), .CLK (clk)) ;
nor04 ix29 (.Y (nx28), .A0 (nx100), .A1 (nx115), .A2 (nx113), .A3 (reset)) ;
and02 ix17 (.Y (nx100), .A0 (q[1]), .A1 (q[0])) ;
dff reg_q_1 (.Q (q[1]), .QB (\$dummy [1]), .D (nx8), .CLK (clk)) ;
nor03 ix9 (.Y (nx8), .A0 (nx121), .A1 (nx100), .A2 (nx101)) ;
nor02 ix122 (.Y (nx121), .A0 (q[0]), .A1 (q[1])) ;
or03 ix55 (.Y (nx101), .A0 (nx113), .A1 (reset), .A2 (nx115)) ;
endmodule
DFT Scan Identification

// Flattening process completed, design_cells=11 leaf_cells=11 library_primitives=19
sim_gates=31 PIs=2 POs=4 CPU time=0.00 sec.
// ---------------------------------------------------------------------------
// Begin circuit learning analyses.
// --------------------------------
// Learning completed, CPU time=0.00 sec.
// ---------------------------------------------------------------------------
// Begin scan chain identification process, memory elements = 4.
// ---------------------------------------------------------------------------
// ---------------------------------------------------------------------------
// Begin scannable cell rules checking for 4 nonscan memory elements.
// ---------------------------------------------------------------------------
// 4 non-scan memory elements identified as scannable.
// ---------------------------------------------------------------------------
// Begin scan clock rules checking.
// ---------------------------------------------------------------------------
// 1 scan clock/set/reset lines have been identified.
// All scan clocks successfully passed off-state check.
// 4 sequential cells passed clock stability checking.
// ---------------------------------------------------------------------------
// Begin shift register identification process for 4 sequential instances.
// ---------------------------------------------------------------------------
// No shift registers identified.
// Number of targeted sequential instances = 4
// Performing scan identification ...
// Total sequential instances identified = 4
Netlist by DFT
/*
* DESC: Generated by DFTAdvisor at Thu Nov 22 06:24:06 2018
*/
module mod_12ctr ( clk , reset , q , scan_in1 , scan_out1 , scan_en );
input clk , reset , scan_in1 , scan_en ;
output scan_out1 ;
output [3:0] q ;
wire nx100 , nx101 , nx8 , nx28 , nx40 , nx60 , nx113 , nx115 , nx121 ;
wire [1:0] \$dummy ;
sff reg_q_0 (.D ( nx60 ) , .SI ( q[3] ) , .SE ( scan_en ) , .CLK ( clk ) ,
.Q ( q[0] ) , .QB ( \$dummy [0] ));
nor02 ix61 (.A0 ( q[0] ) , .A1 ( nx101 ) , .Y ( nx60 ));
nor04 ix41 (.A0 ( nx113 ) , .A1 ( nx115 ) , .A2 ( nx100 ) , .A3 ( reset ) ,
.Y ( nx40 ));
sff reg_q_3 (.D ( nx40 ) , .SI ( scan_in1 ) , .SE ( scan_en ) , .CLK ( clk ) ,
.Q ( q[3] ) , .QB ( nx113 ));
sff reg_q_2 (.D ( nx28 ) , .SI ( q[1] ) , .SE ( scan_en ) , .CLK ( clk ) ,
.Q ( q[2] ) , .QB ( nx115 ));
nor04 ix29 (.A0 ( nx100 ) , .A1 ( nx115 ) , .A2 ( nx113 ) , .A3 ( reset ) ,
.Y ( nx28 ));
and02 ix17 (.A0 ( q[1] ) , .A1 ( q[0] ) , .Y ( nx100 ));
sff reg_q_1 (.D ( nx8 ) , .SI ( q[0] ) , .SE ( scan_en ) , .CLK ( clk ) , .Q
( q[1] ) , .QB ( \$dummy [1] ));
nor03 ix9 (.A0 ( nx121 ) , .A1 ( nx100 ) , .A2 ( nx101 ) , .Y ( nx8 ));
nor02 ix122 (.A0 ( q[0] ) , .A1 ( q[1] ) , .Y ( nx121 ));
or03 ix55 (.A0 ( nx113 ) , .A1 ( reset ) , .A2 ( nx115 ) , .Y ( nx101 ));
assign scan_out1 = q[2] ;
endmodule
Test Scan
---------------------------------------------------------------------------
// Begin scan cell distribution process...
// ---------------------------------------------------------------------------
// Chain allocation per clock/edge domain:
// domain[0]: #cells:4, #chains:1
report statistics (DFT)
Total number of sequential instances = 4
Number of inserted scan chains = 1
Number of new pins inserted = 3
ATPG Faults
------------------------------------------------------------------------
// Simulation performed for #gates = 34 #faults = 81
// system mode = ATPG pattern source = internal patterns
// ------------------------------------------------------------------------
// #patterns test #faults #faults # eff. # test process RE/AU/AAB
// simulated coverage in list detected patterns patterns CPU time
// begin random patterns: capture clock = /clk, observe point = MASTER
// 64 54.31% 53 28 3 3 0.00 sec
// 128 92.24% 9 44 4 7 0.00 sec
// 192 98.28% 2 7 1 8 0.00 sec
// 256 100.00% 0 2 1 9 0.00 sec
Test Proc File
//
// Generated by DFTAdvisor at Thu Nov 22 06:26:39 2018
//
set time scale 1.000000 ns ;
timeplate gen_tp1 =
force_pi 0 ;
measure_po 10 ;
pulse_clock 20 10 ;
period 40 ;
end;
procedure shift =
scan_group grp1 ;
timeplate gen_tp1 ;
// cycle 1 starts at time 0
cycle =
force_sci ;
measure_sco ;
pulse clk ;
end;
end;
procedure load_unload =
scan_group grp1 ;
timeplate gen_tp1 ;
// cycle 1 starts at time 0
cycle =
force clk 0 ;
force scan_en 1 ;
end ;
apply shift 4;
end;
Report Statistics
Statistics Report
Stuck-at Faults
--------------------------------------
Fault Classes #faults
(total)
---------------------- --------------
FU (full) 120
-------------------- --------------
DS (det_simulation) 81 (67.50%)
DI (det_implication) 35 (29.17%)
UU (unused) 4 ( 3.33%)
--------------------------------------
Coverage
--------------------
test_coverage 100.00%
fault_coverage 96.67%
atpg_effectiveness 100.00%
--------------------------------------
#test_patterns 9
#simulated_patterns 320
CPU_time (secs) 0.3

Test Pattern File
//
// Tessent FastScan 2015.4
//
// Design = /home/2017_1/DFT_SSA/mod_12ctr_net.v
// Created = Thu Nov 22 06:36:55 2018
//
// Statistics:
// Test Coverage = 100.00%
// Total Faults = 120
// DS (det_simulation) = 81
// DI (det_implication) = 35
// UU (unused) = 4
// Total Patterns = 9
//
// Settings:
// Simulation Mode = combinational, seq_depth = 0
// Fault Type = stuck
// Fault Mode = uncollapsed
// Pos_Det Credit = 50%
// Z external = X
// Z internal = X
// wired_net = WIRE
//
// Warnings:
//
// Clock Information:
// /clk off-state = 0 type = shift-MASTER poflag = 0
//
ASCII_PATTERN_FILE_VERSION = 3;
SETUP =
declare input bus "PI" = "/clk", "/reset", "/scan_in1", "/scan_en";
declare output bus "PO" = "/q[3]", "/q[2]", "/q[1]", "/q[0]", "/scan_out1";
clock "/clk" =
off_state = 0;
pulse_width = 1;
end;
scan_group "grp1" =
scan_chain "chain1" =
scan_in = "/scan_in1";
scan_out = "/scan_out1";
length = 4;
end;
procedure shift "grp1_load_shift" =
force_sci "chain1" 0;
force "/clk" 1 20;
force "/clk" 0 30;
period 40;
end;
procedure shift "grp1_unload_shift" =
measure_sco "chain1" 10;
force "/clk" 1 20;
force "/clk" 0 30;
period 40;
end;
procedure load "grp1_load" =
force "/clk" 0 0;
force "/scan_en" 1 0;
apply "grp1_load_shift" 4 40;

end;
procedure unload "grp1_unload" =
force "/clk" 0 0;
force "/scan_en" 1 0;
apply "grp1_unload_shift" 4 40;
end;
end;
end;
CHAIN_TEST =
pattern = 0;
apply "grp1_load" 0 =
chain "chain1" = "0011";
end;
force "PI" "0XXX" 1;
measure "PO" "XXXXX" 2;
apply "grp1_unload" 3 =
end;
end;
SCAN_TEST =
pattern = 0;
end;
force "PI" "0100" 1;
measure "PO" "01011" 2;
pulse "/clk" 3;
end;
pattern = 1;
end;
force "PI" "0100" 1;
measure "PO" "10100" 2;
pulse "/clk" 3;
end;
pattern = 2;
end;
force "PI" "0110" 1;
measure "PO" "11101" 2;
pulse "/clk" 3;
end;
pattern = 3;
end;
force "PI" "0010" 1;
measure "PO" "01011" 2;
pulse "/clk" 3;

end;
pattern = 4;
end;
force "PI" "0000" 1;
measure "PO" "11001" 2;
pulse "/clk" 3;
end;
pattern = 5;
end;
force "PI" "0010" 1;
measure "PO" "11101" 2;
pulse "/clk" 3;
end;
pattern = 6;
end;
force "PI" "0000" 1;
measure "PO" "10010" 2;
pulse "/clk" 3;
end;
pattern = 7;
end;
force "PI" "0010" 1;
measure "PO" "11111" 2;
pulse "/clk" 3;
end;
pattern = 8;
end;
force "PI" "0010" 1;
measure "PO" "11011" 2;
pulse "/clk" 3;
end;
end;
SCAN_CELLS =
scan_group "grp1" =
scan_chain "chain1" =
scan_cell = 0 MASTER FFFF "/reg_q_2" "" "SI" "Q";

end;
end;
end;
Fault Run Statistics
Statistics Report
Stuck-at Faults
--------------------------------------
(total)
---------------------- --------------
FU (full) 120
-------------------- --------------
UU (unused) 4 ( 3.33%)
--------------------------------------
Coverage
--------------------
--------------------------------------
#test_patterns 9
CPU_time (secs) 0.3
Good Run
------------------------------------------------------------------------
// Simulation performed for #gates = 34 #faults = 0
// system mode = good machine simulation pattern source = 9 external patterns

// ------------------------------------------------------------------------
// #patterns test #faults #faults # eff. # test process
// simulated coverage in list detected patterns patterns CPU time
Good Report Statistics
Statistics Report
Stuck-at Faults
--------------------------------------
(total)
---------------------- --------------
FU (full) 120
-------------------- --------------
UU (unused) 4 ( 3.33%)
--------------------------------------
Coverage
--------------------
--------------------------------------
#test_patterns 9
CPU_time (secs) 0.3

VLSI TEST AND TESTABILITY DFT ADVISOR REPORT

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VLSI TEST AND TESTABILITY

DFT ADVISOR REPORT

Siddhi Karadkhedkar (2017H1230067H)

Cell: mod_12ctr View: INTERFACE Library: work

Total accumulated area :

// Verilog description for cell mod_12ctr,

module mod_12ctr ( clk, reset, q ) ;

DFT Scan Identification

* DESC: Generated by DFTAdvisor at Thu Nov 22 06:24:06 2018

module mod_12ctr ( clk , reset , q , scan_in1 , scan_out1 , scan_en );

input clk , reset , scan_in1 , scan_en ;

wire [1:0] \$dummy ;

.Q ( q[0] ) , .QB ( \$dummy [0] ));

nor02 ix61 (.A0 ( q[0] ) , .A1 ( nx101 ) , .Y ( nx60 ));

.Q ( q[2] ) , .QB ( nx115 ));

and02 ix17 (.A0 ( q[1] ) , .A1 ( q[0] ) , .Y ( nx100 ));

( q[1] ) , .QB ( \$dummy [1] ));

nor02 ix122 (.A0 ( q[0] ) , .A1 ( q[1] ) , .Y ( nx121 ));

assign scan_out1 = q[2] ;

// Begin scan cell distribution process...

// Chain allocation per clock/edge domain:

// domain[0]: #cells:4, #chains:1

report statistics (DFT)

Total number of sequential instances = 4

Number of inserted scan chains = 1

Number of new pins inserted = 3

// Simulation performed for #gates = 34 #faults = 81

// system mode = ATPG pattern source = internal patterns

// simulated coverage in list detected patterns patterns CPU time

// begin random patterns: capture clock = /clk, observe point = MASTER

// 64 54.31% 53 28 3 3 0.00 sec

// 128 92.24% 9 44 4 7 0.00 sec

// 192 98.28% 2 7 1 8 0.00 sec

// 256 100.00% 0 2 1 9 0.00 sec

Test Proc File

// Generated by DFTAdvisor at Thu Nov 22 06:26:39 2018

set time scale 1.000000 ns ;

// cycle 1 starts at time 0

// cycle 1 starts at time 0

Fault Classes #faults

CPU_time (secs) 0.3

// Tessent FastScan 2015.4

// Created = Thu Nov 22 06:36:55 2018

// Test Coverage = 100.00%

// Total Faults = 120

// Simulation Mode = combinational, seq_depth = 0

// Fault Type = stuck

// Fault Mode = uncollapsed

// Pos_Det Credit = 50%

// /clk off-state = 0 type = shift-MASTER poflag = 0

declare input bus "PI" = "/clk", "/reset", "/scan_in1", "/scan_en";

declare output bus "PO" = "/q[3]", "/q[2]", "/q[1]", "/q[0]", "/scan_out1";

procedure shift "grp1_load_shift" =

force "/clk" 1 20;

force "/clk" 0 30;

procedure shift "grp1_unload_shift" =

measure_sco "chain1" 10;

force "/clk" 1 20;

force "/clk" 0 30;

procedure load "grp1_load" =

apply "grp1_load_shift" 4 40;

procedure unload "grp1_unload" =