Spring 2001 EE 8223 − Analog IC Design Page 17

MOSFET Threshold Voltage

What affects the threshold voltage? ⇒ substrate doping, oxide thickness,

source-to-substrate voltage bias, gate material, and surface charge density

When VGS > VTHN (nMOSFET), the semiconductor/oxide interface is

inverted, i.e., the inversion layer is formed. The associated depletion region
(beneath the inversion layer) thickness is described by

2ε si φ s − φ F kT N A
Xd = ; where φ F = − ln .
qN A q ni

The charge attracted under the MOS gate is described by

Qb' = qN A X d = 2ε si qN A φ s − φ F [C/m2]

In accumulation mode, φs = φF ⇒ Qb′ = 0.

When increasing VGS (positively) results in φs = 0, the semiconductor surface

at the oxide interface becomes depleted.

Continuing to increase VGS till φs =− φF results in the formation of the

inversion channel.

Note that the value of VGS when φs =− φF is VTHN. In this situation the
negative charge in the depletion region is described by

Qb' = qN A X d = 2ε si qN A − 2φ F + VSB [C/m2]

Between strong inversion and depletion, φs changed a total of 2φF.

Spring 2001 EE 8223 − Analog IC Design Page 18

Threshold voltage expression:

VTHN = VTHN 0 + γ ( 2φ F + VSB − 2φ F )

where

Q ' − Qss
'
Q'
VTHN 0 = −φ ms − 2φ F + b 0 = VFB − 2φ F + b0
' '
C ox C ox
and
2qε si N A
γ =
'
C ox

The value of φms is obtained by adding the contact potentials:

φ ms = (φG − φ ox ) + (φ ox − φ F ) = φG − φ F

Note that a voltage equal to VFB must be applied at the gate for φs = φF.
Spring 2001 EE 8223 − Analog IC Design Page 19

MOSFET Operation

For strong inversion linear (nonsaturation) operation, see the gradual-

channel approximation derived in Section 5.3.1 of your text.

In the strong inversion linear region:

W  2 
V DS
I D n = KPn  GS
(V − V )V
THN DS −  for VGS ≥ VTHN and VDS ≤ (VGS−VTHN)
L  2 

W 2 
VSD
I D p = KPp (VSG − VTHP )VSD −  for VSG ≥ |VTHP| and VSD ≤ (VSG−|VTHP|)
L  2 

In the strong inversion (SI) saturation region:

• For VDS = VGS – VTHN, the inversion charge at the drain-channel

junction is zero (QI′(y=L) ⇒ 0), i.e., the channel becomes pinched
off.

• Substituting VDS,sat. (=VGS −VTHN) for VDS in the linear-mode

equation provides

IDn =
KPn W
2 L
[
(VGS − VTHN ) 2 ] for VGS ≥ VTHN and VDS ≥ (VGS−VTHN)

• According to first-order theory, ID will not further increase for VDS

> VGS − VTHN (not true!).
Spring 2001 EE 8223 − Analog IC Design Page 20

• Why does the drain actually increase with VDS > VDS,sat.? Consider
the electrical gate of the MOSFET in SI saturation,

Lelec = Ldrawn − X dl

Then I Dn =
KPn W
2 Lelec
[
(VGS − VTHN ) 2 ]
Channel length modulation (CLM) occurs due to the increase
depletion layer width as VDS increases

∂I D n KPn W dL  1 dX dl 
=− (VGS − VTHN ) 2 ⋅ elec = I Dn ⋅   = I Dn ⋅ λc
∂V DS 2 L2 dV DS  Lelec dV DS 
elec

Typical values for λc range from approximately 0.1 V-1 (short

channel devices) to 0.01 (long channel devices).

Including CLM in our first-order drain current equation,

I Dn =
KPn W
2 L
[
(VGS − VTHN ) 2 1 + λc (V DS − V DS ,sat ) ]

• For minimum gate length devices, max VDS is limited by punch-

through when the drain-substrate depletion region extends from
drain to source. This is BAD! The resultant high current can
destroy the device.

• For long channel devices, max VDS is limited by the drain

implant/substrate diode.

• Warning! The above analysis neglects mobility reduction with

increasing VDS.
Spring 2001 EE 8223 − Analog IC Design Page 21

• Also, for large values of VDS, saturation will appear to occur for
values of VDS below VDS,sat due to the fact that QI′(y) is actually a
function of VDS (i.e., it is not constant). This is also the result of
velocity saturation in short channel devices. Velocity saturation
causes VDS,sat and IDS,sat to decrease.

Note that the MOSFET has 3 different levels of inversion: weak, moderate,
and strong. Within each level of inversion, the MOSFET can be saturated or
non-saturated. Hence, the MOSFET 6 different modes of operation.
Spring 2001 EE 8223 − Analog IC Design Page 22

MOSFET Modeling

Review model parameters and their relationship to theory.

MOSFET Layout

Layout example (with schematic):