A simplified topology of voltage-tolerant Control signals Vφ1 and Vφ2 are represented in Fig.

2 beside their
switches for implantable functional electrical voltage-shifted versions Vφ11 , Vφ13 and Vφ21 , Vφ22 , Vφ23 , respectively.
stimulation The voltage shifters also generate the logic complements of these signals:
0 ,V0 ,V0 0 0 0
Vφ11 φ12 φ13 and Vφ21 , Vφ22 , and Vφ23 .
C.R.Rodrigues, R.S.Silveira, A.R.Plantes Neto, and C.A.Prior

In this letter we propose a minimum topology for voltage tolerant

switches which are able to withstand three times the voltage rating
of each transistor by using only five devices: three cascoded in the
stimulation current path and two as auxiliary switches. The proposed
topology achieves reduced leakage through auxiliary control circuits
while employing less than half the number of transistors from similar
topologies.

Introduction: One of the major challenges for today’s biomedical Fig2.pdf

engineering research is the development of wireless implantable neural
interfaces. The functional electric stimulation (FES) a key function for
those systems and meets application in diverse types of prosthesis (
cochlear[1], retina [2], limbs[3],[4], and treatments like the Deep Brain
Stimulation[5]. Most of FES front-ends rely on the availability of high
voltage transistors which limits the range of choice for fabrication
technologies. An alternative approach is using circuit topology solutions
for implementing high-voltage switches with transistors from CMOS
baseline process. To preserve the circuit lifetime, voltage ratings of
transistors must be respected in order to keep electric field strengths
under below critical values in order to avoid lifetime degradation
machanisms namely [6]: oxide breakdown, hot-carrier degradation, and Fig. 2. Control signal Vφ1 and its voltage shifted copies Vφ12 , and Vφ13 .
junction breakdown. The main topological strategy for voltage limiting
is cascoding a sufficient number of devices thus dividing overvoltages Circuits of N1 and P2 are detailed in the Fig.3. Each switch comprises
among their terminals. An auxiliary biasing circuit is included in order three main, and two auxiliary transistors. Main transistors MN1-NM3 (or
assure the correct distribution of voltage drops among devices. We MP1-MP3) are sized to sink (source) the maximum stimulation current
propose a minimum topology for voltage tolerant switches by using just from(to) the electrodes (Ve+ and Ve-) with few millivolts of voltage
one transistor for each node of the main current path. The operation is drop. The auxiliary transistors PA1-PA2 (or NA1-NA2) have the role of
demonstrated at simulation level with 3.3V transistors from UMC130nm clamping drain-source voltages of main transistors to Vdd when switches
process. are in the high-impedance state.
Regarding the N-switch, schematically shown in Fig.3a, if Vφ1 =Vφ11
is initially low (0V), the gate to source voltage of MN1 is set to
zero which drives the transistor into the cuttof condition [8]. At the
Proposed circuit: Proposed switches are employed to implemement the
same instant, shifted copies of Vφ11 assume also logic level low, i.e.
H-Bridge stimulator shown in Fig.1. A charge-sharing digital-to-analog
Vφ12 =VDD and Vφ13 =2VDD. Thus, to ensure that NM2 and NM3 are
converter (DAC), which is not discussed in this letter, was chosen to set
also in cuttof condition, Vn1 and Vn2 must respectively be set to VDD
the amplitude of stimulation current because of the feedback technique
and 2VDD, defining VGS=0 for both transistors. As the voltages at
employed to keep the stimulation charge balancing [?]. The stimulator
the itermediate nodes of series connected high-impedance elements are
consists of two N-switches (N1 and N2) and two P-switches (P1 and P2).
poorly defined [?], auxiliary transistors PA1 and PA2 are connected in
As the main transistors in the switches require their gates to be driven
such way vp1 and vp2 are set to VDD and 2VDD respectivelly, only
with respect to different reference voltages (i.e., gnd, Vdd, 2.Vdd, and
when N-switch is open. An additional condition for driving auxiliary
3.Vdd), voltage-shifters are employed for shifting control signals.
transistors is that voltages between any of their terminals must be kept
below |VDD|. For PA1, this requirement can be met by setting the source
terminal to Vφ1 0 as this is the voltage vp1 is expected to track. The

V DD 2.VDD 3.VDD VDD-H switching action of PA1 is accomplished by connecting its gate to VDD.
This sets VGS=Vφ11 0 -VDD thus turning PA1 on for V
φ11 =0, and off
Vf23 Vf23 P2 for Vφ11 =VDD as expected. It can be also observed that, as the drain
Vf23 P1 Vf13 to source voltage on PA1 is allways close to zero, reducing leakage
Vf22 Switch Switch Vf12
Level Vf22 currents are reduced in this transistor. Is is not possible to adopt the same
Vf21 Vf11
Shifter 1 Vf22 strategy for PA2, because Vp2 is expected to swing from 0 to 2VDD. The
Vf21 signal with the closest available behavior to connect vp2 is Vφ12 0 . It has

Vf21 Vf13 N1 N1 Vf23 coinciding low and high states, but with its low state is 2VDD instead of
Excitable
Vf2 Vf12 Switch Switch Vf22 0. In order to turn PA2 on when Vφ120 =2VDD, it is required to set its gate
Tissue
Vf11 Vf2 voltage to VDD. The same condition is needed for keeping PA2 off when
V DD 2.VDD 3.VDD 0 =2VDD. Therefore, its gate is connected to VDD, as shown in ig.3a.
Vφ12
V DD The same rationale was addopted to design the P-switch shown in 3b, but
Vf13
changing the reference from 0 to 3VDD and negating the logic signals
Vf13 M SNK
DAC employed.
Level Vf12
Shifter 1 Vf12 I stim
Vf11
Amplitude Simulation results: The stimulator bridge was simulated with included
Vf11 post-layout extracted parameters. The resulting voltages and currents
Vf2 across the transistors in N and P-switches are shown in 4.
Example of citation [?]
Example of equation
Fig. 1. Proposed HV-tolerant stimulator.
 
1
Q= N+ e (1)
2

ELECTRONICS LETTERS 12th December 2011 Vol. 00 No. 00

 P-switch N-switch
3VDD V e+ Vf12
VDD
Vf23 Vf23 Vf13 MN3
MP 3 2VDD
vn 2 PA2
Vf22 NA 2 Vf12 vp 2 MN2
MP 2 PA1
vn 1 vp 1
Vf21 Vf11 MN1
MP 1 NA 1 Vf11
V e+ Vf22

Fig. 3. Schematics of N-switches and P-switches.

Fig4.pdf

Fig. 4 Voltages and currents though the switches: a) voltages across the
main transitors in the N-switch, p-switch and, c) stimulation current for an
electrode with Ze = 10kΩ.

Another equation: Table 1: Table caption (k = 0.05, v = 3, c1 = 1.5, c2 = 4.5)

n a2n rk (1)
αk ĉ†αkσ ĉαkσ + U dˆ†↑ dˆ↑ dˆ†↓ dˆ↓
X
H2C = 0 3.602576748428 1.493719547999
αkσ
1 1.384791111989 0.108928436101
2 0.108600438794 0.000327997399
3 0.000275794597 0.000052202814
[tα ĉ†αkσ dˆσ + h.c.]
X X
+ d dˆ†σ dˆσ + (2) 4 0.000027616892 0.000024585922
σ αkσ 5 0.000018178621 0.000006407300
Symbols: α , d , tα another eq:
X t∗α tβ
αk ĉ†αkσ ĉαkσ +
X
H2K = ĉ†ασ (r = 0)σστ
a
ĉβτ (r = 0)S a E-mail: cesar@ieee.org
U
αkσ αβστ | {z }
Jαβ
References
(3)
Example of table (comment it if not using): 1 Clark G. M. (2003). Cochlear Implants: Fundamentals and Applications.
New York, NY: Springer-Verlag.
2 Walter, P.: ‘A Fully Intraocular Approach for a Bi-Directional Retinal
Prosthesis’ (Springer International Publishing, New York, NY, 2017)
Conclusion: 3 Oddo, C. M. et al.: ‘Intraneural stimulation elicits discrimination of
textural features by artificial fingertip in intact and amputee humans’,
Acknowledgment: This work has been supported by CNPq, grant eLife, 2016, 5, pp. 1-27.
487183/2013-4 4 Riener, R.: ‘The Cybathlon promotes the development of assistive
technology for people with physical disabilities’, Journal of
C.R.Rodrigues, R.S.Silveira. (UFSM, Santa Maria, Brazil) NeuroEngineering and Rehabilitation, 2016, 2016;pp.13-49.

2
5 Gong, C-SA, et al.: ‘A Programmable High-Voltage Compliance Neural
Stimulator for Deep Brain Stimulation in Vivo’, Sensors, 2015, 15(6),
pp.12700-19. doi:10.3390/s150612700.
6 Takahash, M. et al.: ‘3.3V-5V compatible I/O circuit without thick
gate oxide’, 1992 Proceedings of the IEEE Custom Integrated
Circuits Conference, Boston, MA, USA, 1992, pp. 23.3.1-23.3.4. doi:
10.1109/CICC.1992.591341
7 Coleman, P.: ‘1/N expansion for the Kondo lattice’, Phys. Rev. B, 1983,
28, pp. 5255-5262
8 Ludwig, I. and Ludwig A. W. W.: ‘Kondo effect induced by a magnetic
field’, Phys. Rev. B, 2001, 64, p. 045328