By-Vishakha Bhale, PhD

MOS TRANSISTOR
CONTENTS

MOS Transistor (06 Hours)

MOS Structure and operation
MOSFET Structure and operations
MOSFET Current- Voltage Characteristics
Channel Length Modulation
Substrate Bias Effect
MOSFET Capacitances
MOSFET Model.
INTRODUCTION

BJT vs MOS FET

MOS STRUCTURE

❑ The two terminal MOS structure consists of three

layers:
1. Metal (aluminum) gate electrode
2. Insulating Oxide (SiO2) layer
3. P-type bulk Semiconductor (Si), called as substrate.

❑ MOS structure forms a capacitor

(with the gate & substrate acting as two terminals/plates &
oxide layer as dielectric material in between)
❑
 Typically
between
10 nm to
50 nm

(Acceptor ion concentration)

Then equilibrium electron & hole
Concentration in p-type substrate
are approx. given by :
ENERGY BAND DIAGRAM OF P-TYPE SUBSTRATE
• The band gap of CB & VB
for Si is approximately
1.12 eV (1eV=1.6×10-19 C)
• The location of the
equilibrium Fermi level
(EF)Within the band gap
is determined by the
doping Type & doping
concentration in Si
substrate

1 Electron affinity :
2 Fermi potential : It is the function of temperature &
doping & is the difference between the intrinsic Fermi
level Ei & the Fermi level EF

➢ For p-type & n-type semi-conductors, Fermi potential

can be :

• Positive Fermi potential for n-type & negative Fermi potential for p-type material
3 Work function: The energy required for an electron to
move from Fermi level into the free space is called work
function (qφs) & is given by:
 ENERGY BAND DIAGRAM OF COMBINED MOS
SYSTEM
• Three components of ideal MOS system are brought into physical contact.
• Fermi levels of all three materials must line up, as they form MOS capacitor.
• Because of work function difference between metal & semiconductor, voltage
drop occurs across MOS system.
• Part of this drop occurs across the insulating oxide layer.
• Rest of the voltage drop occurs at silicon surface next to silicon-oxide
interface, forcing energy bands of silicon to bend in this region.
• (qØm- qØs) is defined as built-in
potential difference (work function
difference) across MOS system
• If a voltage corresponding to this
is potential difference is applied
externally between gate &
substrate bending of energy bands
near surface can be compensated
i.e. the energy bands becomes
“FLAT” .
• Thus, the voltage defined by
VFB= Øm- Øs is called flat-band
voltage
If voltage corresponding to this potential Metal M
difference is applied externally between G &
B, bending of energy bands near surface
can be compensated i.e. Energy band O
becomes flat & volt is called as Flat Band
Volt.

=ØM-ØS

Fig: Energy Band Diagram of combined MOS system

MOS STRUCTURE UNDER EXTERNAL BIAS
➢ Discuss electrical behaviour of MOS structure under
externally applied bias voltages.
➢ Assume that the substrate volt is set as zero, VB=0, &
let the gate voltage be the controlling parameter.
➢ Depending upon the polarity & magnitude of VG, three
different operating regions can be observed for MOS
system :
Accumulation, Depletion & Inversion
 (CASE 1)
The oxide electric field (EOX)
here is directed towards the
• The majority carrier gate terminal
concentration near Metal
the surface becomes
larger than equilibrium
hole concentration in
the substrate, Hence
this condition is called
carrier accumulation
on the surface
➢ Negative surface
potential also causes
energy bands to bend
upwards near the surface

➢ While the hole density Decrease in electron

near the surface concentration

increases as a result of
applied negative gate Band bending towards the
surface
bias, the electron
concentration decreases
as negatively charged
electrons are pushed
deeper into the
substrate.
 (CASE 2)

➢ VG is small +ve volt & Metal

VB is 0, the oxide electric
field will be directed
downwards the substrate.
➢ The majority carriers Xd
i.e. holes in substrate Xd : depth of depletion region
will be repelled back into
the substrate as a
result of positive gate
bias & these holes will
leave negatively charged
fixed acceptor ions
behind. Thus a depletion
region is created near ➢ The positive surface potential Causes
the surface. energy bands to bend downwards near
➢ Under this bias the surface
condition the region near
semiconductor-oxide
interface is nearly
devoid of all mobile
carriers.
➢ The amount of this depletion region
charge plays very important role in the
analysis of threshold voltage
 ➢ As a result of
further increase
in surface
potential the
(CASE 3) energy band will
further bend
N-type region created near downwards
the surface by positive gate ➢ Eventually mid-
potential is called inversion gap energy level
layer & this condition is
Ei becomes
called surface inversion
smaller than
This thin inversion layer will Fermi level EFP on
be utilized for conducting the surface which
current between two means surface
terminals of MOS semiconductor in
transistor. this region
becomes n-type.

➢ Once the
surface is
Surface inverted any
further increase
inversion in gate volt leads
➢ Xd chieved at
surface to increase of
inversion is mobile electron
the maximum concentration on
depletion the surface but
width Xdm, not to an increase
which remains of depletion depth
constant for
higher gate
voltage.
▪ Practically, the surface is said to be inverted when
density of mobile electrons on the surface becomes
equal to the density of holes in bulk p-type substrate.
▪ This condition requires that the surface potential (Øs)
has the same magnitude, but reverse polarity, as the bulk
Fermi potential (ØF)
i.e. Øs = -ØF …..condition for surface inversion
▪ The creation of a conducting surface inversion layer
through externally applied gate bias is an essential
phenomenon for current conduction in MOS transistor.
NUMERICAL
Consider the MOS structure that consists
of p-type doped silicon substrate, a silicon
dioxide layer, and Al metal gate. The
equilibrium fermi potential of doped silicon
substrate is given as qØfp=0.2eV. Given
electron affinity for Si is 4.15eV & work
function for Al is 4.1eV.Calculate the built
in potential difference across MOS system.
• The MOS capacitor is not a widely used device in itself. However, it is part of the MOS
transistor which is by far the most widely used semiconductor device.
The typical capacitance-voltage characteristics of a MOS capacitor with n-type body is given
below,

Capacitance vs. Gate Voltage (CV) diagram of a MOS Capacitor.

The flatband voltage (Vfb) separates the Accumulation region from the Depletion region.
The threshold voltage (Vth) separates the depletion region from the inversion region.
WHAT IS MOSFET (MISFET)
 MOSFETs are tri-terminal (four-terminal), uni-polar,
voltage-controlled, high input impedance devices which
form an integral part of vast variety of electronic
circuits.
CLASSIFICATION OF MOS FET
➢ A MOS transistor which has no conducting channel
region at zero gate bias is called Enhancement type
(mode) MOSFET
➢ If a conducting channel already exists at zero gate
bias, the device is called Depletion type (mode)
MOSFET
N-Channel MOSFET: has P-type
substrate, N+ source & drain regions,
channel to be formed on the surface is
n-type
P-Channel MOSFET: has N-type
substrate, P+ source & drain regions,
channel to be formed on the surface is
p-type.
Various symbols of MOSFET & its input Characteristics
 ❖ The abbreviations used
for the device terminals are: G for gate, D for drain
➢ Mid section
S for source & B for substrate or body.
of the ❑ All the

STRUCTURE OF MOS TRANSISTOR

device terminal
structure can voltages
easily be of the
Recognized as device are
a MOS defined
structure wrt source
➢ It is a
terminal
symmetric
Device where Eg: Vgs,
drain & source Vds, Vbs
are etc
interchangeable
terminals of the
device.
➢ The two n+
regions are
current
conducting
regions of
the device.

source
gate: metal or heavily doped poly-Si
S
body G drain
B D
metal
n+ oxide
p n+

L W
MOSFET OPERATION
❖ The simple operating principle of this device is “ To
control the current conduction between the source and
drain, using electric field generated by the gate voltage
(Vgs) as a control variable”
❖ The current flow is also controlled by drain-to-source
voltage (Vds) & substrate voltage (Vbs)
❖ Therefore the current can be considered as a function
of these external terminal voltages
i.e. Ids (drain-to-source current) = f(Vgs, Vds, Vbs)
❖ In order to start the current Id to flow first we need
to form a conducting channel between drain & source
terminals.
➢ The simplest bias condition that can be applied to n-channel enhancement
MOSFET is shown in Figure.
❑ The source, substrate & drain all
terminals are grounded.
❑ A small negative gate-to-source
voltage is applied to the gate in
order to create the conducting
channel underneath the gate.
❑ For small gate voltage levels,
majority carriers (holes) are
repelled back into the substrate &
the surface of substrate is
depleted.
❑ Since the surface is devoid of any
mobile carriers, current conduction
between the source & drain is not
possible.
❑
❑ Now gate-to-source voltage is further increased.
❑ As soon as the surface potential (φs) in the channel region reaches (–φFP)
surface inversion will be established & a conducting n-type layer will form
between the source & drain diffusion regions as shown in Figure 2
❑ This channel now provides an electrical connection between two n+ regions &
it allows current flow as long as there is a potential difference between the
source & the drain terminal voltages as seen in Figure 3
❑ The bias conditions for onset of surface inversion & for creation of
conducting channel are therefore very significant for MOSFET operation.
❑ The value of this gate-to-source voltage VGS needed for surface inversion
to create conducting channel is called threshold voltage (VT0)

Fig 3 Fig 2
❑ Any gate-to-source voltage (VGS) smaller than VT0 is not sufficient
to establish an inversion layer; thus, the MOSFET can conduct no
current between its source & drain terminals unless VGS > VT0
❑ For gate-to-source voltage larger than threshold voltage, a large
number of minority carriers i.e. electrons for n-channel device are
attracted to the surface, which ultimately contributes to the
channel current conduction.
❑ Also note that increasing the gate-to-source voltage above & beyond
threshold voltage will not affect the surface potential & the
depletion region depth.
VARIOUS REGIONS OF OPERATION OF MOSFET
❑ In general, any MOSFET is seen to exhibit three operating regions viz.,

Cut-Off Region.
Ohmic or Linear Region.
Saturation Region.

❑ Cut-Off Region

Cut-off region is a region in which the MOSFET will be OFF as there will be no current flow through
it. In this region, MOSFET behaves like an open switch and is thus used when they are required to
function as electronic switches i.e. OFF SWITCH.

❑ Ohmic or Linear Region

Ohmic or linear region is a region where in the current IDS increases with an increase in the value of
VDS. When MOSFETs are made to operate in this region, they can be used AS AMPLIFIERS.

❑ Saturation Region

In saturation region, the MOSFETs have their IDS constant inspite of an increase in VDS and occurs
once VDS exceeds the value of pinch-off voltage VP. Under this condition, the device will act like a
closed switch through which a saturated value of IDS flows. As a result, this operating region is
chosen whenever MOSFETs are required to perform switching operations i.e. ON SWITCH.
 V-I CHARACTERISTICS OF NMOS

I DS
VDS Linear OR

VGS

❖ Figure 1a shows the transfer characteristics (drain-to-source current IDS versus gate-to-source voltage VGS) of
n-channel Enhancement-type MOSFETs. From this, it is evident that the current through the device will be zero
until the VGS exceeds the value of threshold voltage VT. This is because under this state, the device will be void
of channel which will be connecting the drain and the source terminals.
❖ Under this condition, even an increase in VDS will result in no current flow as indicated by the corresponding
output characteristics (IDS versus VDS) shown by Figure 1b. As a result this state represents nothing but the cut-
off region of MOSFET’s operation.
❖ Next, once VGS crosses VT, the current through the device increases with an increase in IDS initially (Ohmic
region) and then saturates to a value as determined by the VGS (saturation region of operation) i.e. as VGS
increases, even the saturation current flowing through the device also increases.
❖ This is evident by Figure 1b where IDSS2 is greater than IDSS1 as VGS2 > VGS1, IDSS3 is greater than IDSS2 as VGS3>VGS2
so on and so forth. Further, Figure 1b also shows the locus of pinch-off voltage (black discontinuous curve),
from which VP is seen to increase with an increase in VGS.
❑ Figure 2a shows the transfer characteristics of p-type enhancement MOSFETs from which it is evident that IDS
remains zero (cutoff state) untill VGS becomes equal to -VT. This is because, only then the channel will be
formed to connect the drain terminal of the device with its source terminal. After this, the IDS is seen to
increase in reverse direction (meaning an increase in ISD, signifying an increase in the device current which will
flow from source to drain) with the decrease in the value of VDS. This means that the device is functioning in its
ohmic region wherein the current through the device increases with an increase in the applied voltage (which will
be VSD).

❑ However as VDS becomes equal to –VP, the device enters into saturation during which a saturated amount of
current (IDSS) flows through the device, as decided by the value of VGS. Further it is to be noted that the value
of saturation current flowing through the device is seen to increase as the VGS becomes more and more negative
i.e. saturation current for VGS3 is greater than that for VGS2 and that in the case of VGS4 is much greater than
both of them as VGS3 is more negative than VGS2 while VGS4 is much more negative when compared to either of
them (Figure 2b). In addition, from the locus of the pinch-off voltage it is also clear that as VGS becomes more
and more negative,even the negativity of VP also increases.
❑ The transfer characteristics of n-channel depletion MOSFET shown by Figure 3a indicate that the device has a
current flowing through it even when VGS is 0V. This indicates that these devices conduct even when the gate
terminal is left unbiased, which is further emphasized by the VGS0 curve of Figure 3b. Under this condition,
the current through the MOSFET is seen to increase with an increase in the value of VDS (Ohmic region) untill VDS
becomes equal to pinch-off voltage VP. After this, IDS will get saturated to a particular level IDSS (saturation
region of operation) which increases with an increase in VGS i.e. IDSS3 > IDSS2 > IDSS1, as VGS3 > VGS2 > VGS1.
Further, the locus of the pinch-off voltage also shows that VP increases with an increase in VGS.

❑ However it is to be noted that, if one needs to operate these devices in cut-off state, then it is required to
make VGS negative and once it becomes equal to -VT, the conduction through the device stops (IDS = 0) as it gets
deprived of its n-type channel (Figure 3a).

❑
❑ The transfer characteristics of p-channel depletion mode MOSFETs (Figure 4a) show that these devices will be
normally ON, and thus conduct even in the absence of VGS. This is because they are characterized by the presence
of a channel in their default state due to which they have non-zero IDS for VGS = 0V, as indicated by the VGS0 curve
of Figure 4b. Although the value of such a current increases with an increase in VDS initially (ohmic region of operation),
it is seen to saturate once the VDS exceeds VP (saturation region of operation).The value of this saturation current is
determined by the VGS, and is seen to increase in negative direction as VGS becomes more and more negative.
For example, the saturation current for VGS3 is greater than that for VGS2 which is however greater when compared to
that for VGS1.This is because VGS2 is more negative when compared to VGS1, and VGS3 is much more negative when
compared to either of them. Next, one can also note from the locus of pinch-off point that even VP starts
to become more and more negative as the negativity associated with the VGS increases.
❑ Lastly, it is evident from Figure 4a that in order to switch these devices OFF, one needs to increase V GS such
that it becomes equal to or greater than that of the threshold voltage VT. This is because, when done so, these
devices will be deprived of their p-type channel, which further drives the MOSFETs into their cut-off region of
operation.
 The explanation provided above can be summarized in the form of a following table

Kind of MOSFET Region of Operation

Cut-Off Ohmic/Linear Saturation

n-channel VGS > VT and VDS <

VGS < VT VGS > VT and VDS > VP
Enhancement-type VP

p-channel VGS < -V T and VDS > -

VGS > -VT VGS < -VT and VDS < -VP
Enhancement-type VP

n-channel Depletion- VGS > -V T and VDS <

VGS < -VT VGS > -VT and VDS > VP
type VP

p-channel Depletion- VGS < VT and VDS > -

VGS > VT VGS < VT and VDS < -VP
type VP
THE THRESHOLD VOLTAGE

❑
 MOSFET OPERATION: A QUALITATIVE VIEW
➢ When 0< VGS < VT0, the gate region
between drain & source is depleted
So no current flows from S to D… Cut-
off mode.
➢ When VGS > VT0, → surface inverted
→ n-type conducting channel forms
between S & D → which is capable of
carrying drain current.
➢ At VDS=0 , thermal equilibrium exists in
the inverted channel region & drain
current ID is equal to zero (Figure a)

➢ If small drain voltage VDS > 0 is applied, a drain

current proportional to VDS Will flow from source
to drain through the conducting channel.
➢ The inversion layer i.e. the channel forms the
conducting current path from source to drain.
➢ This operation mode is called linear mode
➢ Thus in linear region operation, the channel
region acts as a voltage controlled resistor.
➢ As drain volt increases, the inversion layer charge &
channel depth at the drain end start to decrease.
➢ Eventually, for VDS ≥ VDSsat, the inversion
charge at the drain is reduced to zero, which is
called the pinch-off point (Figure b) & condition is
known as Pinch-off condition…here mode is
saturation

➢ Channel length modulation in MOSFET is
similar to Early effect in BJT
➢ Beyond pinch-off point i.e. for VDS > VDSAT,
a depleted surface region forms adjacent to drain,
& this depletion region grows toward the source
with increasing drain voltages. This operation mode
of MOSFET is called saturation mode or
saturation region.
➢ For MOSFET mode operating in saturation
region the effective channel length reduced as
the inversion layer near the drain vanishes,
while channel length voltage remains essentially
constant & is equal to VDSAT (Figure c)
➢
GRADUAL CHANNEL APPROXIMATION

 For current flow analysis, consider cross-sectional view

of n-channel MOSFET operating in linear mode (Fig1)
 VS=VB=0 & VGS & VDS are external parameters
controlling drain (channel) current ID
 The VGS is set to be higher than VT0 (VGS>VT0) to
create conducting inversion layer between drain and
source.
 Define the coordinate system for this structure such that :
X-direction is ┴ to the surface, pointing down into substrate & Y-direction is parallel to the surface.
The y-coordinate origin (y=0) is at the source end of channel.

Structure hold two

electric fields, Ex &
Ey.
Where,
Electric field Ey is
dominant over Ex
Current equation in
linear region
Current equation in saturation region
 k=k’. (W/L)

Kn’

Kp’
CHANNEL LENGTH MODULATION
SUBSTRATE/BODY BIAS EFFECT

 Body bias is used to dynamically adjust the threshold voltage (Vt) of a

CMOS transistor.
 While CMOS transistors are usually thought of as having three terminal
devices, with terminals for the source, gate, and drain, it’s increasingly
common to have a fourth terminal connected to the body (substrate).
Because the voltage difference between the source voltage (Vs) and body
voltage (Vb) affects the Vt, the body can be thought of as a second gate
that helps determine how a transistor turns on and off.
 Under normal operation, an unbiased device has a matching Vs and Vb.
 Altering the voltage of the device’s bulk connection places the device into
either a forward or reverse body bias regime, changing the effective
Vt required to turn the device on.
 While Vs remains at nominal voltage, Vb will be either higher or lower
than Vs. This delta translates roughly to a difference in Vt.
 ➢ Depending on the polarity of the
body bias, this altered Vt gives
the device either a faster or
slower on time (tON) than normal
(Figure 1).
➢ A forward body bias lowers the
Vt required to turn the device on
(Vt(fb)), which allows the device
to turn on quickly for high
performance (tONFB), but the
device then has a higher leakage
current.
➢ Conversely, if the device is put
into a reverse body bias, it
raises the required Vt for the
device to turn on (Vt(rb)). This
increased Vt increases the time
it takes for the device to turn
on (tONRB), but also lowers the
leakage current, which is useful
from a power efficiency
standpoint.

Figure 1: Simplified display of how the body bias effect can alter the tON for a
PMOS transistor. Vs remains at nominal voltage, while Vb increases (reverse bias)
or decreases (forward bias).This produces a similar increase or decrease in tON,
respectively.
MOSFET CAPACITANCES
▪ The nature & amount of parasitic capacitances
associated with MOS transistor.

▪ The on-chip capacitances found in MOS circuits are

complicated functions of layout geometries &
manufacturing processes.

▪ Most of these capacitance are not Lumped but are

Distributed & their exact calculation would require
complex, three-dimensional nonlinear charge-voltage
models….high end simulation analysis eg. Monte Carlo
▪ Capacitances decides the SPEED of operation of the
design.
 Cross-sectional & top view (mask view) of typical n-
channel MOSFET.

 Uptil now we considered cross-sectional view of the

device, since we were primarily concerned about the flow
of carriers within the MOSFET.

 For parasitic device capacitances, look for top view of

MOSFET.
 Channel stop implant

LM is mask length of gate

L is actual length of gate
LD is the extent of both gate-source and gate-drain overlap
Thus, the channel length is : L= LM-2 LD
The purpose of this additional p+ region is to prevent formation of any
Unwanted (parasitic) channels between two neighboring n+ diffusion regions i.e to
ensure that the surface between two such regions cannot be inverted
Hence, p+ channel-stop implants act to electrically isolate neighboring devices on
same substrate.
 The device capacitances can be categorized into two
major groups:
1. Oxide related capacitances

2. Junction capacitances

(side wall and bottom plate capacitances) (assignment

for students)
OXIDE CAPACITANCES

 The gate electrode overlaps both the source

and drain regions at the edges.
 As a result of this structural arrangement TWO
Overlap capacitances arises.
1. CGD(overlap) & 2. CGS(overlap)
Assuming both the source and drain diffusion regions having the same width W,
overlap capacitances can be found as:

Capacitance/unit area
Anything that contains separated mobile charges forms a capacitor
GATE CAPACITANCE
 Capacitance-voltage or CV plotting, is a common
electrical technique for investigating charge phenomena
in MOS structures and transistors. In this article, we’ll
review some of the characteristics of the CV plot, and
how it is used to identify and characterize yield and
process integration problems.
Figure 1 shows a high and low-frequency capacitance-voltage plot of an ideal
MOS structure. The high frequency curve is denoted by the solid line, while
the low frequency curve is denoted by the dashed line. The capacitance is high
when the structure is in accumulation, decreases toward the flatband condition
at zero volts applied to the structure, and decreases further toward Cmin, the
steady state high frequency condition. In the low frequency condition, the
capacitance begins to rise again at a voltage called the match point. As the
voltage increases, the capacitance increases to a level similar to that in
accumulation. This is sometimes referred to as a quasi-static CV measurement,
and is measured using the voltage ramp method. In the voltage ramp method,
the voltage is ramped very slowly at a given rate, typically less than 50 mV/sec.
The measured displacement current is proportional to the capacitance. The
frequency is considered to be low when the generation of electron-hole pairs
keep up with the signal. When the frequency is high, only majority carriers can
follow the signal. At low frequencies, the charge exchange with the inversion
minority carriers is in step with the varying signal. The small signal response
dQ to dV appears at the surface (inversion) rather that at the depletion
boundary. As the inversion layer forms, the capacitance increases back to
Cmax ≈ Cox.
Figure 2 shows a high-frequency capacitance-voltage, or CV plot of an
ideal MOS structure.
High frequency measurements allow the user to hide the effects of
minority
carriers since minority carriers cannot react fast enough to follow the
signal.
The capacitance is high, approximately that of the ideal capacitance
across the oxide, when the voltage is negative.
When the voltage is negative, the MOS structure is in accumulation so
the surface hole concentration increases, raising the capacitance.
At flatband, the capacitance should be equal to the ideal capacitance
for the flatband condition.
As the voltage goes positive, the MOS structure goes into depletion
the surface electron concentration increases, but remains at a level
too low to offset the decrease in surface hole concentration.
In weak inversion, the surface electron hole concentration is higher
than the surface hole concentration, but the depletion width increases,
lowering the capacitance further.
In strong inversion, the surface electron concentration equals the
surface hole concentration at flatband, and the depletion width
reaches its maximum. The capacitance reaches its minimum at this
value as well.
This is also the threshold voltage point, where Ψs is approximately
equal to 2Φb.
The steady-state condition is reached when sufficient electrons are
supplied to the surface mechanisms like electron-hole pair generation.