Chapter 9 Metal-Semiconductor Contacts

Two kinds of metal-semiconductor contacts:

• metal on lightly doped silicon –

• rectifying Schottky diodes
• metal on heavily doped silicon –
• low-resistance ohmic contacts

Semiconductor Devices for Integrated Circuits (C. Hu) Slide 9-1

 9.1 Schottky Barriers
Energy Band Diagram of Schottky Contact
Depletion
Metal Neutral region
layer

qφBn
Ec
• Schottky barrier height, φB ,
Ef is a function of the metal
material.
Ev
• φB is the single most
Ec important parameter. The
sum of qφBn and qφBp is equal
Ef to Eg .
qφBp Ev

Semiconductor Devices for Integrated Circuits (C. Hu) Slide 9-2

 Schottky barrier heights for electrons and holes

Metal Mg Ti Cr W Mo Pd Au Pt
φ Bn (V) 0.4 0.5 0.61 0.67 0.68 0.77 0.8 0.9
φ Bp (V) 0.61 0.5 0.42 0.3
Work
Function 3.7 4.3 4.5 4.6 4.6 5.1 5.1 5.7
ψ m (V)

φBn + φBp ≈ 1.1 V

φBn increases with increasing metal work function

Semiconductor Devices for Integrated Circuits (C. Hu) Slide 9-3

 φBn Increases with Increasing Metal Work Function

Vacuum level, E0

χSi = 4.05 eV
qψ M Ideally,
qφBn= qψM – χSi
q φBn Ec

Ef

Ev

Semiconductor Devices for Integrated Circuits (C. Hu) Slide 9-4

 φBn is typically 0.4 to 0.9 V

• A high density of
Vacuum level, E0 energy states in the
bandgap at the metal-
χSi = 4.05 eV
semiconductor interface
qψ M
pins Ef to a range of
0.4 eV to 0.9 eV below
q φ Bn Ec Ec
+ −
Ef • Question: What is the
typical range of φBp?
Ev

Semiconductor Devices for Integrated Circuits (C. Hu) Slide 9-5

 Schottky barrier heights of metal silicide on Si

Silicide ErSi1.7 HfSi MoSi2 ZrSi2 TiSi2 CoSi2 WSi2 NiSi2 Pd2Si PtSi
φ Bn (V) 0.28 0.45 0.55 0.55 0.61 0.65 0.67 0.67 0.75 0.87
φ Bp (V) 0.55 0.49 0.45 0.45 0.43 0.43 0.35 0.23

Silicide-Si interfaces are more stable than metal-silicon

interfaces. After metal is deposited on Si, an annealing step is
applied to form a silicide-Si contact. The term metal-silicon
contact includes silicide-Si contacts.

Semiconductor Devices for Integrated Circuits (C. Hu) Slide 9-6

 Using CV Data to Determine φB

qφBn qφbi q φ bi = q φ Bn − ( E c − E f )
Ec
Nc
Ef = q φ Bn − kT ln
Nd
Ev 2ε s (φ bi + V )
W dep =
qN d
qφBn q(φbi + V) εs
C= A
qV W dep
Ec
Ef Question:
How should we plot the CV
Ev
data to extract φbi?

Semiconductor Devices for Integrated Circuits (C. Hu) Slide 9-7

 Using CV Data to Determine φB

1/C 2
1 2(φbi + V )
=
C 2
qN d ε s A2

V
− φbi
Once φbi is known, φΒ can be determined using
Nc
qφbi = qφ Bn − ( Ec − E f ) = qφ Bn − kT ln
Nd

Semiconductor Devices for Integrated Circuits (C. Hu) Slide 9-8

 9.2 Thermionic Emission Theory
vthx
-
q(φ B − V) Ec
q φB
N-type Efm qV Efn
V Metal Silicon

Ev

x
3/ 2
 2πmn kT 
n = N c e − q (φ B −V ) / kT = 2  2  e − q (φ B −V ) / kT
 h 
vth = 3kT / mn vthx = − 2kT / πmn
1 4πqmn k 2 2 − qφ B / kT qV / kT
J S →M = − qnvthx = 3
T e e
2 h
= J 0 e qV / kT , where J o ≈ 100e − qφ B / kT A/cm 2

Semiconductor Devices for Integrated Circuits (C. Hu) Slide 9-9

 9.3 Schottky Diode
IS → M IS→ M = Ι IM → S = − Ι0 IS → M = Ι eqV/kT
= −Ι 0 0 0
- - - - < qφ
B
qφB E − Ef = q φB qφB
qV Efn
Ef

(a) V = 0. IS → M = I M → S = Ι0 (b) Forward bias. Metal is positive wrt

Si. IS → M >> IM → S = Ι0

IM →S = −Ι0 IM → S ≈ 0
-
I
qφB
> qφ B
qV

EEfnfn V

Reverse bias Forward bias

(c) Reverse bias. Metal is negative wrt Si. (d) Schottky diode IV.

IS → M << IM → S = Ι0

Semiconductor Devices for Integrated Circuits (C. Hu) Slide 9-10

 9.3 Schottky Diode
IM → S = − Ι0 IS → M = Ι eqV/kT
0
- - < qφ
B
qφB
qV Efn
Ef

I 0 = AKT 2e − qφ B / kT
4πqmn k 2
K= 3
≈ 100 A/(cm 2
⋅ K 2
)
h
I = I S →M + I M →S = I 0e qV / kT − I 0 = I 0 (e qV / kT − 1)
Semiconductor Devices for Integrated Circuits (C. Hu) Slide 9-11
 9.4 Applications of Schottky Diodes
I I Schottky
Schottky diode
I = I 0 (e qV / kT − 1)
I 0 = AKT 2e −qφB / kT
φφBB PN junction
PN junction
diode

V
V

• I0 of a Schottky diode is 103 to 108 times larger than a PN

junction diode, depending on φB . A larger I0 means a smaller
forward drop V.
• A Schottky diode is the preferred rectifier in low voltage,
high current applications.
Semiconductor Devices for Integrated Circuits (C. Hu) Slide 9-12
 Switching Power Supply
PN Junction Schottky
rectifier Transformer rectifier
100kHz
110V/220V Hi-voltage Hi-voltage Lo-voltage 50A
DC MOSFET AC AC 1.8V DC
AC inverter
utility
power

feedback to modulate the pulse width to keep Vout = 1.8 V

Question: What sets the lower limit in a Schottky diode’s

forward drop?

Synchronous Rectifier: For an even lower forward drop,

replace the diode with a wide-W MOSFET which is not
bound by the tradeoff between diode V and I0 : I = I0eqV/kT

Semiconductor Devices for Integrated Circuits (C. Hu) Slide 9-13

 9.4 Applications of Schottky Diodes
There is no minority carrier injection at the Schottky
junction. Thus, the CMOS latch-up problem can be
eliminated by replacing the source/drain of the NFET with
Schottky junctions.

In addition, the Schottky S/D MOSFET would have shallow

junctions and low series resistance. So far, Schottky S/D
MOSFETs have lower performance.
silicide gate silicide
source drain No excess carrier storage.
What application may benefit
P-body from that?

Semiconductor Devices for Integrated Circuits (C. Hu) Slide 9-14

 GaAs MESFET

gate
source drain
metal
+ N-channel
N N+
GaAs
Semi-insulating substrate

The MESFET has similar IV characteristics as the MOSFET,

but does not require a gate oxide.
Question: What is the advantage of GaAs over Si?

Semiconductor Devices for Integrated Circuits (C. Hu) Slide 9-15

 9.5 Ohmic Contacts

Semiconductor Devices for Integrated Circuits (C. Hu) Slide 9-16

 SALICIDE (Self-Aligned Silicide) Source/Drain
contact metal dielectric spacer

G
gate
oxide
Rs Rd channel
S D

N+ source or drain
CoSi2 or TiSi2

After the spacer is formed, a Ti or Mo film is deposited. Annealing causes

the silicide to be formed over the source, drain, and gate. Unreacted metal
(over the spacer) is removed by wet etching.
Question:
• What is the purpose of siliciding the source/drain/gate?
• What is self-aligned to what?

Semiconductor Devices for Integrated Circuits (C. Hu) Slide 9-17

 9.5 Ohmic Contacts
Silicide N+ Si
2ε sφ Bn φBn – V
Wdep = φBn - -
qN d - - Ec , Ef Efm V
Ec , Ef

Tunneling
probability: Ev
Ev

− Hφ Bn Nd x x
P=e

H = 4π ε s mn / h = 5.4 × 10 9 mn / mo cm −3/2 V −1
1 − H (φ Bn −V ) /
≈ qN d vthx P = qN d kT / 2πmn e
Nd
J S →M
2
Semiconductor Devices for Integrated Circuits (C. Hu) Slide 9-18
 9.5 Ohmic Contacts

−1 Hφ Bn / N d
 dJ S → M  e Hφ Bn / Nd
Rc ≡   = ∝e Ω ⋅ cm 2
 dV  qvthx H N d

Semiconductor Devices for Integrated Circuits (C. Hu) Slide 9-19