1

EE 560 MOS INVERTERS: DYNAMIC

CHARACTERISTICS

Kenneth R. Laker, University of Pennsylvania

 VDD Cgd, Cgs, Cgb -> Oxide Caps 2

Cgsp Csbp Cdb, Csb -> Junction Caps

S Cint -> Inteconnect Cap
G B

✓ Cdbp
D
Vin Cgdp Vout
✓
Cgdn
✓ ✓
D Cdbn
G B
✓ ✓
Cint Cgb
S

Cgsn Csbn

✓ + C ✓ + C ✓ + C ✓ + C ✓ + C✓
Cload = Cgdn gdp dbn dbp int gb

Kenneth R. Laker, University of Pennsylvania

 VDD 3

G B
iC= iDp- iDn
D iDp
Vin Vout

iDn iC
D
G B
Cload
S

Cload = Cgdn + Cgdp + Cdbn + Cdbp + Cint + Cgb

Kenneth R. Laker, University of Pennsylvania
 Vin DELAY DEFINITIONS 4

VOH

VOL
t
τPHL= t1 - t0 τPLH = t3 - t2
Vout
VOH
V50% Avg Prop Delay
τ PHL + τ PLH
τP =
2
VOL
t0 t1 t t
t2 3
V50% = VOL +0.5 [VOH - VOL] = 0.5 [VOL +VOH]
Kenneth R. Laker, University of Pennsylvania
 OUTPUT VOLTAGE RISE & FALL TIMES 5

Vout τfall = tB - tA τrise = tD - tC

VOH
V90%

V10%
VOL
tA t
tB tC tD
V10% = VOL +0.1 [VOH - VOL]
V90% = VOL +0.9 [VOH - VOL]

Kenneth R. Laker, University of Pennsylvania

 CALCULATION OF DELAY TIMES 6

Vin
QUICK ESTIMATES: VOH

C load ∆ VHL C load (VOH − V50% )

τ =
PHL = VOL
t
I avg,HL I avg,HL τPHL= t1 - t0 τPLH = t3 - t2
Vout
C load ∆ VLH C load ( V50% − VOL ) VOH
τ P LH = = V50%
I avg,LH I avg,LH
VOL t
t0 t1 t2 t3
Iavg,HL -> approximate average Cload current during
high-to-low Vout transition
I avg,HL = [i C ( Vin = VOH , Vout = VOH ) + i C ( Vin = VOH , Vout = V50% )]
1
2
Iavg,LH -> approximate average Cload current during
low-to-high Vout transition
I avg,LH = [i C ( Vin = VOL , Vout = VOL ) + i C ( Vin = VOL , Vout = V50% )]
1
2
iC= iDp- iDn
Kenneth R. Laker, University of Pennsylvania
 7

MORE ACCURATE CALCULATION OF τPHL, τPLH:

VDD
S
G B

Vin D iDp iC= iDp- iDn

Vout
D iDn iC
G B dVout
Cload i C = C load = i Dp − i Dn
S dt

Kenneth R. Laker, University of Pennsylvania

1) Vin -RISING CASE: Vin 8
VOH
IC: Vout = VOH, Vin = VOL -> VOH = VDD
nMOS - ON SAT Vout > VDD -VT0n
p-MOS OFF LIN 0 < Vout < VDD -VT0n
VOL
iDp = 0 Vout t
iDn iC τPHL= t1 - t0
Vin D Vout
G B VOH = VDD
Cload
S VDD - VT0n
V50%
dVout
C load = − i Dn VOL
dt t
t0 t ’ t1
1
NOTE THAT:
nMOS SAT
|iDp| << |iDn| for all inverter types
nMOS LIN
Kenneth R. Laker, University of Pennsylvania
 9
VOH Vin t0 < t < t1’:
kn
i Dn = (Vin − VT 0 n ) 2
2
VOL
t kn dVout
Vout = (VOH − VT 0 n ) = − C load
2

VOH τPHL= t1 - t0 2 dt
VOH - VT0n
V50%
for VOH − VT 0 n < Vout ≤≥ VOH

VOL
t
t0 t1’ t1

Since iDn is INDEP of Vout

Kenneth R. Laker, University of Pennsylvania

 10
Vin
VOH t1’ < t < t1:

= [2(Vin − VT 0 n )Vout − Vout ]

kn 2
i Dn
VOL
2
t
[2(VOH − VT 0 n ) Vout − Vout ] = − C load
kn dVout
τPHL= t1 - t0 =
2
Vout
VOH 2 dt
VOH - VT0n
V50%
for Vout ≤ VOH − VT 0 n
VOL
t
t0 t1’ t1
t = t1 Vout =V50%  1
∫ dt = − C load ∫   dVout
t = t '1 Vout =VOH − VT 0 n  i Dn 

t = t1 
Vout = V50%
1 
∫ dt = −2 C load ∫  2  dVout
t = t '1 Vout =VOH −VT 0 n  k n [ 2(VOH − VT 0 n )Vout − Vout ]

2 C load 1  Vout  Vout = V50%

t1 − t = − '

k n 2(VOH − VT 0 n )  2(VOH − VT 0 n ) − Vout 

1 ln Vout =VOH −VT 0 n

Kenneth R. Laker, University of Pennsylvania

 2 C load 1  Vout  Vout = V50%
11

t1 − t = −
'

k n 2(VOH − VT 0 n )  2(VOH − VT 0 n ) − Vout 

1 ln Vout =VOH −VT 0 n

C load  2(VOH − VT 0 n ) − V50% 

= ln 
k n (VOH − VT 0 n )  V50% 

τPHL = t1 - t1’ + t1’- t0

2 Cload VT 0 n C load  2(VOH − VT 0 n ) − V50% 
τ PHL = 2 + ln  
k n (VOH − VT 0 n ) k n (VOH − VT 0 n )  V50% 

C load  2 VT 0 n  2(VOH − VT 0 n )  
=  + ln − 1 
k n (VOH − VT 0 n )  VOH − VT 0 n  V50%  

Kenneth R. Laker, University of Pennsylvania

 12

C load  2 VT 0 n  2(VOH − VT 0 n )  
=  + ln − 1 
k n (VOH − VT 0 n )  VOH − VT 0 n  V50%  

SUBSTITUTING V50% = 0.5 [VOL +VOH]

C load  2 VT 0 n  4(VOH − VT 0 n )  
τ PHL =  + ln  − 1 
k n (VOH − VT 0 n )  VOH − VT 0 n  VOH + VOL  

WHERE for CMOS Inverters VOL = 0, VOH = VDD

C load  2 VT 0 n  4(VDD − VT 0 n )  
τ PHL =  + ln  − 1 
k n (VDD − VT 0 n )  VDD − VT 0 n  VDD  

Kenneth R. Laker, University of Pennsylvania

 EXAMPLE 6.1 13

Consider a CMOS inverter with Cload = 1.0 pF, where the IV

characteristics of the nMOS transitor driver are specified as
follows:

VGSn = 5 V and VDSn > 4V => IDn = IDnsat = 5 mA

Assume Vin is a step pulse that switches instantaneously from

0 to 5 V. Calculate the delay time necessary for the inverter
output to fall from its initial value of 5 V to 2.5 V.

V50% = 0.5 [VOL + VOH] = 0.5 [0 + 5 V] = 2.5 V

FROM IV DATA: at SAT VDSn = 5V - VT0n = 4 V => VT0n = 1 V
2 I Dnsat 10 mA −3
kn = = = 0.625x10 A/V 2

(VGS − VT 0 n )2 (4V) 2

Kenneth R. Laker, University of Pennsylvania

 t0 < t < t1’: where iDn = IDnsat = 5mA
14

VOH - VT0n = 4 V
VOH = 5 V

t1’ < t < t1:

C load  2(VOH − VT 0 n ) − V50% 
t1 − t ='
ln 
k n (VOH − VT 0 n )  
1
V50%
1pF  2(5 − 1)V− 2.5V
= ln  
−3
(0.625x10 A/V )(5 − 1)V
2  2.5V 
1x10−12 F  5.5 = 1.26 ns
= ln  
−3 2
(0.625x10 A/V )4V  2.5

τ PHL = 0.2 ns+ 1.26 ns = 1.46 ns

Kenneth R. Laker, University of Pennsylvania
 EXAMPLE 6.2 15

Consider a CMOS inverter with Cload = 1.0 pF and VDD = 5 V,

where the IV characteristics of the nMOS transitor driver are
specified as follows:
kn’ = µnCox = 20 µA/V2, (W/L)n = 10, and VT0n = 1.0 V
Use both the average-current method and the differential
equation method to calculate τfall(time elapased between the
time Vout =V90% = 4.5 V to the time at which Vout =V10% = 0.5 V).
average-current method
5V 4.5V 5V 0.5V
I avg,fall = [ i C ( Vin = VOH , Vout = V90% ) + i C ( Vin = VOH , Vout = V10% )]
1
2
1 1 2 
=  k n (Vin − VT 0 n ) + k n (2(Vin − VT 0 n )Vout − Vout )
2 1
2 2 2 
1
4
[
= k n ( VOH − VT 0 n ) + (2(VOH − VT 0 n )V10% − V10%
2
] 2
)
= 20 x10 −6 (A/V 2 )(10)[(5 − 1)2 V 2 + (2(5 − 1)0.5 − (0.5) 2 ) V 2 ] = 0.9875mA
1
4
Kenneth R. Laker, University of Pennsylvania
 average-current method cont. 16

C load ∆ V 1x10−12 F(4.5 − 0.5)V −9

τ fall = = −3 = 4.05x10 s = 4.09 ns
I avg,fall 0.9875x10 A
τfall = t2 - t0
differential equation method VOH Vout
V90%
SAT for 4.0 V < Vout < 4.5 V VOH - VT0n LIN
dV 1 SAT
C load out = − k n (Vin − VT 0 n )
2

dt 2 V10%
VOH = 5 V t
t0 tsat t2
dVout kn 20 x10 −6 A/V2 (10)
=− ( Vin − VT 0 n ) = −
2
(5 − 1) 2

dt 2 Cload 2(1x10−12 F)
= −1.6 x10 −9 V/s

Kenneth R. Laker, University of Pennsylvania

tsat - t0 = 0.3125 ns
 Vout τfall = t2 - t0 17
differential equation method cont VOH
V90%
tsat = 0.3125 ns VOH - VT0n LIN
SAT
LIN for 0.5 V < Vout < 4.0 V V10%
t
t2
= − k n (2(Vin − VT 0 n )Vout − Vout )
dVout 1 2 t0 = 0 tsat
C load
dt 2
t= t 2 Vout= 0 . 5 V
dVout
∫ dt = −2 C load ∫
Vout =4.0 V k n ( 2(Vin − VT 0 n )Vout − Vout )
2
t = t sat

VOH = 5 V
C load 1  2(Vin − VT 0 n ) − V10% 
t 2 − t sat = ln 
k n (Vin − VT 0 n )  V10% 
VOH = 5 V
1x10 −12 F 1  2(5 − 1) − 0.5
= ln = 3.385 ns
20 x10 A/V (10) (5 − 1)V 
−6 2
0.5 

Kenneth R. Laker, University of Pennsylvania = 4.09 ns Iavg method

 18
2) Vin - FALLING CASE: Vin
IC: Vout = VOL, Vin = VOH -> VOL VOH = VDD
0
nMOS - OFF SAT Vout < Vin - VT0p = -VT0p
p-MOS ON LIN Vout > -VT0p

VGS = Vin - VDD VDS = Vout - VDD VOL = 0 t

τPLH = t1 - t0
Vout
Vin
S VOH = VDD
G B

D iDp iC= iDp V50%

Vout
iDn = 0 -VT0p
iC
VOL = 0 t
Cload t0 t1’ t1
dVout
C load = iD p
dt nMOS SAT
nMOS LIN
Kenneth R. Laker, University of Pennsylvania
 19
C load  2 | VT 0 p |
τ PLH = 
k p (VOH − VOL − | VT 0 p |)  VOH − | VT 0 p |
 2(VOH − VOL − | VT 0 p |)  
+ ln − 1 
 VOH − V50% 
V50% = 0.5 [VOL +VOH], FOR CMOS INV: VOL = 0, VOH = VDD
C load  2 | VT 0 p |  4(VDD − | VT 0 p |)  
τ PLH =  + ln − 1 
k p (VDD − | VT 0 p |)  VDD − | VT 0 p |  VDD 

C load  2 VT 0 n  2(VOH − VT 0 n )  
τPHL =  + ln − 1 
k n (VOH − VT 0 n )  VOH − VT 0 n  V50%  
FOR CMOS INV: VOL = 0, VOH = VDD
C load  2 VT 0 n  4(VDD − VT 0 n )  
τ PHL =  + ln  − 1 
k n (VDD − VT 0 n )  VDD − VT 0 n  VDD  

Kenneth R. Laker, University of Pennsylvania

 20
CONDITIONS FOR Balanced CMOS Inverter Propagation
Delays, i.e. τPHL = τPLH

C load  2 | VT 0 p |  4(VDD − | VT 0 p |)  
τ PLH =  + ln − 1 
k p (VDD − | VT 0 p |)  VDD − | VT 0 p |  VDD 

C load  2 VT 0 n  4(VDD − VT 0 n )  
τ PHL =  + ln  − 1 
k n (VDD − VT 0 n )  VDD − VT 0 n  VDD  

where &

FOR τPHL = τPLH

VT0n = |VT0p|
kn = kp or
 21
NOTE THAT:
• Calculation of τ , depends largely on NMOS driver, i.e.
PHL
nearly same for all INV types.
• Calculation of τ , depends largely on the load device and its
PLH
operation, i.e. different for all INV types. VDD
CONSIDER depletion NMOS Load: +
Vout = VOL, Vin = VOH -> VOL -
IL
dVout
C load = i D , L(Vout ) VGS,L = 0 ID
dt
Vout
VT,L = VT 0 , L+ γ ( | 2φF | + Vout − | 2φF |) V in

SAT: VDS,L = VDD - Vout > 0 - VT,L => Vout < VDD + VT,L
kn,L
[ − VT,L (Vout )]
2
ID , L =
2
LIN: VDS,L = VDD - Vout < 0 - VT,L => Vout > VDD + VT,L
kn,L
ID , L =
2
[ T,L out DD out
2(− V (V ))(V − V ) − (VDD − Vout ) 2
]
Kenneth R. Laker, University of Pennsylvania
 22

Vout = VDD −| VT,L |  dV  Vout= V50%

 dV  
τ PLH = C load  ∫ 
out
+ ∫ 
out

 Vout= VOL  i D , L(sat) Vout= VDD −| VT,L |  i D , L(lin) 

C load  2(VDD − | VT,L | − VOL )  2 | VT,L | −(VDD − V50% )  

τ PLH =  + ln 
k n,L | VT , L |  | VT,L |  VDD − V50% 

Kenneth R. Laker, University of Pennsylvania

 VDD Input Waveform Slope 23

Vout,Vin
iDp Vout VDD
Vin Vin,90%
iDn iC
Cload Vin,10% t
τf τr
EMPERICAL DELAY
VDD CORRECTIONS FOR INPUT τr, τf:
τ
 
2
τ PHL (actual) = τ P HL 2 (step− input) +  r 
 2
Vin iDp Vout
 τ 
2

iC τ PLH (actual) = τ PLH2 (step− input) +  f 

iDn  2
Cload

Kenneth R. Laker, University of Pennsylvania

 24
INVERTER DELAY DESIGN FORMULAS
C load  2 VT 0 n  4(VDD − VT 0 n )  
τ PHL =  + ln  − 1 
k n (VDD − VT 0 n )  VDD − VT 0 n  VDD  

where

C load  2 | VT 0 p |  4(VDD − | VT 0 p |)  
τ PLH =  + ln − 1 
k p (VDD − | VT 0 p |)  VDD − | VT 0 p |  VDD 

where
 EXAMPLE 6.3 25

Design a CMOS inverter by determining the Wn and Wp of the

nMOS and PMOS transistors to meet the following specs:
-> Vth = 2 V for VDD = 5 V
-> Delay time of 2 ns for a Vout transition from 4 V to 1 V,
with Cload = 1.0 pF.
The process and device parameters are specified as follows:
kn’ = µnCox = 30 µA/V2,
kp’ = µpCox = 10 µA/V2
Ln = Lp =1.0 µm
VT0n = 1.0 V
VT0p = -1.5 V
Wmin = 2 µm (limited by design rules)

STEP #1: Satisfy the Delay Constraint:τPHL from 4 V to 1 V

HL => PULL-DOWN => τPHL determined by nMOS driver
NOTE Vin = VOH and 1 < Vout < 4 V => nMOS LIN
Kenneth R. Laker, University of Pennsylvania
 µ n C ox Wn
[ ]
dVout 26
C load =− 2(VOH − VT 0 n ) Vout − Vout
2

dt 2 Ln
Vout =1
−9 1 dVout
τ delay = 2.0 x10 s = −2 Cload Wn Vout∫ =4 [ 2(VOH − VT 0 n )Vout − Vout
2
]
µ n C ox
Ln
1 1  Vout  Vout =1
= −2 C load Wn 2(VOH − VT 0 n ) ln 2(VOH − VT 0 n ) − Vout  Vout =4
µ n C ox
Ln

Wn 1x10−12 F 1
= −9 −6 2 ln(7) = ln(7) = 8.108
L n (2.0 x10 s)(30 x10 A/V )(4) (2.0)(0.03)(4)
Kenneth R. Laker, University of Pennsylvania
 27
Wn
= 8.108 , Ln = 1µm => Wn = 8.108 (1 µm) = 8.1 µm
Ln From τdelay spec.
STEP #2: Satisfy the Vth constraint, where:
VT 0 n +
1
kR
( VDD + VT 0 p ) 1.0 V+
1
kR
( 5 + (−1.5)) V
Vth = =
 1   1
1 +  1 + 
 kR   kR 
1
1.0 V+ (3.5) V 9
kR => k = (1.5) 2
=
= = 2V R
 1 4
1 + 
 kR 

µ n C ox ( W/L )n 30 Wn Wn 9 4
kR = = =3 = => Wp = (3)Wn
µ p C ox ( W/L )p 10 Wp Wp 4 9
4
with Lp = 1 µm Wp = (3)8.1µ m = 10.8µ m
Kenneth R. Laker, University of Pennsylvania 9
 CMOS RING OSCILLATOR 28

1 V1 2 V2 3 V3

Cload,1 Cload,2 Cload,3

Cload,1 = Cload,2 = Cload,3 and INV1 = INV2 = INV3

V1 V2 V3
VOH

V50%

VOL t
τPHL2 τPHL1 τPLH3
τPLH3 τ τPHL1
PHL2

Kenneth R. Laker, University of Pennsylvania

T
 V1 V2 V3 29
VOH

V50%

VOL t
τPHL2 τPHL1 τPLH3
τPLH3 τ τPHL1
PHL2

T
Cload,1 = Cload,2 = Cload,3 and INV1 = INV2 = INV3
T = τPHL2 + τPLH3 + τPHL1 + τPHL2 + τPLH3 + τPHL1 = 6τP
1 1 1
f= = = Oscillation FREQ
T 2(3)τ P 6τ P
For n INVERTERS:
1 1 1
f= = or τP =
T 2 n τP 2 nf
Kenneth R. Laker, University of Pennsylvania
 ESTIMATION OF INTERCONECT PARASITICS 30

MET
L
Current
W Flow

t
h SIO2

SUB

PARASITIC RESISTANCE:
L L
R metal = ρ = R sheet
Wt W

Kenneth R. Laker, University of Pennsylvania

 fringing fields W 31
t
h

CPP
FF = Ctotal/CPP -> FRINGING-FIELD FACTOR
FF -> INC as t/h -> INC, W/h <- DEC, and W/L -> INC
(SEE PLOT FF in FIG. 6.18 of TEXT)
 t 
W− 2π 
C total = ε  2+  pF/µm L for W > t/2
 h  2h 2 h  2 h   
ln1 + + +2 
  t t  t  
  t  
W π  1 − 0.0543  
 2h 
C total = ε  + + 1.47 pF/µm L
 h ln1 + 2 h + 2 h  2 h + 2   for W < t/2
  t t  t  
Kenneth R. Laker, University of Pennsylvania
 32

W
L
C
int

W
int
t
oxF

C C
p-sub oxFt oxFt C
pa

Double-metal double-poly n-well CMOS process

Cmm Cmetal-to-metal = 2.5 nF/cm2
Coxm Cmetal-to-substrate = 5.2 nF/cm2
Coxp Cpoly-to-substrate = 6.5 nF/cm2
Cmm Cmetal-to-poly = 12.0 nF/cm2

Kenneth R. Laker, University of Pennsylvania

 C D E 33
B F
passivation
A m2 G
m2
m2
m2 m2
m1
m1 m2
field ox
poly poly m1
poly field ox
field ox field ox field ox

substrate field ox
Layer Cap Ox Thickness Typ Value
A Poly-substrate Cp 3000 Å 50 aF/µm2 1 µm CMOS
B Metal2-sub Cm2 9000 Å 20 aF/µm2 Capacitances
C Poly-metal2 Cm2p 6000 Å 30 aF/µm2 tox = 200Å
D Metal1-sub Cm1 6000 Å 30 aF/µm2 Cg = 1800 aF/µm2
E Metal1-poly Cm1p 3000 Å 60 aF/µm2 aF = 10-18 F
E Metal1-metal2 Cm2m1 6000 Å 50 aF/µm2
F Metal1-diffusion Cm1d 3000 Å 60 aF/µm2
G Metal2-diffusion Passivation 6000 Å 30 aF/µm2
Kenneth R. Laker, University of Pennsylvania
 32
A B

Zout Zc

RLCG Transmission Line

C

VA

τdelay
t
VB |Zout| << |Zc|
τbuffer + τflight τrise τsettle
t
Kenneth R. Laker, University of Pennsylvania
 35
ROUTE-LENGTH DESIGN GUIDE
To ignore the RC delay of interconnect, τW << τPgate
emperical formula
L = length of route
r = sheet resistance
c = cap per unit length
EXAMPLE: Consider a minimum width metal1 route to a node
with an associated gate delay of 200 ps.
GUIDELINES FOR IGNORING
RC DELAYS (Weste, pp 205)
Layer Max Length (LW)
metal3 10,000 λ
metal2 8000 λ
metal1 5000 λ
Conservatively, LW < 5000λ
silicide 600 λ
λ = design rule parameter
poly 200 λ
Kenneth R. Laker, University of Pennsylvania diffusion 60 λ
 36
POWER DISSIPATION

Ps = Static power dissipation due to leakage current or other current

drawn continuously from the power supply.

Pd = dynamic power dissipation due to charging and discharging load

capacitances (vin assumed to be square-like)

Psc = short circuit power dissipation due to charging and discharging

load capacitances during the finite rise and fall times of vin.

Kenneth R. Laker, University of Pennsylvania

 VDD DYNAMIC POWER DISSAPATION 37

Vin, Vout
S VOH
G B

D iDp iC= iDp- iDn

Vin
Vout V
D iDn iC OL t
G B iC T/2 T
Cload nMOS nMOS
S ON ON
t
pMOS
1T ON
Pd = ∫ v(t)i(t)dt
T0
1 T/ 2 1 T
Pd = ∫ Vout (t)i Dn (t)dt + ∫ (VDD − Vout (t)) i Dp (t)dt
T 0 T T/ 2
dVout dVout
where i Dn (t) = − C load i Dp (t) = C load
dt dt
Kenneth R. Laker, University of Pennsylvania
 1 T/ 2  dVout  1 T  dVout  38
Pd = ∫ Vout (t) − C load dt + ∫ (VDD − Vout (t)) C load dt
T 0  dt  T T/ 2  dt 
Vin, Vout
VOH

VOL t
iC T/2 T
nMOS nMOS
ON ON
t
pMOS
ON
1 0 1 VDD
Pd = ∫ − C load Vout (t)dVout + ∫ C load ( VDD − Vout (t)) dVout
T VDD T 0
1 Vout2
Vout =0  V 2
 Vout = VDD 
= − C load Vout =VDD + C load  VDD Vout −
out
 Vout = 0 
T 2  2  
Kenneth R. Laker, University of Pennsylvania
 1   
2 2 39
Vout Vout =0 Vout Vout =VDD
Pd = − C load + C load  VDD Vout − 

Vout =VDD Vout =0
T 2  2 

1
= 2
C load VDD
T
Pd = C load VDD
2
f

APPLIES TO GENERAL CMOS LOGIC CIRCUITS

VDD

pMOS
Logic
iDp Vout
iDn iC
nMOS Cload
Logic

Kenneth R. Laker, University of Pennsylvania

 40
POWER-DELAY PRODUCT

where P*avg = average switching power dissipation at max

operating frequency fmax.

&

AVERAGE ENERGY required for a gate to switch its output

from LOW to HIGH and from HIGH to LOW

FUNDAMENTAL PARAMETER used to for measuring

quality and performance of a CMOS process and gate design
 POWER METER SIMULATION 41

VDD
iDD(t) Power Meter
+
Cy Vy
is βis
Ry
Vs = 0 +
−
−
is(t) = iDD(t) Vy(0) = 0
Periodic Input DEVICE dVy Vy
or Cy = β iS −
T = Period dt Ry
CIRCUIT Cload

IF RyCy >> T + Vy(0)

Cy
SET β = VDD 1T
T Vy (T) = VDD ∫ i DD (τ)d τ => Pd
T0
Kenneth R. Laker, University of Pennsylvania