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CHAPTER 3 - CMOS MODELS - Analog IC
CHAPTER 3 - CMOS MODELS - Analog IC
0-1
Fig.3.0-1
CMOS Analog Circuit Design © P.E. Allen - 2005
Refined and
optimized
design Fig.3.0-02
This chapter is devoted to the simple model suitable for design not using simulation.
CMOS Analog Circuit Design © P.E. Allen - 2005
Chapter 3 – Introduction (8/3/05) Page 3.0-3
Time Dependence
Time Independent Time Dependent
;;;
Metal-Oxide-Semiconductor Structure
Bulk/Substrate Source Gate Drain
;;;
Thin Oxide
(10-100nm
Polysilicon 100Å-1000Å)
p+ n+ n+
p- substrate
;;;;;
Subthreshold (VG<VT)
VB = 0 VS = 0 VG < VT VD = 0
;;;
Polysilicon
;; ;;;
p+ n+ n+
;;;
p- substrate Depletion Region
Threshold (VG=VT)
;;;;;;
;;;
VB = 0 VS = 0 VG =VT VD = 0
Polysilicon
p+
;; ;;;n+ n+
;;;
p- substrate Inverted Region
;;;
VB = 0 VS = 0 VG >VT VD = 0
;;;;;;
;;;
Polysilicon
p+ n+ n+
Fig.3.1-02
;;;
VGS≤VT:
VB = 0 VS = 0 vG =VT VD = 0.1V iD
;; ;;;
iD
Polysilicon
;; ;;;
p+ n+ n+
;;;
p- substrate Depletion Region 0 vGS
0 VT 2VT 3VT
VGS=2VT:
;;;;
;; ;;;
VB = 0 VS = 0 VG = 2VT VD = 0.1V iD
iD
Polysilicon
p+
;; ;;;n+ n+
;;;
p- substrate Inverted Region
0 vGS
0 VT 2VT 3VT
VGS=3VT:
;;;
VB = 0 VS = 0 VG = 3VT VD = 0.1V iD
;;;;;;
;;;
Polysilicon
p+ n+ n+
;;;
VDS=0:
VB = 0 VS = 0 vG =2VT VD = 0V iD
;;;;
;; ;;;
iD
Polysilicon VGS = 2VT
;; ;;;
p+ n+ n+
;;;
p- substrate Inverted Region
0 vDS
0 0.5VT VT
VDS=0.5VT:
;;
;;;;
;;;
VB = 0 VS = 0 VG = 2VT VD = 0.5VT iD
iD
Polysilicon VGS = 2VT
p+
;;
;;;;
;;;
n+ n+
;;;
p- substrate Channel current
0 vDS
0 0.5VT VT
VDS=VT:
;;;
VB = 0 VS = 0 VG = 2VT VD =VT iD
;;
;;;;
;;;
iD VGS = 2VT
Polysilicon
p+ n+ n+
A depletion region
p- substrate
forms between the drain and channel 0 vDS
0 0.5VT VT Fig.3.1-04
CMOS Analog Circuit Design © P.E. Allen - 2005
;;;
VGS=VT:
VB = 0 VS = 0 vG =VT VD = 2VT iD
;; ;;;
iD
Polysilicon
;; ;;;
p+ n+ n+
;;;
p- substrate VGS =VT
0 vDS
0 VT 2VT 3VT
VGS=2VT:
;;
;;;;
;;;
VB = 0 VS = 0 VG = 2VT VD = 2VT iD
iD
Polysilicon
;;
;;;;
;;;
VGS =2VT
p+ n+ n+
;;;
p- substrate
0 vDS
0 VT 2VT 3VT
VGS=3VT:
;;;
VB = 0 VS = 0 VG = 3VT VD = 2VT iD
VGS =3VT
;;
;;;;
;;;
iD
Polysilicon
p+ n+ n+
Further increase in
p- substrate
VG will cause the FET to become active 0 vDS
0 VT 2VT 3VT
Fig.3.1-05
CMOS Analog Circuit Design © P.E. Allen - 2005
Chapter 3 – Section 1 (8/3/05) Page 3.1-6
1500
VGS = 2.5
iD(μA)
1000
VGS = 2.0
500
VGS = 1.5
VGS = 1.0
0
SPICE Input File: 0 1 2 3 4 5
vDS (Volts) Fig. 3.1-6
Output Characteristics for NMOS M5 6 5 0 0 MOS1 w=5u l=1.0u
M1 6 1 0 0 MOS1 w=5u l=1.0u VGS5 5 0 3.0
VGS1 1 0 1.0 VDS 6 0 5
M2 6 2 0 0 MOS1 w=5u l=1.0u .model mos1 nmos (vto=0.7 kp=110u
VGS2 2 0 1.5 +gamma=0.4 +lambda=.04 phi=.7)
M3 6 3 0 0 MOS1 w=5u l=1.0u .dc vds 0 5 .2
VGS3 3 0 2.0 .print dc ID(M1), ID(M2), ID(M3), ID(M4),
M4 6 4 0 0 MOS1 w=5u l=1.0u ID(M5)
VGS4 4 0 2.5 .end
CMOS Analog Circuit Design © P.E. Allen - 2005
3000
VDS = 2V
2000
VDS = 1V
1000
0
SPICE Input File: 0 1 2 3 4 5
vGS (Volts) Fig. 3.1-7
Transconductance Characteristics for NMOS M5 5 6 0 0 MOS1 w=5u l=1.0u
M1 1 6 0 0 MOS1 w=5u l=1.0u VDS5 5 0 5.0
VDS1 1 0 1.0 VGS 6 0 5
M2 2 6 0 0 MOS1 w=5u l=1.0u .model mos1 nmos (vto=0.7 kp=110u
VDS2 2 0 2.0 +gamma=0.4 lambda=.04 phi=.7)
M3 3 6 0 0 MOS1 w=5u l=1.0u .dc vgs 0 5 .2
VDS3 3 0 3.0 .print dc ID(M1), ID(M2), ID(M3), ID(M4),
M4 4 6 0 0 MOS1 w=5u l=1.0u ID(M5)
VDS4 4 0 4.0 .probe
.end
CMOS Analog Circuit Design © P.E. Allen - 2005
Chapter 3 – Section 2 (8/3/05) Page 3.2-1
;;;
3.2 - LARGE SIGNAL FET MODEL FOR HAND CALCULATIONS
;;;
Large Signal Model Derivation +
vGS +
-
1.) Let the charge per unit area in the channel iD - vDS
inversion layer be
n+ n+
QI(y) = -Cox[vGS-v(y)-VT] (coul./cm2) Source
v(y)
dy Drain
p- y
2.) Define sheet conductivity of the inversion 0 L y y+dy
layer per square as Fig.110-03
cm2
coulombs amps 1
S = μoQI(y)
v·s
cm2 = volt = /sq.
3.) Ohm's Law for current in a sheet is
iD dv -iD -iDdy
JS = W = -SEy = -S dy dv = SW dy = μoQI(y)W iD dy = -WμoQI(y)dv
4.) Integrating along the channel for 0 to L gives
L vDS vDS
iDdy = - WμoQI(y)dv = WμoCox[vGS-v(y)-VT] dv
0 0 0
5.) Evaluating the limits gives
WμoCox v2(y)vDS WμoCox vDS2
iD = L (vGS-VT)v(y) -
2 0 iD = L (vGS-VT)vDS -
2
CMOS Analog Circuit Design © P.E. Allen - 2005
Increasing
values of vGS
vDS
Fig. 110-04
The saturation voltage for MOSFETs is the value of drain-source voltage at the peak of
the inverted parabolas. v DS
diD μoCoxW
dvDS = L [(vGS-VT) - vDS] = 0 Cutoff Saturation Active
T
V
S-
vDS(sat) = vGS - VT
vG
S=
Useful definitions:
vD
0 vGS
μoCoxW K’W 0 VT Fig. 3.2-4
L = L =
CMOS Analog Circuit Design © P.E. Allen - 2005
Chapter 3 – Section 2 (8/3/05) Page 3.2-3
Illustration of the Need to Account for the Influence of vDS on the Simple Sah Model
Compare the Simple Sah model to SPICE level 2:
25μA
2
K' = 44.8μA/V
20μA k = 0, v DS(sat) 2
K' = 44.8μA/V
= 1.0V k=0.5, v DS(sat)
= 1.0V
15μA
iD
10μA SPICE Level 2
K' = 29.6μA/V 2
5μA k = 0, vDS(sat)
= 1.0V
0μA
0 0.2 0.4 0.6 0.8 1
vDS (volts)
VGS = 2.0V, W/L = 100μm/100μm, and no mobility effects.
To find vDS(sat), set the diD/dvDS equal to zero and solve for vDS = vDS(sat),
vGS - VT
vDS(sat) = 1 + k
Therefore, in the saturation region, the drain current is
WμoCox
iD = 2(1+k)L (vGS - VT)2
For k = 0.5 and K’ = 44.8μA/V2, excellent correlation is achieved with SPICE 2.
CMOS Analog Circuit Design © P.E. Allen - 2005
;;;
Channel modulation effect: VG > VT VD > VDS(sat)
As the value of vDS increases, the
;;;;;;;
B S
effective L decreases causing the
Depletion
current to increase. Polysilicon
;;;;;;;
Region
p+ n+ n+
Illustration:
Leff
;;;
Influence of the Bulk Voltage on the Large Signal MOSFET Model
;;
;;;;;;;
Illustration of the influence of the bulk: VBS0 = 0V
VS = 0 VG > VT VD > 0
VSB0 = 0V: Polysilicon
iD
p+
p- substrate
;;;;;;;;;
n+
Channel current
n+
;;;
Fig.110-07A
;;;;
;; ;;;
VSB1 > 0V
VSB1>0V: VS = 0 VG > VT VD > 0
iD
Polysilicon
p+
;;
;;;;;;;
n+ n+
;;;
p- substrate Channel current
Fig.110-07B
;; ;;;
;;;;
VSB2 > VSB1: VSB2 >VSB1 V = 0 VG > VT VD > 0
S
iD = 0
Polysilicon
p- substrate
;;
;;;;
;;;
n+ n+
Fig.110-07C
© P.E. Allen - 2005
Chapter 3 – Section 2 (8/3/05) Page 3.2-9
Influence of the Bulk Voltage on the Large Signal MOSFET Model - Continued
Bulk-Source (vBS) influence on the transconductance characteristics-
iD
Decreasing values
of bulk-source voltage
VBS = 0
ID
vDS ≥ vGS-VT
vGS
VT0 VT1 VT2 VT2
Fig. 110-08
In general, the simple model incorporates the bulk effect into VT by the previously
developed relationship:
Silicon Constants
MOSFET Parameters
Model Parameters for a Typical CMOS Bulk Process (0.8μm CMOS n-well):
where, iD iBD
G rG vBS rB B
rG, rS, rB, and rD are ohmic and contact + -
resistances iBS
and
vBD
CGS CBS
iBD = Is exp Vt - 1
and CGB
rS
v
BS
iBS = Is exp V
t
-1
S Fig. 3.2-10
VELOCITY SATURATION
What is Velocity Saturation?
The most important short-channel
104
An expression for the electron drift 5x103
velocity as a function of the electric 105 106 107
field is, Electric Field (V/m) Fig130-1
μn E
vd 1 + E/Ec
where
vd = electron drift velocity (m/s)
μn = low-field mobility ( 0.07m2/V·s)
Ec = critical electrical field at which velocity saturation occurs
CMOS Analog Circuit Design © P.E. Allen - 2005
L GS T DS DS 2[1+ (v GS T L
-V )]
21 + Ec L
Saturation Voltage
Differentiating iD with respect to vDS and setting equal to zero gives,
vDS2 + 2vDS – 2(VGS-VT) = 0
Solving for vDS gives,
1 (VGS-VT)
V’DS(sat) = 1 + 2(VGS-VT -1 (VGS-VT)1 -
2 + ···
or
(VGS-VT)
V’DS(sat) VDS(sat) 1 - 2 + ···
Note that the transistor will enter the saturation region for vDS < vGS - VT in the presence
of velocity saturation.
Therefore the large signal model in the saturation region is,
K’ W (VGS-VT)
iD = 2[1 + (vGS-VT)] L [ vGS - VT]2, vDS (VGS-VT) 1 -
2 + ···
600
θ = 0.6
400
θ = 0.8
θ = 1.0
200
0
0.5 1 1.5 2 2.5 3
vGS (V) Fig130-2
Note as the velocity saturation effect becomes stronger, that the drain current-gate
voltage relationship becomes linear.
0.11μm
600
VGS=1.4V
500
400 VGS=-1.8V
VGS=1.0V
300 VGS=-1.4V
200
VGS=-1.0V
100 VGS=0.6V
VGS=-0.6V
0
-1.8 -1.2 -0.6 0.0 0.6 1.2 1.8
Drain Voltage (V) Fig130-4
†
Su, L., et.al., “A High Performance Sub-0.25μm CMOS Technology with Multiple Thresholds and Copper Interconnects,” 1998 Symposium on
VLSI Technology Digest of Technical Papers, pp. 18-19.
CMOS Analog Circuit Design © P.E. Allen - 2005
Chapter 3 – Section 3 (8/3/05) Page 3.3-8
1 gm 1 gm
fT = 2 Cgs L-2 fT = 2 Cgs L-1
0.6
0.5
0.4
PMOS
0.3
0.2
NMOS
0.1
0
0 0.5 1 1.5 2 2.5
Channel Length (microns) Fig.130-6
CMOS Analog Circuit Design © P.E. Allen - 2005
Chapter 3 – Section 3 (8/3/05) Page 3.3-10
;;;
yyy
Weak inversion operation occurs when the applied gate voltage is below VT and
;;;
pertains to when the surface of the substrate beneath the gate is weakly inverted.
VGS
n+ n-channel n+
Diffusion Current
p-substrate/well
Fig. 140-01
10-12 V
0 VT Fig. 140-02 GS
The electrons in the substrate at the drain side can be expressed as,
-v
s DS
np(L) = npoexp Vt
VGS<VT
0 vDS
0 1V
Fig. 140-03
CMOS Analog Circuit Design © P.E. Allen - 2005
Chapter 3 – Section 3 (8/3/05) Page 3.3-14
diD | ID
gds = dvDS Q VA
100μA
10μA
iD vGS
1μA
ID(M1)
100nA
10nA
1nA
100pA
0V 0.4V 0.8V 1.2V 1.6V 2V
VGS Fig. 140-05
†
Y. Cheng and C. Hu, MOSFET Modeling & BSIM3 User’s Guide, Kluwer Academic Publishers, Boston, 1999.
CMOS Analog Circuit Design © P.E. Allen - 2005
Chapter 3 – Section 3 (8/3/05) Page 3.3-16
10μm2 3.98.85410-14(F/cm)(100cm/106μm)
Cgs = WL Cox + Cjs
= 0.33WLCox = 3
100Å (106μm/1010Å)
1 1 25.75μS
Cgs = 11.5fF fT = 2 T = 2 11.5fF 360MHz
(Equivalent transistor operating in strong inversion has an fT = 3.4GHz)
;;;
VG > VT
;;;;;;;;
B S VD > VDS(sat)
Polysilicon
Depletion
;;;;;;;;
Region
p+ n+ A
Free n+
;;;;;;;;
Fixed electron
Atom
p- substrate Free
hole
Fig130-7
iDB
G
B
S Fig130-8
Small-signal model:
iDB IDB
gdb = vDB = K2 VDS - VDS(sat)
This conductance will have a negative influence on high-output resistance current
sinks/sources.
CMOS Analog Circuit Design © P.E. Allen - 2005
Present Solution
Keep circuit separate by using multiple substrates and put the multiple substrates in the
same package.
;; ;
RL Substrate Noise
vin vout vout
VGS vin
vin VDD(Analog)
;;;;;;;;
;;; ;;;
vin vout RL
VDD(Digital) VGS
Digital Ground
n+ channel vout Analog Ground
stop (1 Ω-cm)
;;;;;;;;
;;; ;;;
p+ n+ n+ p+ p+ n+ n+ n+ p+
p+ channel stop (1Ω-cm)
n- well "AC ground"
Hot Back-gating due to a
iD
Carrier momentary change in
Put substrate connections reverse bias
as close to the noise source
as possible ΔiD
ID
"AC ground" ΔiD
vGS
p- substrate (10 Ω-cm) VGS
;; ;
RL Substrate Noise
vin vout vout
VGS vin
vin VDD(Analog)
;;;;;;;;
;;; ;;;
vin vout RL
VDD(Digital) VGS
Digital Ground vout Analog Ground
;;;;;;;;
;;; ;;;
p+ n+ n+ p+ p+ n+ n+ n+ p+
;;
VDD
vin vout
L1
Cs1
n- well
Digital Ground VDD(Digital)
;;;;;;
;;;;;
vin vout
Cs3 Cs2
vin vout Rs1 Substrate
;;;;;;
;;;;;
Rs2
Rs3
p+ n+ n+ p+ p+ n+
n- well Cs4
;;;;;
Hot Cs5
Carrier Coupling
Hot
L2 L3
Carrier Coupling
Coupling
;
RL Substrate Noise
vin vout
VGS VDD
VDD(Analog)
vin RL RL
vout
vout
;;;
VGS Analog Ground L4 CL
;;;
L6
n+ n+ p+
VGS
Cs6 Rs4 Cs7
Substrate
Cs5
L5
Inductor
Substrate BJT
;;;;;;;;
Collector Base Emitter Collector
n+ p+ n+ n+
p- well
Fig. SI-04
Heavily Lightly Intrinsic Lightly Heavily Metal
Doped p Doped p Doping Doped n Doped n
Also, there is coupling from power supplies and clock lines to other adjacent signal lines.
CMOS Analog Circuit Design © P.E. Allen - 2005
di 4
v = L dt 0
0 1 2 3 4 5 6 7 8
Use multiple bonding wires to reduce the ground Number of Substrate Contact Package Pins
noise caused by inductance. Fig. SI-08
C2
• Fast changing signals have part of
their path (circuit through ground t=0
and power supplies. Therefore - VDD
Vout
bypass the off-chip power Vin C1 +
supplies to ground as close to the VSS
chip as possible.
Fig. SI-05
CMOS Analog Circuit Design © P.E. Allen - 2005
Chapter 3 – Section 3 (8/3/05) Page 3.3-26
SiO2
Gate
Source Drain
C1 C2 C3
FOX FOX
C4
CBS CBD
Bulk
Fig120-06
Gate
Drain-gate overlap
Channel capacitances:
Source-gate overlap
capacitance CGS (C1) capacitance CGD (C3) C2 = gate-to-channel = CoxWeff·(L-2LD) =
Gate CoxWeff·Leff
FOX FOX
Source Drain C4 = voltage dependent channel-
Gate-Channel Channel-Bulk
Capacitance (C2)
Bulk
Capacitance (C4)
bulk/substrate capacitance
Fig. 120-09
Gate
FOX C5 Source/Drain C5 FOX
Bulk
Fig120-10
C5 = CGBO
Capacitance values based on an oxide thickness of 140 Å or Cox=24.7 10-4 F/m2:
Type P-Channel N-Channel Units
CGSO 220 10-12 220 10-12 F/m
CGDO 220 10-12 220 10-12 F/m
CGBO 700 10-12 700 10-12 F/m
CJ 560 10-6 770 10-6 F/m2
CJSW 350 10-12 380 10-12 F/m
MJ 0.5 0.5
MJSW 0.35 0.38
CMOS Analog Circuit Design © P.E. Allen - 2005
;;;
Expressions for CGD, CGS and CGB
Cutoff
Cutoff Region: VB = 0 VS = 0 VG < VT VD > 0
CGS
CGB = C2+2C5 = Cox(Weff)(Leff) Polysilicon
CGD
+ 2CGBO(Leff) p+ n+ CGB n+
CGS = C1 Cox(LD)Weff = CGSO(Weff)
;;;
p- substrate
CGD = C3 Cox(LD)Weff = CGDO(Weff)
Saturated
Saturation Region: VB = 0 VS = 0 VG >VT VD >VG -VT
CGB = 2C5 = 2CGBO(Leff) CGS
Polysilicon
CGD
CGS = C1+(2/3)C2 =
p+ n+ n+
;;;
Cox(LD+0.67Leff)(Weff)
p- substrate Inverted Region
= CGSO(Weff) + 0.67Cox(Weff)(Leff)
CGD = C3 Cox(LD)Weff) = CGDO(Weff) Active
;;;
VB = 0 VS = 0 VG >VT VD <VG -VT
Nonsaturated Region: CGS
Polysilicon
CGD
CGB = 2 C 5 = 2CGBO(Leff)
p+ n+ n+
CGS = C1 + 0.5C2 = Cox(LD+0.5Leff)(Weff)
= (CGSO + 0.5CoxLeff)Weff p- substrate Inverted Region
Fig120-11
CGD = C3 + 0.5C2 = Cox(LD+0.5Leff)(Weff)
= (CGDO + 0.5CoxLeff)Weff
CMOS Analog Circuit Design © P.E. Allen - 2005
Chapter 3 – Section 4 (8/3/05) Page 3.4-6
D D
id
G B
+ + +D
G B G B vgs vbs rds vds
gmvgs gmbsvbs
- - -
S S
S S Fig. 120-01
Assume that vbs = 0,
vds vgs 1 1
AC resistance = id = id = gm + gds gm = Rac
diD | qID
gm = dvGS Q = nkT
diD | ID
gds = dvDS Q VA
1.4
1.2
VT(V) 0.8
0.6
Theory
0.4 matched
at 25°C
0.2
0
0 50 100 150 200 250 300
Temperature (°C) Fig. 3.6-1
1.4
1.2
1
VT(V) 0.8
0.6
Theory
0.4 matched
at 25°C
0.2
0
0 50 100 150 200 250 300
Temperature (°C) Fig. 3.6-2
1000
Data
Symbol Min. L
800 6 μm
5 μm
4 μm
600 2 μm
μ(T)
(cm2/V·s)
400
Theory
matched
at 25°C
200
0
0 50 100 150 200 250 300
Temperature (°C) Fig. 3.6-3
1000
Data
Symbol Min. L
800 6 μm
5 μm
4 μm
600 2 μm
μ(T)
(cm2/V·s)
400 Theory
matched
at 25°C
200
0
0 50 100 150 200 250 300
Temperature (°C) Fig. 3.6-4
25°C
100 100°C
VDS = 6V 150°C
200°C
80 250°C
275°C
ID (μA)
60 300°C
40
150°C
275°C 250°C 200°C
Zero TC Point
20 25°C
100°C
0
0 0.6 1.2 1.8 2.4 3
VGS (V) Fig. 3.6-065
25°C
300°C 100°C
40
VDS = -6V
30 150°C
ID (μA)
20
275°C
VSG(ZTC) ≈ -1.95V
10
150°C
250°C
100°C
25°C
0
0 -0.6 -1.2 -1.8 -2.4 -3.0
VGS (V) Fig. 3.6-066
Zero temperature coefficient will occur for every MOSFET up to about 200°C.
CMOS Analog Circuit Design © P.E. Allen - 2005
;;;
VG > VT VD > VDS(sat)
;;;;;;;
B S
Depletion
Polysilicon
;;;;;;;
Region
p+ n+ n+
p-well
n- substrate
Fig.3.6-5
;;;
VG <VT VD > VDS(sat)
;;; ;;
B S
Depletion
Polysilicon
;;; ;;
Region
p+ n+ n+
p-well
n- substrate
Fig.3.6-6
Go
iD Is = qA
Lp + Ln L N = KT 3exp Vt
Differentiating with respect to temperature gives,
V
V
10-5
200°C Data
10-6 Symbol Min. L
6 μm
250°C
10-7
Leakage Current (A)
5 μm
4 μm
10-8 IR 2 μm
50μm
Lmin 100°C
10-9 1V
Theory
10-10 matched
at 150°C Generation-
Diffusion Recombination
10-11
Leakage Leakage
Dominant Dominant
10-12
1.8 2 2.2 2.4 2.6 2.8
-1
1000/T (°K ) Fig. 3.6-7
Theory:
VG(T)
Is(T) T exp kT
3
MOSFET NOISE
MOS Device Noise at Low Frequencies
D D
D
eN2
G B G in2 G * B
Noise Noise
S B Free
Free S
MOSFET MOSFET S
where
8kTgm(1+) KF ID
in =
2
3 + fSCoxL2 f (amperes2)
f = bandwidth at a frequency, f
gmbs
= gm
k = Boltzmann’s constant
KF = Flicker noise coefficient
S = Slope factor of the 1/f noise
CMOS Analog Circuit Design © P.E. Allen - 2005
KF
It will be convenient to use B = 2CoxK’ for model simplification.
in2
S S
Circuit 1: Frequency Dependent Noise Model
ei2 Cgd
G D
*
vin ii2 Cgs vgs rds io2
gmvgs
S S
Circuit 2: Input-referenced Noise Model
2
gm2 2Cgs2
2Cgs2 in2 if Cgd < Cgs ii2 = gm2 in2
into the base are electrons for the npn transistor and holes for the pnp transistor.
• Base - The base is a region which physically separates the emitter and collector and has
an opposite doping (holes for the npn and electrons for the pnp BJTs). The word
“base” comes from the way that the first transistors were constructed. The base was
the physical support for the whole transistor.
• Collector - The collector serves to “collect” those carries injected from the emitter into
the base and which reach the collector without recombination.
;;;;;
;;;
E B C Depletion
Depletion
;;;;;
;;;
Region Region
n+ p
n
;;
B
;;
E
n+ p n C
A A'
;;
Carrier
Concentration
;;;
Depletion
nnE Region
pp(x) nnC
; ;;;
Depletion
Region
;; ;;;
np(0) ND
NA
pnE(0) np(x) pnC
;;;
np(WB)
pnE
x
A Emitter Base Collector A'
x=0 x =WB Fig.070-04
Comments:
• The above carrier concentrations assume that the base-emitter junction is forward
biased and the base-collector junction is reverse biased.
• The above carrier concentration will be used to derive the large signal model on the
next slide.
CMOS Analog Circuit Design © P.E. Allen - 2005
Chapter 3 – Section 7 (8/3/05) Page 3.7-4
Derivation of the BJT Large Signal Model in the Foward Active Region
1.) Carrier concentrations in the base on the emitter side. The concentration of electrons
in the base on the emitter side (x = 0) is
np(0) = npo exp(vBE/Vt)
The concentration of electrons in the base on the collector side (x = WB) is
np(WB) = npo exp(vBC/Vt) 0 because vBC is negative and large.
2.) If the recombination of electrons in the base is small, then the minority-carrier
concentrations, np(x), are straight lines and shown on the previous page. From
charge-neutrality requirements for the base,
NA + np(x) = pp(x) np(x) - pp(x) = NA
3.) The collector current is produced by minority-carrier electrons in the base diffusing
in the direction of the concentration gradient and being swept across the collector-
base depletion region by the field existing there. Therefore, the diffusion current
density due to electrons in the base is
dnp(x)
Jn = qDn dx
where Dn is the diffusion constant for electrons. The derivative is the slope of the
concentration profile in the base which gives,
np(0)
J = -qD
CMOS Analog Circuit Design n n WB © P.E. Allen - 2005
Derivation of the BJT Large Signal Model in the Foward Active Region - Continued
3.) Continued
If the collector current is defined as positive flowing into the collector terminal, then
np(0) qADnnpo vBE
iC = qADn WB = WB exp Vt
qADnnpo
iC WB 1
F = iB = n W qA qAD n 2 = W 2 D W N 50 to 150
1 po B p i B p B A
2 b + Lp ND 2bDn + Dn Lp ND
Note that F is increased by decreasing WB and increasing ND/NA.
Derivation of the Current Gain from Emitter to Collector in Forward Active Region
iC
1.) Emitter to collector current gain is designated as, F = iE .
2.) Since sum of all currents flowing into the transistor must be zero, we can write that
iC iC
1
iE = -(iC+iB) = - iC + F =- iC 1+ F = - F
F 1 1
F = 1 + F = 1 = WB 2 Dp WB NA T
1 + F 1 +
2bDn + Dn Lp ND
where
1
T Base Transport factor WB2 1
1 + 2bDn
and
1
Emitter injection efficiency Dp WB NA 1
1 + Dn Lp ND
Large Signal Model for the BJT in the Forward Active Region
Large-signal model for a npn transistor:
iB
B C B C
+ +
vBE VBE(on)
βFiB βFiB
- Assumes vBE is a -
E E E E
v constant and iB is
iB = Is exp BE determined externally Fig.070-05
βF Vt
;; ;;;
Carrier Collector depletion
Concentration region widens due to a
change in vCE, ΔVCE
;; ;;;
Initial
Depletion
;; ;;;
Region
np(0) = npo exp vBE
Vt
;; ;;;
iC
iC+ΔiC
x
Emitter WB Collector
Base Fig.070-07
ΔWB
Note that the change of the collector-emitter voltage causes the amount of charge in the
base to change slightly influencing the collector current.
CMOS Analog Circuit Design © P.E. Allen - 2005
Chapter 3 – Section 7 (8/3/05) Page 3.7-10
VBE3
VBE2
VBE1
VA vCE
Fig.070-08
Modified large signal model now becomes,
vCE vBE
iC = IS 1 + VA exp Vt
vBC B ≈ B
Cutoff Region Inverse Active Region
BE reverse biased BE reverse biased
BC reverse biased BC forward biased E E
Fig.080-01
Note: While the back-to-back diode model is appropriate here, it is not a suitable model
for the BJT in general because it does not model the current gain mechanism of the BJT.
Essentially, the back-to-back diode model has a very wide base region and all the injected
carriers from the emitter recombine in the base (F = 0).
Saturation Region
In the saturation region, both the base-emitter and base-collector pn junctions are forward
biased.
Consequently, there is injection of electrons into the base from both the emitter and
collector.
The carrier concentrations in saturation are:
;;
Carrier
Concentration
;; ;;
nnE pp(x)
;; ;;
np(0) nnC
;; ;;
Electrons np(x) iC
np(WB)
np1(x) pnC
pnE(0)
;; ;;
np2(x) Electrons
pnE
x
WB
Emitter Base Collector
Fig.080-02
3
Saturation 0.02mA
2
0.01mA
IB=0
Cutoff 1
VCE(V)
-8 -6 -4 -2 10 20 30 40
IB=0.01mA Cutoff BVCEO
-0.02
IB=0 0.02mA Saturation
-0.04
0.03mA
-0.06
0.04mA -0.08
Inverse
active -0.10 Fig.080-04
region
E E E E
npn pnp Fig.1.3-11
where VBE(on) 0.6 to 0.7V and VCE(sat) 0.2V
IE=1.5mA
1.5
iC
IE=1.0mA
1.0
IE VCB IE=0.5mA
0.5
IE=0
VCB(V)
Fig.080-08 0 20 40 60 80 100
BVCBO
As the collector-base voltage becomes large, the collector current can be written as,
iC = -FiEM
where
1
M= vCB n
1 - BVCBO
1 FM
iC = -(iE + iB) iC 1- FM = -iB iC = 1-FM iB
where,
1
M= vCB n
1 - BVCBO
Breakdown occurs when FM = 1.
Assuming that vCE vCB gives,
F BVCEO BVCBO
1/n
BVCEOn = 1 =
BVCBO F1- F1/n
1 - BVCBO
Note that BVCEO is less than BVCBO. For F = 100 and n = 4, BVCEO 0.5BVCBO.
CMOS Analog Circuit Design © P.E. Allen - 2005
Chapter 3 – Section 7 (8/3/05) Page 3.7-20
100
Region III: High current region where
F decreases as iC increases.
0 iC
0.1μA 1μA 10μA 100μA 1mA 10mA Fig.080-09
vBE iC ln βFM
exp Vt
ln βFL iB
where FM = the
vBEmaximum value of F.
iC = IS exp Vt
and iBX = ISX
Region I:
vBE Region
expmVt
;
;;;;;;
;;;
Carrier
Emitter Concentration
iC = IC + ic
ΔQh
; ;;;
;;;;;;
Depletion
iB = IB + ib Region Collector
Depletion
;
;;;;;;
;;;
vi Region
VCC np(0) = npo exp VBE+vbe
Vt ΔQe
;
;;;;;;
;;;
VBE IC+ic
np(0) = npo exp VBE
Vt
IC x
Emitter WB Collector
Base Fig.090-02
An increase in vBE (vi) causes more electrons to be injected in the base increasing the
base current iB by an amount ib. The increased base current causes the collector current
iC to increase by an amount ic.
vi ib ic
But
iC = IC +vic IC
vi 2 IC
vi 3 IC
ic IC Vt + 2
Vt + 6
Vt + ··· Vt vi = gmvi
diC | 1
VBE IC
go dvCE Q = IS VA
exp Vt VA
VA
ro = IC
Note that the small signal model is the same for either a npn or a pnp BJT.
Example:
Find the small signal input resistance, Rin, the output resistance, Rout, and the
voltage gain of the common emitter BJT if the BJT is unloaded (RL = ), vout/vin, the dc
collector current is 1mA, the Early voltage is 100V, and at room temperature.
IC 1mA 1 o
gm = Vt = 26mV = 26 mhos Rin = r = gm = 100·26 = 2.6k
VA 100V vout
Rout = ro = IC = 1mA = 100k vin = -gm ro = - 26mS·100k = -2600V/V
;; ;;;
Carrier Collector depletion
Concentration region widens due to a
change in vCE, ΔVCE
;; ;;;
Initial
Depletion
;; ;;;
Region
np(0) = npo exp vBE
Vt
;; ;;;
iC
iC+ΔiC
x
Emitter WB Collector
Base Fig.3.7-6
ΔWB
We noted that an increase in vCE causes and increase in the depletion width and a
decrease in the total minority-carrier charge stored in the base and therefore a decrease in
the base recombination current, iB1.
This influence is modeled by a collector-base resistor, rμ, defined as
vCE vCE iC iC
rμ = i1 = iC i1 = ro i1 oro (if base current is primarily recomb.)
In general, rμ 10 oro for the npn BJT and about 2-5 oro for the lateral pnp BJT.
CMOS Analog Circuit Design © P.E. Allen - 2005
Chapter 3 – Section 7 (8/3/05) Page 3.7-28
;;;;;;;;;
;;;;;;;
Carrier
Emitter Concentration
iC = IC + ic
ΔQh
;;;
;;;;;;;
Depletion
iB = IB + ib Region Collector
Depletion
; ;;;
vi Region
VCC np(0) = npo exp VBE+vbe
Vt ΔQe
; ;;;
;;;;;;
VBE IC+ic
np(0) = npo exp VBE
Vt
IC x
Emitter WB Collector
Base Fig.3.7-16
The vBE change causes a change in the minority carriers, Qe = qe, which must be
equal to the change in majority carriers, Qh = qh. This charge can be related to the
voltage across the base, vi, as
qh = Cbvi
where Cb is the base-charging capacitor and is given as
qh F ic IC
Cb = vi = vi = F gm = F Vt
WB2
The base transit time F is defined as 2Dn
CMOS Analog Circuit Design © P.E. Allen - 2005
n collector rc1
rc2
n+ buried layer
p- substrate
p+ p p- ni n- n n+ Metal Fig.3.7-18
Cμ rc
B rb B' C
+
Cπ rπ v1 gmv1 ro Ccs
-
rex
E E
Fig. 3.7-19
Example
Derive the complete small signal equivalent circuit for a BJT at IC = 1mA, VCB = 3V,
and VCS = 5V. The device parameters are Cje0 = 10fF, ne = 0.5, 0e = 0.9V, Cμ0 = 10fF,
nc = 0.3, 0c = 0.5V, Ccs0 = 20fF, ns = 0.3, 0s = 0.65V, o = 100, F = 10ps, VA = 20V,
rb = 300, rc = 50, rex = 5, and rμ = 10oro.
Solution
Because Cje is difficult to determine and usually an insignificant part of C, let us
approximate it as 2Cje0.
Cje = 20fF
Cμ0 10fF Ccs0 20F
Cμ = VCB = 3
0.3
= 5.6fF and Ccs = V =
CSns 5 0.3 = 10.5fF
n
e 1+
1+
1+
0c 0.5
1+
0s 0.65
IC 1mA
gm = Vt = 26mV = 38mA/V Cb = F gm = (10ps)(38mA/V) = 0.38pF
C = Cb + Cje = 0.38pF+0.02pF = 0.4pF
o VA 20V
r =gm =100·26=2.6k, ro= IC =1mA =20k, and rμ=10ro=10·100·20k =20M
Fig.3.7-20
1000
βo
100 -6dB/octave
10
1 ω (log scale)
ωβ 0.1ωT ωT
Fig.3.7-21
Note that the product of the magnitude and frequency at any point on the –6dB/octave
curve is equal to T.
For example,
0.1 T x10 = T
In measuring T, the value of |(j)| is measured at some frequency less than T (say
x) and T is calculated by taking the product of |(jx)| and x to get T.
CMOS Analog Circuit Design © P.E. Allen - 2005
Chapter 3 – Section 7 (8/3/05) Page 3.7-34
Current Dependence of fT
1 C Cμ Cb Cje Cμ Cje Cμ
Note that T = = gm + gm = gm + gm + gm = F + gm + gm
At low currents, the Cje and Cμ terms dominate causing T to rise and T to fall.
At high currents, T approaches F which is the maximum value of T.
For further increases in collector current, T decreases because of high-level injection
effects and the Kirk effect.
Typical frequency dependence of fT:
fT (GHz)
10
6
4
2
0 IC
10μA 100μA 1mA 10mA Fig.3.7-22
Add all internal noise sources to the BJT small signal model to get:
v2b = 4kTrb f
B rb B' C
* +
r C v gmv ro io
i2b = 2qIBf + K1 IB f - i2c = 2qICf
f
E Noise-free BJT E
where
vb2 = thermal noise of the base resistance
ib2 = base shot and flicker noise currents
and
ic2 = collector shot and flicker noise currents
CMOS Analog Circuit Design © P.E. Allen - 2005
Chapter 3 – Section 7 (8/3/05) Page 3.7-36
eeq2 =vi2
B rb B' C
*
vin ieq2 = ii2 rπ Cπ vπ ro io2
gmvπ
E Noise-free BJT E Fig. 3.7-25
r 2
sC
1 2
io2 = ic2 + gm2 1 ib 2 = ic2 + g m2 r 2srC+1 ib
2
r + sC
1 2
io2 = ic2 + ßo2 s ib2 = ic2 + |ß(j)|2 ib2
ß + 1
Circuit 2:
io2 = |ß(j)|2 ii2
Equating the above results gives
i2eq = i2i A
Hz
10-23 1/f
re
;;;
VG > VT VD < VDS(sat)
Consider the following illustration of a
VSB
;;;;;;;
MOSFET in the active region: B S
Depletion
Polysilicon
;;;;;;;
Region
p+ n+ v(y) n+
dy
y
0 L
p- substrate
Fig.3.8-1
Assume, the charge in the depletion region between the channel and bulk is no longer
constant and is dependent on v(y). Therefore, we model the dependence of threshold
voltage, VT, on y as
VT(y) = VT0 + 2|F| + vCB - 2F
where vCB is the voltage across the depletion region at y and is expressed as
vCB = vS + v(y) – vB = v(y) + vSB
VT(y) = VT0 + 2|F| + v(y) + vSB - 2F
CMOS Analog Circuit Design © P.E. Allen - 2005
Chapter 3 – Section 8 (8/3/05) Page 3.8-2
vDS 2
2
1.5
iDL = μnWC vGS-VT0+ 2|F|- 2
vDS-3 2|F| +vSB+vDS
+3 2|F|+vSB
1.5
ox
μnWCox
vDS 2
2
or iD = v v 1.5 1.5
L GS -V T0 + 2| |- - 2|
F 2
DS 3 F SB DS
|+v +v + 2| |+v
3 F SB
These results agree with the first edition of the text if the following definitions are made:
si
VBIN VT0 - 2|F| , 1 and 4CoxW 1 VBIN VT0 - 2|F|
CMOS Analog Circuit Design © P.E. Allen - 2005
Mobility Degradation
The degradation of the surface mobility μo can be written as
UCRIT·si UEXP
μs = μo Cox [vGS-VT-UTRA·vDS]
where
UCRIT = Critical field for mobility degradation (Volts/cm)
UTRA = Transverse field coefficient for mobility degradation
UEXP = Critical field exponent for mobility degradation
Normally, μs μo
;;;;
Corrected Bulk Threshold Parameter
;;;;;;;
;;;;;
Consider the following geometrical Polysilicon Gate Gate oxide
situation for short channels:
;;;;;;;
;;;;;
SourceXJ WS W XJ Drain
D
;;;;;
WS XJ+WS XJ+WD
Define the corrected bulk threshold WD
parameter as Bulk charge depleted
by the gate field
s = (1-S - D) Bulk/Substrate
Fig.3.8-2
where
XJ 2WS
S = 2L 1+ XJ - 1
XJ 2WD
D = 2L 1+ XJ - 1
where
XJ = metallurgical junction depth (meters)
2si
WS = source depletion width = q·NSUB (2F + |vSB|) )
2si
WD = Drain depletion width = q·NSUB (2F + |vSB| + vDS) )
and
vGS-VBIN s2 2 vGS-VBIN
vDS(sat) = + 22
1- 1+ 2
+ 2F + |vBS|
s
Other short channel effects not considered here:
• Saturation due to scattering-limited velocity
• Hot electron effects
BSIM2 Model
Generic composite expression for the model parameters:
LX WX
X = Xo + Leff + Weff
where
Xo = parameter for a given W and L
LX (WX) = first-order dependence of X on L (W)
Modeling features of BSIM2:
Mobility
• Mobility reduction by the vertical and the lateral field
Drain Current
• Velocity saturation
• Linear region drain current
• Saturation region drain current
• Subthreshold current
μoCoxWeff kT evGS-Vt-Voff
1 - eqVDS/kT
iDS = Leff ·
q
n ·
where
NB
Voff = VOF + VOFB ·vBS + VOFD ·vDS and n = NO + PHI - v + ND ·vDS
BS
CMOS Analog Circuit Design © P.E. Allen - 2005
5 6 7 8
Weff,2
1 2 3 4
Weff,1
Leff
Leff,1 Leff,2 Leff,3 Leff,4
• A long, wide device is used as the base to add geometry effects as corrections.
• Procedure:
1.) Oxide thickness and the differences between the drawn and effective channel
dimensions are provided as process input.
2.) A long, wide device is used to determine some base parameters which are used as
the starting point for each individual device extraction in the second phase.
3.) In the second phase, a set of parameters is extracted independently for each device.
This phase represents the fitting of the data for each independent device to the intrinsic
equation structure of the model
4.) In the third phase, the compiled parameters from the second phase are used to
determine the geometry parameters. This represents the imposition of the extrinsic
structure onto the model.
CMOS Analog Circuit Design © P.E. Allen - 2005
100μA
10μA iD +
vGS
1μA -
ID(M1)
100nA
10nA
1nA
100pA
0V 0.4V 0.8V 1.2V 1.6V 2V
VGS
BSIM3 Model
The background for the BSIM3 model and the equations are given in detail in the text
MOSFET Modeling & BSIM3 User’s Guide, by Y. Cheng and C. Hu, Kluwer Academic
Publishers, 1999.
The short channel effects included in the BSIM3 model are:
• Normal and reverse short-channel and narrow-width effects on the threshold.
• Channel length modulation (CLM).
• Drain induced barrier lowering (DIBL).
• Velocity saturation.
• Mobility degradation due to the vertical electric field.
• Impact ionization.
• Band-to-band tunnelling.
• Velocity overshoot.
• Self-heating.
1.) Channel quantization.
2.) Polysilicon depletion.
INTRODUCTION: This report contains the lot average results obtained by MOSIS from measurements of
MOSIS test structures on each wafer of this fabrication lot. SPICE parameters obtained from similar
measurements on a selected wafer are also attached.
COMMENTS: TSMC 0251P5M.
TRANSISTOR PARAMETERS W/L N-CHANNEL P-CHANNEL UNITS
MINIMUM 0.36/0.24
Vth 0.54 -0.50 volts
SHORT 20.0/0.24
Idss 557 -256 uA/um
Vth 0.56 -0.56 volts
Vpt 7.6 -7.2 volts
WIDE 20.0/0.24
Ids0 6.6 -1.5 pA/um
LARGE 50.0/50.0
Vth 0.47 -0.60 volts
Vjbkd 5.8 -7.0 volts
Ijlk -25.0 -1.1 pA
Gamma 0.44 0.61 V0.5
K’ (Uo*Cox/2) 112.0 -23.0 uA/V 2
x3
"Extraction" Methodology
Process
I-V characterisitcs Measurement
Simulators
Capacitances Methods
Transconductances
• Objective
Develop models having adjustable precision in ac and dc performance using table
lookup models.
• Advantages
Usable at any level – device, circuit, or behavioral
Quickly developed from experiment or process simulators
Faster than analytical device models (BSIM)
• Disadvantages
Requires approximately 10kbytes for a typical MOS model
Can’t be parameterized easily
CMOS Analog Circuit Design © P.E. Allen - 2005
Weff v
2
iD = K’
(v - V )v - DS
(1 + v ) (2)
Leff GS T DS 2 DS
where
VT = VT0 + [ 2|F| + vSB 2|F| ] (3)
vDS >VDSAT
Weak inversion
region 1/2
⎛ K ′ Weff ⎞
m= ⎜⎝ ⎟
2L eff ⎠
0 vGS
0 b′ =VT0 AppB-01
Comments:
• Stay away from the extreme regions of mobility degradation and weak inversion
• Use channel lengths greater than Lmin
These results indicate that the first (lowest value of VGS) data point is either bad, or at a
point where the transistor is in weak inversion. This data point will not be included in
subsequent analysis. Performing the linear regression yields the following results.
K'Weff
VT0 = 0.898 V 2
and 2Leff = 21.92 μA/V
vGS
VT0 VT1 VT2 VT3
FigAppB-02
By plotting VT versus x of Eq. (13) one can measure the slope of the best fit line from
which the parameter can be extracted. In order to do this, VT must be determined at
various values of vSB using the technique previously described.
VSB =0V
0.5 0.5
(vSB +2 φF ) − (2 φF ) FigAppB-03
vDS
AppB-03
CMOS Analog Circuit Design © P.E. Allen - 2005
Using the values of K’, VT , , and extracted previously, use an appropriate extraction
procedure to find the value of adjusting the values of K’, VT , and as needed.
Comments:
• We will assume that the bulk will be connected to the source or the standard
relationship between VT and VBS can be used.
• The saturation voltage is still given by
VDS( sat) = VGS - VT
†
Anurag Kaplish, “Parameter Optimization of Deep Submicron MOSFETS Using a Genetic Algorithm,” May 4, 2000, Special Project Report,
School of ECE, Georgia Tech.
CMOS Analog Circuit Design © P.E. Allen - 2005
Chapter 3 – Section 10 (8/3/05) Page 3.10-17