Akash Dayanand Hiremath

18BEC0361

1.

Ans: for VDD=1.3V

333.33
Width of PMOS in CMOS is 333.33nm And, W/L ratio= = 2.77
120
 Akash Dayanand Hiremath
18BEC0361

Full Adder(1bit adder) Schematic

 Akash Dayanand Hiremath
18BEC0361

Full Adder Symbol

 Akash Dayanand Hiremath
18BEC0361

Full Adder Simulation Schematic,

 Akash Dayanand Hiremath
18BEC0361

Output of Full Adder,

 Akash Dayanand Hiremath
18BEC0361

Sum Fall Delay:

Tpdf = (50.75-50.74402) ns = 5.98 ps
Sum Rise Delay:
Tpdr = (100.25-100.24962) ns = 0.38 ps
TOTAL PROPAGATION DELAY of Sum Ds= (Tpdf+ Tpdr)/2= (5.98+0.38)/2 = 3.18 ps

Carry Fall Delay:

Tpdf = (50.75-50.80656) ns = 56.56 ps
Carry Rise Delay:
Tpdr = (100.25-100.29831) ns = 48.31 ps
TOTAL PROPAGATION DELAY of Carry Dc= (Tpdf+ Tpdr)/2= (56.56+48.31)/2 = 52.435 ps

Therefore, TOTAL PROPAGATION DELAY = max(Ds,Dc) = 52.435 ps

And, Total Power dissipated = 285.6782 µW

 Akash Dayanand Hiremath
18BEC0361

2-bit Adder Schematic using Full Adder Symbol

 Akash Dayanand Hiremath
18BEC0361

Output of 2-bit Adder,

 Akash Dayanand Hiremath
18BEC0361

S0 Fall Delay:
Tpdf = (150.75-50.78066) ns = 30.66 ps
S0 Rise Delay:
Tpdr = (50.75-50.9019) ns = 151.9 ps
TOTAL PROPAGATION DELAY of Sum Ds0= (Tpdf+ Tpdr)/2= (30.66+151.9)/2 = 91.28 ps

S1 Fall Delay:
Tpdf = (50.75-50.766581) ns = 15.81 ps
S1 Rise Delay:
Tpdr = (100.25-100.45123) ns = 201.23 ps
TOTAL PROPAGATION DELAY of Sum Ds= (Tpdf+ Tpdr)/2= (15.81+201.23)/2 = 217.04 ps

Carry Fall Delay:

Tpdf = (50.75-50.83525) ns = 85.25 ps
Carry Rise Delay:
Tpdr = (100.25-100.35939) ns = 109.39 ps
TOTAL PROPAGATION DELAY of Carry Dc= (Tpdf+ Tpdr)/2= (85.25+109.39)/2 = 194.64 ps
 Akash Dayanand Hiremath
18BEC0361

Therefore, TOTAL PROPAGATION DELAY = max(Ds0,Ds1,Dc) = 217.04 ps

And, Total Power dissipated = 484.938 µW