You are on page 1of 62

A B C D E

WWW.AliSaler.Com

1 1

Compal Confidential
2 2

2014 S-series(400series) Rolo/Reeses/Raisinet


INTEL Sharkbay & Crescent bay ULT –U processor with DDR3L

3
Date : 2014/02/18 3

Version 0.5

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2011/06/29 Deciphered Date 2011/06/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.5
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B181P
Date: Tuesday, March 25, 2014 Sheet 1 of 62
A B C D E
A B C D E

CPU DC/DC
WWW.AliSaler.Com
Compal Confidential TPS51622ARSMR 50~51
Model Name : INPUTS OUTPUTS
Intel Broadwell U / Haswell Block Diagram B+ VCC_VORE

1
Project Name : SYSTEM DC/DC 1

eDP to LVDS Converter RT8243AZQW 47


LVDS Panel Conn. (RTD2136N) eDP
page19 page18
204pin DDRIII-SO-DIMM X2 INPUTS OUTPUTS
Memory Bus
page15, 16
B+ 3VDS/5VDS
1.35V DDR3L 1600MHz
DP to VGA Converter SYSTEM DC/DC
CRT Conn. (IT6513FN) DDI
page31 12/20 page31 RT8207MZQW 48
USB20
Right
USB20
Right
USB30
Left
USB30
Left Touch CMOS INPUTS OUTPUTS
FingerPrint
HDMI Conn. DDI Broadwell Camera 1.35V_VDDQ
page20
page25 page25 page25 page25 page19 page43 page19 B+
0.675VS
( Haswell )
USB2.0 SYSTEM DC/DC
2
AMD Topaz VGA
128Mx16 / 256Mx16
PCIEx4 USB3.0 SY8206DQNC 49 2
Option
DDR3 x4 VRAM
page33
SATA INPUTS OUTPUTS
B+ 1.05VS
WWAN / SSD
PCIeMini Card (Half)
SATA HDD 2.5" SATA ODD NGFF M2 Conn. WLAN & BT Combo SYSTEM DC/DC
Int. Speaker page21

AUDIO CODEC
page22 page22 page21
SY8003DFC 52
HD Audio
Audio Jack (Realtek ALC3227) INPUTS OUTPUTS
( HeadPhone, MIC)
PCIE x1 B+ 1.5VS
page26
Digital MIC x2 SYSTEM DC/DC
LAN(GbE) Card Reader
RT8880BGQW 54~55
Realtek RTL8161GSH-CG RT5237-GR
page23 page24 INPUTS OUTPUTS
3 3
Wifi on/off & B+ +VGA_CORE
Audio Mute / B
page4~14
page43

LPC Bus SPI SYS BIOS ROM SYSTEM DC/DC


Power/B
8MB page33
SY8003DFC 56
page29 12/20 page32
KBC
SMSC MEC1322-NU INPUTS OUTPUTS
Fan Control TPM
SLB9660TT1.2 B+ +1.8VS_VGA
page29 page30
PS/2 LPC Debug
Conn. page32

RTC CKT. Thermal Touch Pad Int.KBD Accelerometer SYSTEM DC/DC


page7 page43 page28 ST HP3DC2 CPU XDP
page6 page30
Conn. page6
SY8003DFC 57
DC/DC interface CKT. INPUTS OUTPUTS
4
PCH XDP 4
page40 Conn. page6 B+ +0.95VS_VGA
Power Circuit

page44~57
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/06/29 Deciphered Date 2011/06/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagrams
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom 0.5
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B181P
Date: Tuesday, March 25, 2014 Sheet 2 of 62
A B C D E
A B C D E

WWW.AliSaler.Com
@ is NO SMT part (empty) LVDS@ : Support LVDS panel. WWAN@ : For WWAN function. PX@ : GPU BOM config.
short@ : short pad , don't pop. eDP@ : Support eDP panel.
@EMI@,@ESD@,@RF@ : Reserve , don't pop.
RF@ : RF team request, must add.
1 EMI@ : EMI team request, must add. 1

ESD@ : ESD team request, must add.

+3VS
UCPU1
R=10K

F3 I2C_0_SCL
F2 I2C_0_SDA

+3VS

R=10K
2 2

F1 I2C_1_SCL
G4 I2C_1_SDA

TouchPad

<USB2.0 port>
CPU +3V_PCH +3VS
XDP
DESTINATION
USB2.0 port
CS
R=2.2K R=10K 0 USB 2.0(Right side)
AP2 SMBCLK PCH_SMBCLK
AH1 SMBDATA 2N7002 PCH_SMBDATA SO-DIMM A 1 USB 2.0(Right side)
2 USB 2.0(Left side)
+3V_PCH
3 WLAN/BT
R=1K
SO-DIMM B
4 Finger Print
AN1 SML0CLK WWAN
AK1 SML0DATA 5 (Option)
Touch
6 Camera
USB 2.0(Left side)
3 7 3
ACCELEROMETER

+3V_PCH
+3VGS
PX@
R=2.2K R=10K
AU3 SML1CLK
AH3 SML1DATA
<PCI-E,SATA,USB3.0>
2N7002 R=0ohm 2N7002 GPU
SML1CLK_R VGA_SMB_DA3
0x96 PX@ DESTINATION
SML1DATA_R VGA_SMB_CK3 PX@
Lane# PCI-E SATA USB3.0
@ R=0ohm CS
+3VDS 1 0 USB3.0
U17:+3VDS 2 1 USB3.0
R=10K 3 1 2 WWAN (M.2)
KBC_I2CLK 4 2 3 Card reader(PCI-E)
125
KBC_I2CDAT
126 5 3 10/100/1000 LAN
+3VDS
+3VS 6 4 WLAN (M.2)
7 GPU(DIS only)
+3VS +3VS
EC 88
89
PCH_KBC_I2CLK
PCH_KBC_I2CDAT
R=10K

2N7002
R=10K

Thermal Sensor
8
9
10
5
GPU(DIS only)
GPU(DIS only)
GPU(DIS only)
+3VDS
11 L3 3 2.5"HDD
12 L2 2 ODD
R=4.7K 6
4
111
I2C_MAIN_DAT 13 L1 1 4

112
I2C_MAIN_CLK R=100 BAT 14 L0 0 SSD(NGFF)

R=0 Charger

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2011/06/29 Deciphered Date 2011/06/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.5
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-B181P
Date: Tuesday, March 25, 2014 Sheet 3 of 62
A B C D E
5 4 3 2 1

WWW.AliSaler.Com UCPU1A HASWELL_MCP_E L CC97~CC102 must closed to connector not CPU

<20> PCH_DPB_N2 C54 C45 EDP_CPU_LANE_N0_C CC97 1 2 0.1U_0402_16V7K EDP_CPU_LANE_N0


DDI1_TXN0 EDP_TXN0 EDP_CPU_LANE_N0 <18>
<20> PCH_DPB_P2 C55 B46 EDP_CPU_LANE_P0_C CC98 1 2 0.1U_0402_16V7K EDP_CPU_LANE_P0
DDI1_TXP0 EDP_TXP0 EDP_CPU_LANE_P0 <18>
<20> PCH_DPB_N1 B58 A47 EDP_CPU_LANE_N0_1 CC99 1 2 0.1U_0402_16V7K EDP_CPU_LANE_N1 <eDP>
DDI1_TXN1 EDP_TXN1 EDP_CPU_LANE_N1 <18>
<HDMI> <20> PCH_DPB_P1 C58 B47 EDP_CPU_LANE_P0_1 CC1001 2 0.1U_0402_16V7K EDP_CPU_LANE_P1
DDI1_TXP1 EDP_TXP1 EDP_CPU_LANE_P1 <18>
D <20> PCH_DPB_N0 B55 D
A55 DDI1_TXN2 C47
<20> PCH_DPB_P0 DDI1_TXP2 EDP_TXN2
<20> PCH_DPB_N3 A57 C46
B57 DDI1_TXN3 EDP_TXP2 A49
<20> PCH_DPB_P3 DDI1_TXP3 DDI EDP EDP_TXN3 B49
C51 EDP_TXP3
<31> PCH_DPC_N0 DDI2_TXN0
<31> PCH_DPC_P0 C50 A45 EDP_CPU_AUX#_C CC1011 2 0.1U_0402_16V7K EDP_CPU_AUX#
DDI2_TXP0 EDP_AUXN EDP_CPU_AUX# <18>
<31> PCH_DPC_N1 C53 B45 EDP_CPU_AUX_C CC1021 2 0.1U_0402_16V7K EDP_CPU_AUX <eDP>
DDI2_TXN1 EDP_AUXP EDP_CPU_AUX <18>
<31> PCH_DPC_P1 B54
C49 DDI2_TXP1 D20 EDP_COMP
B50 DDI2_TXN2 EDP_RCOMP A43 RC1 1 @ 2 0_0402_5%
A53 DDI2_TXP2 EDP_DISP_UTIL
RC11 2 1 10K_0402_5% H_CPUPWRGD_R B53 DDI2_TXN3 RC2 1 @ 2 0_0402_5%
DDI2_TXP3 BKL_PWM_CPU <8,18>

+3V_PCH
COMPENSATION PU FOR eDP DG V0.9 PEG_COMP
1 OF 19 +VCCIOA_OUT L Trace width=20mil and spacing=25mil

1
+VCCIO_OUT RC234 EDP_COMP 2 1
Max length=100mil
@ 10K_0402_5% 24.9_0402_1% RC3
HASWELL_MCP_E
UCPU1B

2
1

C RC4 PROC_DETECT# D61 C


62_0402_5% PAD T51 @ K61 PROC_DETECT MISC
N62 CATERR J62 XDP_PRDY#
<32> H_PECI PECI PRDY XDP_PRDY# <6>
K62 XDP_PREQ#
XDP_PREQ# <6>
2

PREQ E60 XDP_TCK0


PROC_TCK XDP_TCK0 <6>
E61 XDP_TMS_CPU
JTAG PROC_TMS XDP_TMS_CPU <6>
<50> KBC_PROC_HOT# KBC_PROC_HOT# RC6 1 2 56_0402_5% KBC_PROC_HOT#_R K63 E59 XDP_TRST#_CPU
PROCHOT PROC_TRST XDP_TRST#_CPU <6>
THERMAL F63 XDP_TDI_CPU
PROC_TDI XDP_TDI_CPU <6> +1.05VS_VCCST
C32 1 2 47P_0402_50V8J F62 XDP_TDO_CPU
PROC_TDO XDP_TDO_CPU <6>
1

<32> KBC_PROC_HOT 2 <6,11> +1.05VS_PG RC7 1 @ 2 1K_0402_1% H_CPUPWRGD_R C61


G PROCPWRGD PWR
S QC9 <6> H_CPUPWRGD_R J60 XDP_OBS0_R XDP_TDI_CPU RC12 2 @ 1 51_0402_1%
XDP_OBS0_R <6>
3

BPM#0 H60 XDP_OBS1_R


2N7002KW_SOT323-3 BPM#1 XDP_OBS1_R <6>
H61 XDP_OBS2_R T52 @ PAD XDP_PREQ# RC13 2 @ 1 51_0402_1%
BPM#2 H62 XDP_OBS3_R T53 @ PAD
SM_RCOMP0 AU60 BPM#3 K59 XDP_OBS4_R T54 @ PAD XDP_TMS_CPU RC17 2 @ 1 51_0402_1%
SM_RCOMP1 AV60 SM_RCOMP0 DDR3
BPM#4 H63 XDP_OBS5_R T55 @ PAD
SM_RCOMP2 AU61 SM_RCOMP1 BPM#5 K60 XDP_OBS6_R T56 @ PAD
DDR3_DRAMRST# AV15 SM_RCOMP2 BPM#6 J61 XDP_OBS7_R T57 @ PAD
DDR_PG_CNTL AV61 SM_DRAMRST BPM#7
L DG V0.5 Trace width=12~15 mil SM_PG_CNTL1
Max length=500mil
2 OF 19
DDR3 COMPENSATION SIGNALS
B B
200_0402_1% 2 1 RC18 SM_RCOMP0

120_0402_1% 2 1 RC19 SM_RCOMP1

100_0402_1% 2 1 RC20 SM_RCOMP2 +1.35V_VDDQ


+1.35V_VDDQ
1

RC308
470_0402_5%
UC10
5 1
2

DDR3_DRAMRST# VCC NC
DDR3_DRAMRST# <15,16>
1 2 DDR_PG_CNTL
4 A
<15,48> SM_PG_CTRL Y
@ CC88 3
GND
0.1U_0402_16V7K
2 74AUP1G07GW_TSSOP5

A A

Security Classification Compal Secret Data


Issued Date 2011/06/29 Deciphered Date 2011/06/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDI,MSIC,XDP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.5
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B181P
Date: Tuesday, March 25, 2014 Sheet 4 of 62
5 4 3 2 1

Compal Electronics, Inc.


5 4 3 2 1

WWW.AliSaler.Com
<15> DDR_A_D[0..63] <16> DDR_B_D[0..63]

HASWELL_MCP_E
UCPU1D

UCPU1C HASWELL_MCP_E <DDR3L>


<DDR3L>
DDR_B_D0 AY31 AM38
SB_DQ0 SB_CK#0 M_CLK_DDR#2 <16>
DDR_A_D0 AH63 AU37 DDR_B_D1 AW31 AN38
D SA_DQ0 SA_CLK#0 M_CLK_DDR#0 <15> SB_DQ1 SB_CK0 M_CLK_DDR2 <16> D
DDR_A_D1 AH62 AV37 DDR_B_D2 AY29 AK38
SA_DQ1 SA_CLK0 M_CLK_DDR0 <15> SB_DQ2 SB_CK#1 M_CLK_DDR#3 <16>
DDR_A_D2 AK63 AW36 DDR_B_D3 AW29 AL38
SA_DQ2 SA_CLK#1 M_CLK_DDR#1 <15> SB_DQ3 SB_CK1 M_CLK_DDR3 <16>
DDR_A_D3 AK62 AY36 DDR_B_D4 AV31
SA_DQ3 SA_CLK1 M_CLK_DDR1 <15> SB_DQ4
DDR_A_D4 AH61 DDR_B_D5 AU31 AY49
SA_DQ4 SB_DQ5 SB_CKE0 DDR_CKE0_DIMMB <16>
DDR_A_D5 AH60 AU43 DDR_B_D6 AV29 AU50
SA_DQ5 SA_CKE0 DDR_CKE0_DIMMA <15> SB_DQ6 SB_CKE1 DDR_CKE1_DIMMB <16>
DDR_A_D6 AK61 AW43 DDR_B_D7 AU29 AW49
SA_DQ6 SA_CKE1 DDR_CKE1_DIMMA <15> SB_DQ7 SB_CKE2
DDR_A_D7 AK60 AY42 DDR_B_D8 AY27 AV50
DDR_A_D8 AM63 SA_DQ7 SA_CKE2 AY43 DDR_B_D9 AW27 SB_DQ8 SB_CKE3
DDR_A_D9 AM62 SA_DQ8 SA_CKE3 DDR_B_D10 AY25 SB_DQ9 AM32
SA_DQ9 SB_DQ10 SB_CS#0 DDR_CS0_DIMMB# <16>
DDR_A_D10 AP63 AP33 DDR_B_D11 AW25 AK32
SA_DQ10 SA_CS#0 DDR_CS0_DIMMA# <15> SB_DQ11 SB_CS#1 DDR_CS1_DIMMB# <16>
DDR_A_D11 AP62 AR32 DDR_B_D12 AV27
SA_DQ11 SA_CS#1 DDR_CS1_DIMMA# <15> SB_DQ12
DDR_A_D12 AM61 DDR_B_D13 AU27 AL32
DDR_A_D13 AM60 SA_DQ12 AP32 DDR_B_D14 AV25 SB_DQ13 SB_ODT0
DDR_A_D14 AP61 SA_DQ13 SA_ODT0 DDR_B_D15 AU25 SB_DQ14 AM35
SA_DQ14 SB_DQ15 SB_RAS DDR_B_RAS# <16>
DDR_A_D15 AP60 AY34 DDR_B_D16 AM29 AK35
SA_DQ15 SA_RAS DDR_A_RAS# <15> SB_DQ16 SB_WE DDR_B_WE# <16>
DDR_A_D16 AP58 AW34 DDR_B_D17 AK29 AM33
SA_DQ16 SA_WE DDR_A_WE# <15> SB_DQ17 SB_CAS DDR_B_CAS# <16>
DDR_A_D17 AR58 AU34 DDR_B_D18 AL28
SA_DQ17 SA_CAS DDR_A_CAS# <15> SB_DQ18
DDR_A_D18 AM57 DDR_B_D19 AK28 AL35
SA_DQ18 SB_DQ19 SB_BA0 DDR_B_BS0 <16>
DDR_A_D19 AK57 AU35 DDR_B_D20 AR29 AM36
SA_DQ19 SA_BA0 DDR_A_BS0 <15> SB_DQ20 SB_BA1 DDR_B_BS1 <16>
DDR_A_D20 AL58 AV35 DDR_B_D21 AN29 AU49
SA_DQ20 SA_BA1 DDR_A_BS1 <15> SB_DQ21 SB_BA2 DDR_B_BS2 <16>
DDR_A_D21 AK58 AY41 DDR_B_D22 AR28
SA_DQ21 SA_BA2 DDR_A_BS2 <15> SB_DQ22 DDR_B_MA[0..15] <16>
DDR_A_D22 AR57 DDR_B_D23 AP28 AP40 DDR_B_MA0
SA_DQ22 DDR_A_MA[0..15] <15> SB_DQ23 SB_MA0
DDR_A_D23 AN57 AU36 DDR_A_MA0 DDR_B_D24 AN26 AR40 DDR_B_MA1
DDR_A_D24 AP55 SA_DQ23 SA_MA0 AY37 DDR_A_MA1 DDR_B_D25 AR26 SB_DQ24 SB_MA1 AP42 DDR_B_MA2
DDR_A_D25 AR55 SA_DQ24 SA_MA1 AR38 DDR_A_MA2 DDR_B_D26 AR25 SB_DQ25 SB_MA2 AR42 DDR_B_MA3
DDR_A_D26 AM54 SA_DQ25 SA_MA2 AP36 DDR_A_MA3 DDR_B_D27 AP25 SB_DQ26 SB_MA3 AR45 DDR_B_MA4
DDR_A_D27 AK54 SA_DQ26 SA_MA3 AU39 DDR_A_MA4 DDR_B_D28 AK26 SB_DQ27 SB_MA4 AP45 DDR_B_MA5
DDR_A_D28 AL55 SA_DQ27 SA_MA4 AR36 DDR_A_MA5 DDR_B_D29 AM26 SB_DQ28 SB_MA5 AW46 DDR_B_MA6
C C
DDR_A_D29 AK55 SA_DQ28 SA_MA5 AV40 DDR_A_MA6 DDR_B_D30 AK25 SB_DQ29 SB_MA6 AY46 DDR_B_MA7
DDR_A_D30 AR54 SA_DQ29 SA_MA6 AW39 DDR_A_MA7 DDR_B_D31 AL25 SB_DQ30 SB_MA7 AY47 DDR_B_MA8
DDR_A_D31 AN54 SA_DQ30 SA_MA7 AY39 DDR_A_MA8 DDR_B_D32 AY23 SB_DQ31 DDR CHANNEL B SB_MA8 AU46 DDR_B_MA9
DDR_A_D32 AY58 SA_DQ31 SA_MA8 AU40 DDR_A_MA9 DDR_B_D33 AW23 SB_DQ32 SB_MA9 AK36 DDR_B_MA10
DDR_A_D33 AW58 SA_DQ32 SA_MA9 AP35 DDR_A_MA10 DDR_B_D34 AY21 SB_DQ33 SB_MA10 AV47 DDR_B_MA11
DDR_A_D34 AY56 SA_DQ33 SA_MA10 AW41 DDR_A_MA11 DDR_B_D35 AW21 SB_DQ34 SB_MA11 AU47 DDR_B_MA12
DDR_A_D35 AW56 SA_DQ34 SA_MA11 AU41 DDR_A_MA12 DDR_B_D36 AV23 SB_DQ35 SB_MA12 AK33 DDR_B_MA13
DDR_A_D36 AV58 SA_DQ35 DDR CHANNEL A SA_MA12 AR35 DDR_A_MA13 DDR_B_D37 AU23 SB_DQ36 SB_MA13 AR46 DDR_B_MA14
DDR_A_D37 AU58 SA_DQ36 SA_MA13 AV42 DDR_A_MA14 DDR_B_D38 AV21 SB_DQ37 SB_MA14 AP46 DDR_B_MA15
DDR_A_D38 AV56 SA_DQ37 SA_MA14 AU42 DDR_A_MA15 DDR_B_D39 AU21 SB_DQ38 SB_MA15
SA_DQ38 SA_MA15 SB_DQ39 DDR_B_DQS#[0..7] <16>
DDR_A_D39 AU56 DDR_B_D40 AY19 AW30 DDR_B_DQS#0
SA_DQ39 DDR_A_DQS#[0..7] <15> SB_DQ40 SB_DQSN0
DDR_A_D40 AY54 AJ61 DDR_A_DQS#0 DDR_B_D41 AW19 AV26 DDR_B_DQS#1
DDR_A_D41 AW54 SA_DQ40 SA_DQSN0 AN62 DDR_A_DQS#1 DDR_B_D42 AY17 SB_DQ41 SB_DQSN1 AN28 DDR_B_DQS#2
DDR_A_D42 AY52 SA_DQ41 SA_DQSN1 AM58 DDR_A_DQS#2 DDR_B_D43 AW17 SB_DQ42 SB_DQSN2 AN25 DDR_B_DQS#3
DDR_A_D43 AW52 SA_DQ42 SA_DQSN2 AM55 DDR_A_DQS#3 DDR_B_D44 AV19 SB_DQ43 SB_DQSN3 AW22 DDR_B_DQS#4
DDR_A_D44 AV54 SA_DQ43 SA_DQSN3 AV57 DDR_A_DQS#4 DDR_B_D45 AU19 SB_DQ44 SB_DQSN4 AV18 DDR_B_DQS#5
DDR_A_D45 AU54 SA_DQ44 SA_DQSN4 AV53 DDR_A_DQS#5 DDR_B_D46 AV17 SB_DQ45 SB_DQSN5 AN21 DDR_B_DQS#6
DDR_A_D46 AV52 SA_DQ45 SA_DQSN5 AL43 DDR_A_DQS#6 DDR_B_D47 AU17 SB_DQ46 SB_DQSN6 AN18 DDR_B_DQS#7
DDR_A_D47 AU52 SA_DQ46 SA_DQSN6 AL48 DDR_A_DQS#7 DDR_B_D48 AR21 SB_DQ47 SB_DQSN7
SA_DQ47 SA_DQSN7 SB_DQ48 DDR_B_DQS[0..7] <16>
DDR_A_D48 AK40 DDR_B_D49 AR22 AV30 DDR_B_DQS0
SA_DQ48 DDR_A_DQS[0..7] <15> SB_DQ49 SB_DQSP0
DDR_A_D49 AK42 AJ62 DDR_A_DQS0 DDR_B_D50 AL21 AW26 DDR_B_DQS1
DDR_A_D50 AM43 SA_DQ49 SA_DQSP0 AN61 DDR_A_DQS1 DDR_B_D51 AM22 SB_DQ50 SB_DQSP1 AM28 DDR_B_DQS2
DDR_A_D51 AM45 SA_DQ50 SA_DQSP1 AN58 DDR_A_DQS2 DDR_B_D52 AN22 SB_DQ51 SB_DQSP2 AM25 DDR_B_DQS3
DDR_A_D52 AK45 SA_DQ51 SA_DQSP2 AN55 DDR_A_DQS3 DDR_B_D53 AP21 SB_DQ52 SB_DQSP3 AV22 DDR_B_DQS4
DDR_A_D53 AK43 SA_DQ52 SA_DQSP3 AW57 DDR_A_DQS4 DDR_B_D54 AK21 SB_DQ53 SB_DQSP4 AW18 DDR_B_DQS5
DDR_A_D54 AM40 SA_DQ53 SA_DQSP4 AW53 DDR_A_DQS5 DDR_B_D55 AK22 SB_DQ54 SB_DQSP5 AM21 DDR_B_DQS6
DDR_A_D55 AM42 SA_DQ54 SA_DQSP5 AL42 DDR_A_DQS6 DDR_B_D56 AN20 SB_DQ55 SB_DQSP6 AM18 DDR_B_DQS7
B
DDR_A_D56 AM46 SA_DQ55 SA_DQSP6 AL49 DDR_A_DQS7 DDR_B_D57 AR20 SB_DQ56 SB_DQSP7 B
DDR_A_D57 AK46 SA_DQ56 SA_DQSP7 DDR_B_D58 AK18 SB_DQ57
DDR_A_D58 AM49 SA_DQ57 AP49 +V_SM_VREF_CNT DDR_B_D59 AL18 SB_DQ58
SA_DQ58 SM_VREF_CA +V_SM_VREF_CNT SB_DQ59
DDR_A_D59 AK49 AR51 +V_DDR_REFA_R +V_DDR_REFA_R DDR_B_D60 AK20
DDR_A_D60 AM48 SA_DQ59 SM_VREF_DQ0 AP51 +V_DDR_REFB_R DDR_B_D61 AM20 SB_DQ60
SA_DQ60 SM_VREF_DQ1 +V_DDR_REFB_R SB_DQ61
DDR_A_D61 AK48 DDR_B_D62 AR18
DDR_A_D62 AM51 SA_DQ61 DDR_B_D63 AP18 SB_DQ62
DDR_A_D63 AK51 SA_DQ62 SB_DQ63
SA_DQ63

4 OF 19

3 OF 19

A A

Security Classification Compal Secret Data


2011/06/29 2011/06/29 Title
Issued Date Deciphered Date DDRIII
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.5
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B181P
Date: Tuesday, March 25, 2014 Sheet 5 of 62
5 4 3 2 1

Compal Electronics, Inc.


5 4 3 2 1

WWW.AliSaler.Com
*
INTVRMEN
H:Integrated VRM enable 1
1
RC31
2
10M_0402_5%
PCH_RTCX1

PCH_RTCX2 RTC BAT conn

1
+RTCVCC L:Integrated VRM disable +RTCVCC
CC2 JCMOS1 +RTCBATT_R +RTCBATT JRTC1
1U_0402_6.3V6K SHORT PADS
CMOS +RTCVCC
YC1

2
330K_0402_5% 1 2 RC236 PCH_INTVRMEN 2 1 2 1K_0402_5% +3VS
1 2 PCH_RTCRST#
PCH_RTCRST# <8> RC33
RC32 20K_0402_5% 1 32.768KHZ Q13FC1350000500
1 DC1 15mils 15mils
1 2 PCH_SRTCRST# CC3 CC4 15mils 2 2 1 1 2 mSATA_DET# RC219 1 2 43K_0402_5%
RC34 20K_0402_5% 18P_0402_50V8J 1 + -
1

1
18P_0402_50V8J 1 3 +3VDS NMI_SMI_DBG# RC327 1 2 10K_0402_5%
CC5 JME1 2 2 CC6
1U_0402_6.3V6K SHORT PADS
ME CMOS 1U_0402_6.3V6K BAV70W 3P C/C_SOT-323

2
2 NMI_SMI_DBG# mSATA_DET#
2 LOTES_AAA-BAT-054-K01

2
CONN@
D PLT_RST# @ D
<32,44> BAT_GRNLED# 1
+RTCVCC

C124
0.1U_0402_10V6K
RC225
@ESD@ 10K_0402_5%
2

5
+3V_PCH
QC8A QC8B

1
2
G

1
HASWELL_MCP_E
UCPU1E

1
2 1 1 6 4 3 HDA_SDOUT RC35
S

D
RC374 1K_0402_5% RC36 1M_0402_5%
MESS84DW-G_SC88-6 MESS84DW-G_SC88-6 1M_0402_5% PCH_RTCX1 AW5
PCH_RTCX2 AY5 RTCX1 +3VS

2
SM_INTRUDER# AU6 RTCX2 J5 SATA_PRX_DTX_N0 <22> VBIOS ID TALBE

2
PCH_INTVRMEN AV7 INTRUDER SATA_RN0/PERN6_L3 H5
INTVRMEN SATA_RP0/PERP6_L3 SATA_PRX_DTX_P0 <22>

2
PCH_SRTCRST# AV6 RTC B15 2.5" SSD/HDD
SRTCRST SATA_TN0/PETN6_L3 SATA_PTX_DRX_N0 <22>

1
D PCH_RTCRST# AU7 A15 RC218
RTCRST SATA_TP0/PETP6_L3 SATA_PTX_DRX_P0 <22>
<21> WWAN_DET# 2 Q89 UMA@ 10K_0402_5%
G 2N7002KW_SOT323-3 J8 SATA_PRX_DTX_N1 <22>
SATA_RN1/PERN6_L2 H8
S SATA_PRX_DTX_P1 <22>

1
SATA_RP1/PERP6_L2 A17
SATA_TN1/PETN6_L2 B17
SATA_PTX_DRX_N1 <22> ODD AMD_VBIOS_SEL0
SATA_TP1/PETP6_L2 SATA_PTX_DRX_P1 <22>

1
HDA_BIT_CLK AW8 J6
HDA_SYNC AV11 HDA_BCLK/I2S0_SCLK SATA_RN2/PERN6_L1 H6 10/24 Add VBIOS select RC220
HDA_RST# AU8 HDA_SYNC/I2S0_SFRM SATA_RP2/PERP6_L1 B14 PX@ 100K_0402_5%
HDA_SDI0 AY10 HDA_RST/I2S_MCLK SATA_TN2/PETN6_L1 C15
<26> HDA_SDI0 HDA_SDI0/I2S0_RXD AUDIO SATA_TP2/PETP6_L1
AU12 GPIO35 GPIO34

2
HDA_SYNC_R R11 1 short@ 2 0_0402_5% HDA_SYNC HDA_SDOUT AU11 HDA_SDI1/I2S1_RXD F5 (SEL1) (SEL0)
HDA_SDO/I2S0_TXD SATA_RN3/PERN6_L0 SATA_PRX_DTX_N3 <21>
AW10 E5 0 0 VBIOS1
DOCKEN/I2S1_TXD SATA SATA_RP3/PERP6_L0 SATA_PRX_DTX_P3 <21>
AV10 C17 WWAN (M.2 slot)
HDA_DOCK_RST/I2S1_SFRM SATA_TN3/PETN6_L0 SATA_PTX_DRX_N3 <21>
AY8 D17 0 1 VBIOS2 11/28
I2S1_SCLK SATA_TP3/PETP6_L0 SATA_PTX_DRX_P3 <21>
+3VS
1 0 VBIOS3
V1 AMD_VBIOS_SEL0
SATA0GP/GPIO34 U1 AMD_VBIOS_SEL1
SATA1GP/GPIO35 1 1 UMA

2
V6 NMI_SMI_DBG# NMI_SMI_DBG# <32>
CM28 SATA2GP/GPIO36
@ AC1 mSATA_DET# mSATA_DET# <21> RC217
1 2 HDA_BITCLK_AUDIO PCH_JTAG_RST# AU62 SATA3GP/GPIO37 UMA@ 10K_0402_5%
PCH_JTAG_TCK AE62 PCH_TRST A12
PCH_TCK SATA_IREF +1.05VS_VCCSATA3PLL
PCH_JTAG_TDI AD61 L11 RC39 <Page 12>

1
22P_0402_50V8J +5VS PCH_JTAG_TDO AE61 PCH_TDI TP7 K10 3K_0402_1%
11/28 PCH_JTAG_TMS AD62 PCH_TDO TP8 C12 SATA_COMP 1 2 AMD_VBIOS_SEL1
C @
CM29
PAD T156 AL11 PCH_TMS
JTAG
SATA_RCOMP U3 SATA_ACT# L DG V0.9 SATA_COMP C
TP5 SATALED SATA_ACT# <7,43>
1

1
1 2 HDA_RST_AUDIO# AC4 Width=12mil
XDP_TCK_JTAGX AE63 TP6 RC221
10K_0402_5% PAD T157 AV2 JTAGX Max length=500mil PX@ 100K_0402_5%
22P_0402_50V8J RC222 RSVD
2

2
RP1
<26> HDA_BITCLK_AUDIO HDA_BITCLK_AUDIO 1 8 HDA_BIT_CLK
2
G

<26> HDA_RST_AUDIO# HDA_RST_AUDIO# 2 7 HDA_RST# 5 OF 19


<26> HDA_SYNC_AUDIO 3 6 HDA_SYNC_R
<26> HDA_SDOUT_AUDIO 4 5 HDA_SDOUT_Q 3 1 HDA_SDOUT
33_0804_8P4R_5% +3VS
S

RC240 @ @ CC86
QC11 PWR_GD 2 1 1 2
2N7002KW_SOT323-3
10K_0402_5% +VCCIO_OUT +VCCIO_OUT
XDP@ UC5 .1U_0402_16V7K
2 16 +VCCIO_OUT JXDP1
1OE VCC 1 2
XDP_TDO_CPU 3 4 XDP_TDO XDP_PREQ# 3 GND0 GND1 4 CFG17
<4> XDP_TDO_CPU 1A 1B <4> XDP_PREQ# OBSFN_A0 OBSFN_C0 CFG17 <14>

0.1U_0402_16V4Z

2.2U_0402_6.3V6M
<CPU site> <4> XDP_PRDY# XDP_PRDY# 5 6 CFG16
+1.05VS_VCCST 5 7 OBSFN_A1 OBSFN_C1 8 CFG16 <14>
2OE 1 1 GND2 GND3
CFG0 9 10 CFG8
<14> CFG0 OBSDATA_A0 OBSDATA_C0 CFG8 <14>

CC125

CC126
XDP_TDI_CPU 6 7 XDP_TDI_SWITCH CFG1 11 12 CFG9
<4> XDP_TDI_CPU 2A 2B <14> CFG1 OBSDATA_A1 OBSDATA_C1 CFG9 <14>
RC283 1 2 51_0402_1% PCH_JTAG_TDO 13 14
12 2 2 CFG2 15 GND4 GND5 16 CFG10
1 2 51_0402_1% 3OE <14> CFG2 17 OBSDATA_A2 OBSDATA_C2 18 CFG10 <14>
RC41 @ PCH_JTAG_TDI CFG3 CFG11
<14> CFG3 OBSDATA_A3 OBSDATA_C3 CFG11 <14>
12/20
<4> XDP_TMS_CPU XDP_TMS_CPU 11 10 XDP_TMS 19 20
RC45 1 @ 2 51_0402_1% PCH_JTAG_TMS 3A 3B XDP_OBS0_R 21 GND6 GND7 22 CFG19
<4> XDP_OBS0_R OBSFN_B0 OBSFN_D0 CFG19 <14>
15 XDP_OBS1_R 23 24 CFG18
4OE <4> XDP_OBS1_R OBSFN_B1 OBSFN_D1 CFG18 <14>
RC46 1 @ 2 51_0402_1% XDP_TCK_JTAGX Place near JXDP1 25 26
XDP_TRST#_CPU 14 13 XDP_TRST# CFG4 27 GND8 GND9 28 CFG12
<4> XDP_TRST#_CPU 4A 4B <14> CFG4 OBSDATA_B0 OBSDATA_D0 CFG12 <14>
CFG5 29 30 CFG13
<14> CFG5 OBSDATA_B1 OBSDATA_D1 CFG13 <14>
1 31 32
NC CFG6 33 GND10 GND11 34 CFG14
<14> CFG6 OBSDATA_B2 OBSDATA_D2 CFG14 <14>
8 9 CFG7 35 36 CFG15
GND NC <14> CFG7 37 OBSDATA_B3 OBSDATA_D3 38 CFG15 <14>
RC17 need to close to JCPU1 GND12 GND13
XDP_TRST#_CPU RC37 1 @ 2 0_0402_5% PCH_JTAG_RST# <PCH site> <4> H_CPUPWRGD_R H_CPUPWRGD_R RC371 1 2 1K_0402_1% H_CPUPWRGD_XDP 39 40 CLK_CPU_ITP <7>
74CBTLV3126DS_SSOP16 41 PWRGOOD/HOOK0 ITPCLK/HOOK4 42
<XDP> <8,32> ON/OFFBTN#
43 HOOK1 ITPCLK#/HOOK5 44
CLK_CPU_ITP# <7>
B 45 VCC_OBS_AB VCC_OBS_CD 46 XDP_RST#_R RC3732 1K_0402_1%
1 B
<11> CPU_PWR_DEBUG HOOK2 RESET#/HOOK6 PLT_RST# <8,21,23,30,32,33,43>
47 48 XDP_DBRESET#
+1.05VS_VCCST <8,32> PM_PWROK HOOK3 DBR#/HOOK7 XDP_DBRESET# <8>
49 50
51 GND14 GND15 52 XDP_TDO
<7,15,16,43> PCH_SMBDATA SDA TD0
53 54 XDP_TRST#
<7,15,16,43> PCH_SMBCLK SCL TRST#

1
<XDP> XDP_TMS RC201 1 short@ 2 0_0402_5% PCH_JTAG_TMS <PCH site> XDP_TCK1 55 56 XDP_TDI
+3V_PCH XDP_TCK0 57 TCK1 TDI 58 XDP_TMS
R511 59 TCK0 TMS 60 2 1 CFG3
U16 GND16 GND17 RC372 1K_0402_1%
10K_0402_5%
1 5 SAMTE_BSH-030-01-L-D-A CONN@

2
NC VCC
<CPU> PWR_GD 2
<8,32,41> PWR_GD A 4 +1.05VS_PG <4,11>
3 Y
PCH_JTAG_TDO RC307 1 @ 2 0_0402_5% XDP_TDI GND
<PCH site> <XDP> 74AUP1G07GW_TSSOP5 <CPU,XDP,XDP Switch>

XDP_TDI RC200 1 short@ 2 0_0402_5% XDP_TDI_SWITCH


<EC output>
<XDP>

<PCH site> PCH_JTAG_TDI RC195 1 short@ 2 0_0402_5% XDP_TDI


Resistors Resistors
Topolog Description Be st Use for Stuffed ufStuffed
XDP_TDO RC194 1 short@ 2 0_0402_5% PCH_JTAG_TDO
<PCH site>
<XDP> Default Setting: Dual In this topology, the - Run control oper. R1d,R2,R3d, J1s, J2s,
TCK S can Chains CPU JTAG chain will be - ME/Sx debug R4,R5,J1d J3s
PCH_JTAG_TCK RC38 1 @ 2 51_0402_5%
XDP_TRST#_CPU RC16 2 @ 1 51_0402_1% (also known as controlled by TCK0 and J2d,J3d* R6,R7,R8,R9
XDP_TCK0 RC15 2 1 51_0402_1%
"Shared JTAG" in TCK1 will control J4d and Rs5*
other docum ent) the PCH JTAG chain.
XDP_TCK:XDP contact with CPU No 0ohm(RS5)

A
In th is topolog y, PCH -B oundary Scan/ J1s,J2s,J3s** R1d,r3d,J1d,J2d A
PCH_JTAG_TCK RC196 1 short@ 2 0_0402_5% XDP_TCK1 +1.05VS_VCCST Single TCK scan chain TDI- TDO and CPU TDI-TDO Manufacturing est R2,R4,R5,R5s** J3d**,J4d,
<PCH site>
(also known as "Com m on will be chained to form
R6,R7,R8,R9
JTAG" in other docum one JTAG scan chain
XDP_TDO_CPU RC10 2 1 51_0402_1%
PCH_JTAG_TCK RC197 1 @ 2 0_0402_5% XDP_TCK0 ent) controlled by TCK0
XDP_TCK0 <4> <CPU and XDP>
+1.05VS_VCCST
<PCH site> XDP_TCK_JTAGX RC193 1 short@ 2 0_0402_5%
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/06/29 Deciphered Date 2011/06/29 Title
<XDP> XDP_TDO RC14 2 @ 1 51_0402_1%
<PCH site> XDP_TCK_JTAGX RC306 1 @ 2 0_0402_5% XDP_TDO
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
RTC,SATA,HDA,JTAG
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.5
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B181P
Date: Tuesday, March 25, 2014 Sheet 6 of 62
5 4 3 2 1
5 4 3 2 1

WWW.AliSaler.Com
CPU_XTAL24_IN

CPU_XTAL24_OUT
HASWELL_MCP_E 2 1
UCPU1F
1M_0402_5% RC48

3 1
C43 A25 CPU_XTAL24_IN 3 1
C42 CLKOUT_PCIE_N0 XTAL24_IN B25 CPU_XTAL24_OUT GND GND
CLKOUT_PCIE_P0 XTAL24_OUT 1 1
CR_RST#_D U2 CC9 CC10
<43> CR_RST#_D PCIECLKRQ0/GPIO18 4 2
K21 RC52 18P_0402_50V8J
RC310 1 short@ 2 0_0402_5% PCIE_CR# B41 TP15 M21 3K_0402_1% 18P_0402_50V8J YC2
D <43> CLK_PCIE_CR# CLKOUT_PCIE_N1 TP16 2 2 D
PCIE Card reader RC311 1 short@ 2 0_0402_5% PCIE_CR A41 C26 PCH_CLK_BIASREF 1 2 +1.05VS_AXCK_LCPLL <Page12> 24MHZ 12PF 20PPM X3G024000DC1H
<43> CLK_PCIE_CR CLKOUT_PCIE_P1 DIFFCLK_BIASREF
<43> CR_CLKREQ# CR_CLKREQ# Y5
PCIECLKRQ1/GPIO19 C35 TESTLOW1 RPH15 4 5 10K_0804_8P4R_5%
RC49 1 short@ 2 0_0402_5% PCIE_LAN# C41 CLOCK TP19 C34 TESTLOW2 3 6
<23> CLK_PCIE_LAN# CLKOUT_PCIE_N2 SIGNALS TP20
PCIE LAN RC50 1 short@ 2 0_0402_5% PCIE_LAN B42 AK8 TESTLOW3 2 7
<23> CLK_PCIE_LAN CLKOUT_PCIE_P2 TP21
LAN_CLKREQ#_P AD1 AL8 TESTLOW4 1 8 <EC>
<9> LAN_CLKREQ#_P PCIECLKRQ2/GPIO20 TP22
RC55 1 short@ 2 0_0402_5% PCIE_MINI1# B38 AN15 CLK_PCI0 EMI@ RC61 1 2 22_0402_5% CLK_PCI_KBC
<21> CLK_PCIE_MINI1# CLKOUT_PCIE_N3 CLKOUT_LPC_0 CLK_PCI_KBC <32>
WLAN RC57 1 short@ 2 0_0402_5% PCIE_MINI1 C37 AP15 CLK_PCI1 EMI@ RC63 1 2 22_0402_5% CLK_PCI_DEBUG CLK_PCI_DEBUG <32>
<21> CLK_PCIE_MINI1 CLKOUT_PCIE_P3 CLKOUT_LPC_1
MINI1_CLKREQ#_P N1 EMI@ RC62 1 2 22_0402_5% CLK_PCI_TPM
PCIECLKRQ3/GPIO21 CLK_PCI_TPM <30> 11/28
B35 CLK_CPU_ITP# <LPC Debug>
CLKOUT_ITPXDP CLK_CPU_ITP# <6>
GPU CLK_PEG_VGA# A39 A35 CLK_CPU_ITP
<33> CLK_PEG_VGA# CLKOUT_PCIE_N4 CLKOUT_ITPXDP_P CLK_CPU_ITP <6>
CLK_PEG_VGA B39 <XDP CLK reserve TP>
<33> CLK_PEG_VGA CLKOUT_PCIE_P4
GPU_CLKREQ#_P U5
PCIECLKRQ4/GPIO22
B37
A37 CLKOUT_PCIE_N5
+3VS PCIECLKREQ5# T2 CLKOUT_PCIE_P5 +3V_PCH
RPH11 PCIECLKRQ5/GPIO23 @RF@
CM30
4 5
GPS_XMIT_OFF# <9,21>
3 6 SATA_ACT# 6 OF 19 1 2 CLK_PCI_KBC
SATA_ACT# <6,43>
2 7 CR_CLKREQ#
1 8 GPU_CLKREQ#_P
22P_0402_50V8J SML0CLK 1K_0402_5% 1 2 RC72
HASWELL_MCP_E
10K_0804_8P4R_5% UCPU1G @RF@
CM31
SML0DATA 1K_0402_5% 1 2 RC73
+3VS LPC_LAD0 AU14 AN2 PCH_GPIO11 1 2 CLK_PCI_DEBUG
<30,32> LPC_LAD0 LAD0 SMBALERT/GPIO11 PCH_GPIO11 <9>
RPH12 LPC_LAD1 AW12 AP2 SMBCLK RP2
<30,32> LPC_LAD1 LAD1 LPC SMBCLK
4 5 CR_RST#_D LPC_LAD2 AY12 AH1 SMBDATA SML1DATA 1 8
<30,32> LPC_LAD2 LAD2 SMBUS SMBDATA 22P_0402_50V8J
C 3 6 PCIECLKREQ5# LPC_LAD3 AW11 AL2 PCH_DDR_RST SMBDATA 2 7 C
<30,32> LPC_LAD3 LAD3 SML0ALERT/GPIO60
2 7 SIRQ SIRQ <9,30,32> LPC_LFRAME# AV12 AN1 SML0CLK @RF@ SML1CLK 3 6
<30,32> LPC_LFRAME# LFRAME SML0CLK CM33
1 8 MINI1_CLKREQ#_P AK1 SML0DATA SMBCLK 4 5
SML0DATA AU4 THERMAL_ALERT# 1 2 PCH_SPI_CLK_R
10K_0804_8P4R_5% SML1ALERT/PCHHOT/GPIO73 AU3 SML1CLK 2.2K_0804_8P4R_5%
SML1CLK/GPIO75 AH3 SML1DATA PCH_DDR_RST R162 1 2 1K_0402_5%
PCH_SPI_CLK AA3 SML1DATA/GPIO74 22P_0402_50V8J
PCH_SPI_CS0# Y7 SPI_CLK AF2
Y4 SPI_CS0 CL_CLK AD2
AC2 SPI_CS1 SPI C-LINK CL_DATA AF4
PCH_SPI_SI AA2 SPI_CS2 CL_RST +3VS +3VS
PCH_SPI_SO AA4 SPI_MOSI
PCH_SPI_SIO2 Y6 SPI_MISO
PCH_SPI_SIO3 AF1 SPI_IO2
SPI_IO3 +3V_PCH

2
10/17 Add RC293
RC78 RC79
RPH19 THERMAL_ALERT# RC293 1 2 10K_0402_5% 10K_0402_5% 10K_0402_5%
PCH_SPI_CS0# 8 1 PCH_SPI_CS0#_R 7 OF 19
PCH_SPI_CS0#_R <32>

2
PCH_SPI_SO 7 2 PCH_SPI_SO_R QC2A ME2N7002D1KW-G 2N_SOT363-6
PCH_SPI_SO_R <32>

1
PCH_SPI_SI 6 3 PCH_SPI_SI_R
PCH_SPI_SI_R <32>
PCH_SPI_SIO3 5 4 PCH_SPI_HOLD# SMBCLK 6 1

PCH
PCH_SPI_HOLD# <32> KBC PCH_SMBCLK <6,15,16,43>
15_0804_8P4R_5%
+3VS

5
PCH_SPI_CLK RC368 1 2 15_0402_5% PCH_SPI_CLK_R ME2N7002D1KW-G 2N_SOT363-6
PCH_SPI_CLK_R <32>
PCH_SPI_SIO2 RC370 1 2 15_0402_5% PCH_SPI_WP# QC2B
PCH_SPI_WP# <32>
SMBDATA 3 4
PCH_SMBDATA <6,15,16,43>

2
RC81 RC80
B B
10K_0402_5% 10K_0402_5%
2
QC10A

1
PCH_KBC_I2CLK 6 1 THERMAL_SMBCLK
+3V_PCH
ME2N7002D1KW-G 2N_SOT363-65 RC192 2 1 0_0402_5%
PCH_KBC_I2CLK <30,32,34>
PCH_KBC_I2CDAT QC10B3 4 THERMAL_SMBDATA

ME2N7002D1KW-G 2N_SOT363-6 RC198 2 1 0_0402_5%


PCH_KBC_I2CDAT <30,32,34>

2
ME2N7002D1KW-G 2N_SOT363-6

CPU THERMAL SENSOR SML1CLK 1 6 SML1CLK_R RC202 2 @ 1 0_0402_5%


KBC_I2CLK <32>

5
+3VS QC6A

SML1DATA 4 3 SML1DATA_R RC199 2 @ 1 0_0402_5%


KBC_I2CDAT <32>
CC14 2 @ 1 0.1U_0402_16V4Z
ME2N7002D1KW-G 2N_SOT363-6
QC6B
1 UC3
1

C 1 8 THERMAL_SMBCLK
QC7 2 CC15 VDD SCL RC105 2 110K_0402_5% +3VS RC177
MMBT3904W_SOT323-3 B 2200P_0402_50V7K H_THERMDA 2 7 THERMAL_SMBDATA LAN_CLKREQ#_P 1 short@ 2 LAN_CLKREQ#
2 D+ SDA LAN_CLKREQ# <23>
E
3

H_THERMDC 3 6 THERM_SCI# 0_0402_5%


D- ALERT# THERM_SCI# <9>
A +3VS 1 2 CPU_THERM# 4 5 RC184 RC190 A
RC96 33K_0402_5% T_CRIT# GND MINI1_CLKREQ#_P 1 short@ 2 GPU_CLKREQ#_P 1 short@ 2 GPU_CLKREQ#
MINI1_CLKREQ# <21> GPU_CLKREQ# <34>
NCT7718W_MSOP8 0_0402_5% 0_0402_5%
<29> CPU_THERM#
Address:1001100xb (x is R/W bit)
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/06/29 Deciphered Date 2011/06/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CLK,SPI,SMB,LPC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.5
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B181P
Date: Tuesday, March 25, 2014 Sheet 7 of 62
5 4 3 2 1
5 4 3 2 1

WWW.AliSaler.Com
PM_APWROK

1
PWR_GD

1
T83
PAD
RC268

RC269
1 short@

1 @
2 0_0402_5%

2 0_0402_5%
PM_SLP_S0#_R

SLP_S3#
BT_OFF

1 DSWODVREN - On Die DSW VR Enable


+RTCVCC

C121
0.1U_0402_10V6K

C128
0.1U_0402_10V6K

C127
0.1U_0402_10V6K
@ESD@ @ESD@ Non Deep S3 RC91-->SMT ESD@ H:Enable DSWODVREN RC254 2 1 330K_0402_5%
2 2
Deep S3 RC93-->SMT
HASWELL_MCP_E 2
*
<9> SYS_RESET# UCPU1H L:Disable DSWODVREN RC255 2 1 330K_0402_5%
@
SYSTEM POWER MANAGEMENT

SUSWARN#_R R131 1 short@ 2 0_0402_5% SUSACK# AK2 AW7 DSWODVREN


R133 1 short@ 2 0_0402_5% SYS_RESET# AC3 SUSACK DSWVRMEN AV5 PCH_DPWROK_R
<6> XDP_DBRESET# SYS_RESET DPWROK
<6,32> PM_PWROK PM_PWROK AG2 AJ5 PCH_PCIE_WAKE#
AY7 SYS_PWROK WAKE PCH_PCIE_WAKE# <21,32>
PM_APWROK 11/07
<6,32,41> PWR_GD PWR_GD
RC182 1 short@ 2 0_0402_5% PM_APWROK_R AB5 PCH_PWROK
RC100 1 @ 2 0_0402_5% PLT_RST#_PCH AG7 APWROK V5 PM_CLKRUN#
<32> PM_APWROK PLTRST CLKRUN/GPIO32 PM_CLKRUN# <32> +3V_DSW_P
1 AG4 BT_OFF <21>
D SUS_STAT/GPIO61 D
C129
0.1U_0402_10V6K

AE6 SUSCLK_KBC <32>


@ESD@ SUSCLK/GPIO62 AP5 SLP_S5# T142 PAD
PM_RSMRST# AW6 SLP_S5/GPIO63 PCH_PCIE_WAKE# RC98 1 2 1K_0402_5%
2 <32> PM_RSMRST# RSMRST
Deep S3 <32> SUS_PWR_ACK short@ RC104 1 2 0_0402_5% SUSWARN#_R AV4
short@ RC103 1 2 0_0402_5% ON/OFFBTN#_R AL7 SUSWARN/SUSPWRDNACK/GPIO30 AJ6 SLP_S4#
<6,32> ON/OFFBTN# PWRBTN SLP_S4 SLP_S4# <25,32,40,43,48>
<32,34> AC_PRES_OUT AC_PRES_OUT AJ8 AT4 SLP_S3#
AN4 ACPRESENT/GPIO31 SLP_S3 AL5 SLP_S3# <26,32,35,40,41,49,52>
<32> BATLOW# BATLOW# SIO_SLP_A#
BATLOW/GPIO72 SLP_A SIO_SLP_A# <32>
PM_SLP_S0#_R AF3 AP4
PAD T151 PCH_SLP_WLAN# AM5 SLP_S0 SLP_SUS AJ7 RC286 1 short@ 2 0_0402_5% SLP_SUS#
SLP_WLAN/GPIO29 SLP_LAN SLP_SUS# <32> 11/07

SUSWARN#_R
<9> SUSWARN#_R
SUS_PWR_ACK Non Deep S3 RC286-->@
8 OF 19 Deep S3 RC286-->SMT +3VDS
+3VDS
+3VLP
1

1
C114
0.1U_0402_10V6K

@ESD@ RC112 2 1 100K_0402_5% PM_PWROK


100K_0402_5%

1
2 RC133 U18 RC130
PCH_DPWROK_R RC316 1 short@ 2 0_0402_5% DPWROK 1 5 10K_0402_5%

2
NC VCC
PM_RSMRST# RC330 1 @ 2 0_0402_5% DPWROK 2
<47> 3V_PG

2
A 4 DPWROK
3 Y
GND
1
PM_PWROK 74AUP1G07GW_TSSOP5
CC103
0.1U_0402_16V7K
+3V_PCH 2
1
C123
0.1U_0402_10V6K

@ESD@ JME2
1
2 SLP_S3# 2 1 Pinout on customer's board,
2
+3VDS 3
3
as in the PDG, CDI #514849
SLP_S5# 4
SLP_S4# 5 4
SIO_SLP_A# 6 5 Pin Pin
7 6
C 8 7 1 VccSus3_3 10 GND C
PCH_RTCRST# 9 8
<6> PCH_RTCRST#
10 9 2 SLP_S3# 11 PWRBTN#
ON/OFFBTN# 11 10
12 11 3 VccDSW3_3 12 GND
SYS_RESET# 13 12
14 13 4 SLP_S5# 13 SYS_RESET#
PAD T143 15 14
16 15 5 SLP_S4# 14 GND
17 16
18 17 6 SLP_A# 15 SLP_S0#
18
7 +3.3DS 16 NC
19 8 GND 17 NC
20 GND
GND
E-T_6718K-Y18N-21L
9 RTCRST# 14 NC
CONN@

+3V_DSW_P

HASWELL_MCP_E
UCPU1I BATLOW# RC102 1 2 10K_0402_5%
AC_PRES_OUT RC101 1 2 10K_0402_5%
PANEL_BKEN_CPU PD 100K on Page20

short@ RC114 1 2 0_0402_5% BKL_PWM_CPU_R B8 B9 PCH_DDPB_CLK


<4,18> BKL_PWM_CPU EDP_BKLCTL DDPB_CTRLCLK PCH_DDPB_CLK <20> +3VS
short@ RC115 1 2 0_0402_5% ENBKL_CPU A9 C9 PCH_DDPB_DAT <HDMI>
<18> ENBKL EDP_BKLEN eDP SIDEBAND DDPB_CTRLDATA PCH_DDPB_DAT <20>
ENVDD_CPU RC116 1 2 0_0402_5% ENVDD_CPU_R C6 D9 R165 1 2 2.2K_0402_5%
<19> ENVDD_CPU EDP_VDDEN DDPC_CTRLCLK D11
short@ R164 1 2 2.2K_0402_5%
+3VS
DDPC_CTRLDATA PM_CLKRUN# RC110 2 1 8.2K_0402_5%

BRD_ID2 U6 ACCEL_INT_R# RC111 2 1 10K_0402_5%


+3VS BRD_ID3 P4 PIRQA/GPIO77 C5
BRD_ID4 N4 PIRQB/GPIO78 DISPLAY DDPB_AUXN B6 DDI1_AUX_DN
PIRQC/GPIO79 DDPC_AUXN DDI1_AUX_DN <31>
HDD_HALTLED N2 B5
<43> HDD_HALTLED PIRQD/GPIO80 DDPB_AUXP
5

AD4 A6 DDI1_AUX_DP
B PME GPIO DDPC_AUXP DDI1_AUX_DP <31> B
Q86B ME2N7002D1KW-G 2N_SOT363-6
<30> ACCEL_INT# 3 4 ACCEL_INT_R# U7
MUX_SELECT# L1 GPIO55
DGPU_PWR_EN L3 GPIO52 C8
<35> DGPU_PWR_EN
LPC_RESET# R5 GPIO54 DDPB_HPD A8
PCH_DDPB_HPD <20> <HDMI>
<32> LPC_RESET# GPIO51 DDPC_HPD DDI1_HPD <31>
CAMERA_ON L4 D6
<19> CAMERA_ON GPIO53 EDP_HPD EDP_HPD <18>
<eDP HPD>

RC120 1 2 100K_0402_5% ENVDD_CPU R627 9 OF 19


DGPU_PWR_EN 1 @ 2 VGA_EN
VGA_EN <35,54>
0_0402_5%
0.1

+3VS +3VS +3VS +3VS


0.2
+3VS 0.3
1

1
0.4
RC314 RC113 RC118 RC124
RC125 2 1 10K_0402_5% DGPU_PWR_EN 1 @ 2 10K_0402_5% @ 8.2K_0402_5% @ 8.2K_0402_5% @ 8.2K_0402_5%
RC300 0_0402_5%
2

2
RPH22 4 5 +3VS
3 6 BRD_ID1 BRD_ID2 BRD_ID3 BRD_ID4
BRD_ID1 <9>
2 7 mSATA_DEVSLP1 mSATA_DEVSLP1 <9,21>
1 8 CAMERA_ON 0.5
5

1
10K_0804_8P4R_5% UC9
1 PLT_RST#_PCH <CPU> RC132 RC117 RC119 RC122
P

RC127 2 1 10K_0402_5% LPC_RESET# PLT_RST# 4 IN1 @ 10K_0402_5%


<6,21,23,30,32,33,43> PLT_RST# O 8.2K_0402_5% 8.2K_0402_5% 8.2K_0402_5%
2
IN2
G

RC128 2 1 10K_0402_5% MUX_SELECT#


2

2
SN74AHC1G08DCKR_SC70-5
3

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2011/06/29 Deciphered Date 2011/06/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PM,GPIO,DDI
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.5
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B181P
Date: Tuesday, March 25, 2014 Sheet 8 of 62
5 4 3 2 1
5 4 3 2 1

+1.05VS_VCCST
WWW.AliSaler.Com

1
HASWELL_MCP_E
UCPU1J RC242
1K_0402_5%

short@ RC129

2
0_0402_5%
PCH_GPIO76 P1 D60 H_THERMTRIP#_C 1 2 H_THEMTRIP#
WWAN_TRANSMIT_OFF#AU2 BMBUSY/GPIO76 THRMTRIP V4 GPS_XMIT_OFF#
<21> WWAN_TRANSMIT_OFF# GPIO8 RCIN/GPIO82 GPS_XMIT_OFF# <7,21>
PCH_GPIO12 AM7 T4 SIRQ SIRQ <7,30,32> DG V0.9 PCH_OPIRCOMP
TLS_ENcrytion AD6 LAN_PHY_PWR_CTRL/GPIO12 CPU/ SERIRQ AW15PCH_OPIRCOMP RC131 2 1 49.9_0402_1%
<28> KBL_DET# GPIO15 OPI_COMP2
KBL_DET# Y1 MISC AF20 Width=12mil,spacing=12mil
D DGPU_PWROK RC123 1 short@ 2 0_0402_5% PCH_GPIO17
LAN_PWR_EN
T3
AD5
GPIO16
GPIO17
RSVD
RSVD
AB21 L Max length=500mil D

EC_PME# AN5 GPIO24


<23> EC_PME# GPIO27
NFC_RST# AD7
NFC_INT AN3 GPIO28
GPIO26 R6 BRD_ID1 BRD_ID1 <8>
Boot BIOS Strap
WLAN_TRANSMIT_OFF#AG6 GSPI0_CS/GPIO83 L6 GSPI0_CLK
<21> WLAN_TRANSMIT_OFF# GPIO56 GSPI0_CLK/GPIO84 PCH_GPIO86 Boot BIOS Location
CR_PWREN# AP1 N6 GSPI0_MISO
<43> CR_PWREN# GPIO57 GSPI0_MISO/GPIO85
PCH_GPIO58 AL4 L8 BBS_BIT0 0 SPI
<21> WWANSSD_M2
WWANSSD_M2 AT5 GPIO58
GPIO59 GPIO
GSPI0_MOSI/GPIO86
GSPI1_CS/GPIO87
R7 GSPI1_CS# +3VS *
PCH_GPIO44 AK4 L5 GSPI1_CLK
GPIO44 GSPI1_CLK/GPIO88

2
PCH_GPIO47 AB6 N7 GSPI1_MISO
U4 GPIO47 GSPI1_MISO/GPIO89 K2 GSPI1_MOSI RC270
<43> FPR_LOCK# GPIO48 GSPI_MOSI/GPIO90
DGPU_PRSNT# Y3 J1 PLT_ID1 PX@ 10K_0402_5%
RC121 1 short@ 2 0_0402_5% PCH_GPIO50 P3 GPIO49 UART0_RXD/GPIO91 K3 PLT_ID2
<33> DGPU_HOLD_RST# GPIO50 UART0_TXD/GPIO92 PLT_ID2 <19,32>
MPHY_PWREN Y2 J2 PLT_ID3 PLT_ID3 <19>
<40> MPHY_PWREN

1
PCH_GPIO13 AT3 HSIOPC/GPIO71 LPIO UART0_RTS/GPIO93 G1 TOUCH_RST#
<10> PCH_GPIO13 GPIO13 UART0_CTS/GPIO94 TOUCH_RST# <19>
PCH_GPIO14 AH4 K4 SG_IN
PCH_GPIO25 AM4 GPIO14 UART1_RXD/GPIO0 G2 DOCKID1
GPIO25 UART1_TXD/GPIO1

2
WWAN_CONFIG_1 AG5 J3 SC_PWRSV#
WWAN_CONFIG_2 AG3 GPIO45 UART1_RST/GPIO2 J4 ODD_DA# RC271
GPIO46 UART1_CTS/GPIO3 ODD_DA# <22>
F2 PCH_GPIO4 UMA@ 10K_0402_5%
+3V_PCH PCH_GPIO9 AM3 I2C0_SDA/GPIO4 F3 TOUCH_DET#
GPIO9 I2C0_SCL/GPIO5 TOUCH_DET# <19>
PCH_GPIO10 AM2 G4 EC_SCI# EC_SCI# <32>

1
HDD_DEVSLP0 P2 GPIO10 I2C1_SDA/GPIO6 F1 THERM_SCI#
<22> HDD_DEVSLP0 DEVSLP0/GPIO33 I2C1_SCL/GPIO7 THERM_SCI# <7>
1

NFC_DWL_REQ C4 E3 SDIO_CLK T179 PAD


R125 mSATA_DEVSLP1 L2 SDIO_POWER_EN/GPIO70 SDIO_CLK/GPIO64 F4 FPR_OFF
<8,21> mSATA_DEVSLP1 DEVSLP1/GPIO38 SDIO_CMD/GPIO65 FPR_OFF <43>
10K_0402_5% OCP_OC# N5 D3 SDIO_D0 T184 PAD
HDA_SPKR V2 DEVSLP2/GPIO39 SDIO_D0/GPIO66 E4 SDIO_D1 T182 PAD
<26> HDA_SPKR SPKR/GPIO81 SDIO_D1/GPIO67
C C3 ODD_EN C
ODD_EN <22>
2

WWAN_TRANSMIT_OFF# SDIO_D2/GPIO68 E2 SDIO_D3 T183 PAD


SDIO_D3/GPIO69
RC278 DGPU_HOLD_RST# 10 OF 19
1 2 FPR_LOCK#
1
10K_0402_5% 11/28 CC127
@ 2.2U_0402_6.3V6M
+3VDS
2
+3V_PCH RC325 1 2 10K_0402_5% PCH_GPIO12
RC267 1 2 10K_0402_5% PCH_GPIO25 OCP_OC#
RC326 1 2 10K_0402_5% EC_PME# +3VS

RPH17 4 5

6
3 6 NFC_RST# Q86A
2 7 SUSWARN#_R TOUCH_RST# RC274 1 2 10K_0402_5%
SUSWARN#_R <8>
1 8 ME2N7002D1KW-G 2N_SOT363-6 DOCKID1 RC284 1 2 10K_0402_5%
10K_0804_8P4R_5% <32> OCP_PWM_OUT 2 SC_PWRSV# RC287 1 2 10K_0402_5%
ODD_DA# RC289 1 2 10K_0402_5%
RPH18 4 5 LED_LINK_LAN#_R PCH_GPIO4 RC290 1 2 10K_0402_5%
LED_LINK_LAN#_R <10,23>

1
3 6 PCH_GPIO58 TOUCH_DET# RC291 1 2 10K_0402_5%
2 7 EC_SCI# RC292 1 2 10K_0402_5%
1 8 PCH_GPIO44 +3VS SDIO_CLK RC299 1 2 10K_0402_5%
10K_0804_8P4R_5% FPR_OFF RC305 1 2 10K_0402_5%
SDIO_D1 RC309 1 2 10K_0402_5%
RPH20 4 5 NFC_INT SDIO_D3 RC312 1 2 10K_0402_5%
3 6 PCH_GPIO11 PCH_GPIO76 RC126 1 2 10K_0402_5%
PCH_GPIO11 <7>

5
2 7 PCH_GPIO10 U4107 @ GSPI0_CLK RC315 1 2 10K_0402_5%
B 1 8 PCH_GPIO9 2 GSPI0_MISO RC317 1 2 10K_0402_5% B

P
<54,56> 1.8V_PWRGD B
10K_0804_8P4R_5% 4 DGPU_PWROK GSPI1_CS# RC318 1 2 10K_0402_5%
Y DGPU_PWROK <34>
CR_PWREN# 1 GSPI1_CLK RC319 1 2 10K_0402_5%
<33,54> VGA_PWRGD A
G
RC99 1 2 1K_0402_5% TLS_ENcrytion GSPI1_MISO RC320 1 2 10K_0402_5%
GSPI1_MOSI RC321 1 2 10K_0402_5%
3

RC295 1 2 10K_0402_5% WLAN_TRANSMIT_OFF# 1 RC5


C116
0.1U_0402_10V6K

RC297 1 2 10K_0402_5% CR_PWREN# MC74VHC1G08DFT2G_SC70-5 1 PX@ 2 DGPU_PWROK


<33,54> GPU_PGD
RC298 1 2 10K_0402_5% WWANSSD_M2 @ESD@
RC322 1 2 10K_0402_5% LAN_PWR_EN 0_0402_5%
RC323 1 2 10K_0402_5% WWAN_CONFIG_1 2
RC324 1 2 10K_0402_5% WWAN_CONFIG_2

+3V_PCH
RPH14 +3VS
4 5
3 6 PCH_GPIO47 PCH Strap Platform ID +3VS

1
2 7 PCH_GPIO14 @
1 8 RC243 12/20
1K_0402_5%
10K_0804_8P4R_5% PLT_ID1 RC266 1 2 10K_0402_5%
+3VS PLT_ID2 RC272 1 2 10K_0402_5%

2
RPH13 Boot BIOS Strap Bit (BBS) GSPI0_MOSI/GPIO86 BBS_BIT0 PLT_ID3 RC273 1 2 10K_0402_5%
4 5 LAN_CLKREQ#_P
LAN_CLKREQ#_P <7> * SPI 0

1
3 6 SYS_RESET# <8> PLT_ID1 RC275 1 @ 2 10K_0402_5%
2 7 KBL_DET# RC244 PLT_ID2 RC276 1 @ 2 10K_0402_5%
LPC 1
1 8 PCH_GPIO50 1K_0402_5% PLT_ID3 RC277 1 @ 2 10K_0402_5%
10K_0804_8P4R_5%

2
RC215 1 2 10K_0402_5% PCH_GPIO17
A A

RC216 1 2 10K_0402_5% ODD_EN


RC224 1 2 10K_0402_5% MPHY_PWREN RC377 1 @ 2 10K_0402_5%

RC214 1 2 10K_0402_5% OCP_OC#


RC279 1 2 10K_0402_5% HDD_DEVSLP0 Security Classification Compal Secret Data
RC313 1 2 10K_0402_5% NFC_DWL_REQ 2011/06/29 2011/06/29 Title
Issued Date Deciphered Date
RC375 1 UMA@ 2 10K_0402_5% DGPU_PRSNT# RC376 1 PX@ 2 10K_0402_5%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
GPIO,UART,I2C
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
11/28 Custom 0.5
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B181P
Date: Tuesday, March 25, 2014 Sheet 9 of 62
5 4 3 2 1
5 4 3 2 1

WWW.AliSaler.Com
HASWELL_MCP_E
UCPU1K

PEG_GTX_C_HRX_N7 F10 AN8


D <33> PEG_GTX_C_HRX_N7 PERN5_L0 USB2N0 USB20_N0 <25> D
PEG_GTX_C_HRX_P7 E10 AM8 USB2.0
<33> PEG_GTX_C_HRX_P7 PERP5_L0 USB2P0 USB20_P0 <25>
0.1U_0402_16V7K PX@ 1 2 CC90 PEG_HTX_GRX_N7 C23 AR7
<33> PEG_HTX_C_GRX_N7 PETN5_L0 USB2N1 USB20_N1 <25>
0.1U_0402_16V7K PX@ 1 2 CC91 PEG_HTX_GRX_P7 C22 AT7 USB2.0/USB3.0
<33> PEG_HTX_C_GRX_P7 PETP5_L0 USB2P1 USB20_P1 <25>
PEG_GTX_C_HRX_N8 F8 AR8
<33> PEG_GTX_C_HRX_N8 PERN5_L1 USB2N2 USB20_N2 <25>
PEG_GTX_C_HRX_P8 E8 AP8 USB2.0/USB3.0
<33> PEG_GTX_C_HRX_P8 PERP5_L1 USB2P2 USB20_P2 <25>
GPU <33> PEG_HTX_C_GRX_N8
0.1U_0402_16V7K PX@ 1 2 CC89 PEG_HTX_GRX_N8 B23 AR10
USB20_N3 <21> WWAN
0.1U_0402_16V7K PX@ 1 2 CC92 PEG_HTX_GRX_P8 A23 PETN5_L1 USB2N3 AT10
<33> PEG_HTX_C_GRX_P8 PETP5_L1 USB2P3 USB20_P3 <21> WLAN/BT (NGFF)
PEG_GTX_C_HRX_N9 H10 AM15 R138 1 2 0_0402_5%
<33> PEG_GTX_C_HRX_N9 PERN5_L2 USB2N4 USB20_N4 <43> USB20_N5_WWAN <21>
PEG_GTX_C_HRX_P9 G10 AL15 FP R139 1 2 0_0402_5%
<33> PEG_GTX_C_HRX_P9 PERP5_L2 USB2P4 USB20_P4 <43> USB20_P5_WWAN <21>
0.1U_0402_16V7K PX@ 1 2 CC93 PEG_HTX_GRX_N9 B21 AM13 USB20_N5 R128 1 TS@ 2 0_0402_5%
<33> PEG_HTX_C_GRX_N9 PETN5_L2 USB2N5 USB20_N5_TS <19>
0.1U_0402_16V7K PX@ 1 2 CC94 PEG_HTX_GRX_P9 C21 AN13 USB20_P5 R129 1 TS@ 2 0_0402_5%
<33> PEG_HTX_C_GRX_P9 PETP5_L2 USB2P5 USB20_P5_TS <19>
PEG_GTX_C_HRX_N10 E6 AP11 Touch
<33> PEG_GTX_C_HRX_N10 PERN5_L3 USB2N6 USB20_N6 <19>
PEG_GTX_C_HRX_P10 F6 AN11 Camera
<33> PEG_GTX_C_HRX_P10 PERP5_L3 USB2P6 USB20_P6 <19>
0.1U_0402_16V7K PX@ 1 2 CC95 PEG_HTX_GRX_N10 B22 AR13
<33> PEG_HTX_C_GRX_N10 PETN5_L3 USB2N7 USB20_N7 <25>
0.1U_0402_16V7K PX@ 1 2 CC96 PEG_HTX_GRX_P10 A21 AP13 USB2.0
<33> PEG_HTX_C_GRX_P10 PETP5_L3 USB2P7 USB20_P7 <25>

<23> PCIE_PRX_DTX_N3 PCIE_PRX_DTX_N3 G11


C PERN3 C
<23> PCIE_PRX_DTX_P3 PCIE_PRX_DTX_P3 F11 G20 USB3_RX0_N <25>
PERP3 USB3RN0 H20
10/100/1G LAN 0.1U_0402_16V7K 2 1 CC12 PCIE_PTX_DRX_N3 C29 USB3RP0 USB3_RX0_P <25>
<23> PCIE_PTX_C_DRX_N3
0.1U_0402_16V7K 2 1 CC13 PCIE_PTX_DRX_P3 B30 PETN3 PCIe USB C33
USB2.0/USB3.0
<23> PCIE_PTX_C_DRX_P3 PETP3 USB3TN0 USB3_TX0_N <25>
B34
USB3TP0 USB3_TX0_P <25>
<21> PCIE_PRX_DTX_N4 PCIE_PRX_DTX_N4 F13
PCIE_PRX_DTX_P4 G13 PERN4 E18
<21> PCIE_PRX_DTX_P4 PERP4 USB3RN1 USB3_RX1_N <25>
F18 USB3_RX1_P <25>
0.1U_0402_16V7K 2 1 CC19 PCIE_PTX_DRX_N4 B29 USB3RP1
WLAN <21> PCIE_PTX_C_DRX_N4
0.1U_0402_16V7K 2 1 CC38 PCIE_PTX_DRX_P4 A29 PETN4 B33
USB2.0/USB3.0
<21> PCIE_PTX_C_DRX_P4 PETP4 USB3TN1 USB3_TX1_N <25>
A33
USB3TP1 USB3_TX1_P <25>
G17 DG V0.9 USBRBIAS
<21> USB3_RX2_N
<21> USB3_RX2_P F17 PERN1/USB3RN2
PERP1/USB3RP2
L Trace width=50ohm and spacing=15mil
NGFF C30
<21> USB3_TX2_N
C31 PETN1/USB3TN2 AJ10 USBRBIAS RC148 1 2 22.6_0402_1%
Max length=500mil
<21> USB3_TX2_P PETP1/USB3TP2 USBRBIAS AJ11
PCIE_PRX_DTX_N2 F15 USBRBIAS AN10
<43> PCIE_PRX_DTX_N2 PERN2/USB3RN3 TP13
<43> PCIE_PRX_DTX_P2 PCIE_PRX_DTX_P2 G15 AM10
PERP2/USB3RP3 TP14
Card Reader 0.1U_0402_16V7K 2 1 CC73 PCIE_PTX_DRX_N2 B31
<43> PCIE_PTX_C_DRX_N2 PETN2/USB3TN3
0.1U_0402_16V7K 2 1 CC74 PCIE_PTX_DRX_P2 A31
<43> PCIE_PTX_C_DRX_P2 PETP2/USB3TP3 AL3 LED_LINK_LAN#_R LED_LINK_LAN#_R <9,23>
OC0/GPIO40 AT1 USB_OC1#
B B
OC1/GPIO41 AH2 CR_WAKE#
OC2/GPIO42 CR_WAKE# <43> +3V_PCH
RC151 E15 AV3 USB_OC3#
3K_0402_1% E13 TP3 OC3/GPIO43
1 2 PCH_PCIE_RCOMP A27 TP4 RPH10
<Page12> +1.05VS_VCCUSB3PLL
B27 PCIE_RCOMP PCH_GPIO13 4 5
PCIE_IREF <9> PCH_GPIO13
USB_OC1# 3 6
2 7
DG V0.9 PCIE_RCOMP USB_OC3# 1 8
L Width=12mil,spacing=12mil
11 OF 19
10K_0804_8P4R_5%
Max length=500mil CR_WAKE# RC328 1 @ 2 10K_0402_5%

+3VS

CR_WAKE# RC329 1 2 10K_0402_5%

A A

Security Classification Compal Secret Data


Issued Date 2011/06/29 Deciphered Date 2011/06/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCIE,USB
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.5
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B181P
Date: Tuesday, March 25, 2014 Sheet 10 of 62
5 4 3 2 1
5 4 3 2 1

WWW.AliSaler.Com +VCC_CORE@10000mA
+VCC_CORE
HASWELL_MCP_E
UCPU1L

+1.35V_VDDQ L59 C36


J58 RSVD VCC C40
RSVD VCC C44
+VCC_CORE 2500mA AH26 VCC C48
AJ31 VDDQ VCC C52
AJ33 VDDQ VCC C56
AJ37 VDDQ VCC E23
D D
AN33 VDDQ VCC E25
+VCC_CORE AP43 VDDQ VCC E27
AR48 VDDQ VCC E29
AY35 VDDQ VCC E31
AY40 VDDQ VCC E33
VDDQ VCC

1
AY44 E35
RC157 AY50 VDDQ VCC E37
+1.05VS_VCCST 100_0402_1% VDDQ VCC E39
DG V0.5 H_CPU_SVIDALRT#
SVID ALERT L RC154 close to CPU<300mil VCC_SENSE
F59
N58 VCCIN
VCC
VCC
E41
E43

2
AC58 RSVD VCC E45
Max length=1000~2000mil RSVD VCC

1
E47
RC154 VCCSENSE E63 VCC E49
<50> VCCSENSE VCC_SENSE VCC
75_0402_5% AB23 E51
A59 RSVD VCC E53
+VCCIO_OUT VCCIO_OUT VCC
+VCCIOA_OUT E20 E55
2

AD23 VCCIOA_OUT VCC E57


RC155 1 2 43_0402_1% H_CPU_SVIDALRT# AA23 RSVD VCC F24
<50> VR_SVID_ALRT# RSVD VCC
AE59 F28
RSVD VCC F32
H_CPU_SVIDALRT# L62 VCC F36
VR_SVID_CLK N63 VIDALERT VCC F40
+1.05VS_VCCST <50> VR_SVID_CLK VIDSCLK VCC
VR_SVID_DAT L63 F44
B59 VIDSOUT VCC F48
SVID DATA <50> VR12.5_VR_ON 1
<4,6> +1.05VS_PG
2 F60 VCCST_PWRGD
VR_EN
VCC
VCC
F52
1

RC301 RF@ 0_0402_5% VR12.6PG_MCP C59 F56


RC156 VR_READY HSW ULT POWER VCC G23
130_0402_1% D63 VCC G25
1 VSS VCC
@RF@ CPU_PWR_DEBUG H59 G27
C421 P62 PWR_DEBUG VCC G29
2

33P_0402_50V8J P60 VSS VCC G31


2 P61 RSVD_TP VCC G33
C
VR_SVID_DAT N59 RSVD_TP VCC G35 C
<50> VR_SVID_DAT RSVD_TP VCC
N61 G37
T59 RSVD_TP VCC G39
AD60 VSS VCC G41
AD59 VSS VCC G43
AA59 VSS VCC G45
AE60 VSS VCC G47
AC59 VSS VCC G49
AG58 VSS VCC G51
+VCCIO_OUT +1.05VS_VCCST U59 VSS VCC G53
V59 VSS VCC G55
RC294 1 @ 2 0_0402_5% +VCC_CORE VSS VCC G57
+1.05VS 600mA AC22 VCC H23
AE22 VCCST VCC J23
AE23 VCCST VCC K23
VCCST VCC K57
AB57 VCC L22
AD57 VCC VCC M23
AG57 VCC VCC M57
C24 VCC VCC P57
C28 VCC VCC U57
C32 VCC VCC W57
L DG V0.5 VIDSOUT VCC VCC
RC156 close to CPU<500mil 12 OF 19
Max length=1000~2000mil

+1.05VS_VCCST
VR12.5_VR_ON

11/07

1
150_0402_5%

B B
1

RC288
+1.05VS +1.05VS_VCCST
RC166

10K_0402_5%

2
short@
2

RC223 1 2 VR12.6PG_MCP
<50> VR12.6PG_MCP
CPU_PWR_DEBUG
1U_0402_6.3V6K

CPU_PWR_DEBUG <6>
0_0805_5%
10K_0402_5%

22U_0805_6.3V6M
CC71

1 1
1

CC72
@

@
RC167

2 2
2

+1.35V_VDDQ +1.35V_VDDQ
2.2U_0402_6.3V6M
CC20

2.2U_0402_6.3V6M
CC21

2.2U_0402_6.3V6M
CC22

2.2U_0402_6.3V6M
CC23

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
1 1
1 1 1 1 1 1 1 1 1 1
CC24 + CC25 +

CC26

CC27

CC28

CC29

CC30

CC31
@ @ @ @ @
330U_2.5V_M 330U_2.5V_M
2 2 2 2 2 2 2 2 2 2 2 2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2011/06/29 Deciphered Date 2011/06/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.5
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B181P
Date: Tuesday, March 25, 2014 Sheet 11 of 62
5 4 3 2 1
5 4 3 2 1

WWW.AliSaler.Com +1.05VS_VCCUSB3PLL
RC168 1
short@
2 +1.05VS_VCCHSIO short@

1U_0402_6.3V6K
+1.05VS_MODPHY
RC170 +3V_DSW_PRTCSUS 1 RC169 2 1 0_0402_5% +3V_PCH
1 2 +1.05VS_VCCUSB3PLL 0_0805_5%

1U_0402_6.3V6K

1U_0402_6.3V6K
+1.05VS_MODPHY 1 1

CC32
47U_0805_6.3V6M

CC33

CC34
2.2UH_LQM2MPN2R2NG0L_30%

1U_0402_6.3V6K
2
1 1 2 2

CC35

CC36
+RTCVCC +RTCVCC
HASWELL_MCP_E
UCPU1M
D 2 2 D

0.1U_0402_16V7K
CC37
K9

1U_0402_6.3V6K
VCCHSIO 1 1
L10
VCCHSIO

CC39
M9 @
N8 VCCHSIO mPHY RTC AH11
+1.05VS_VCCSATA3PLL +1.05VS VCCIO VCCSUS3 2 2
P9 AG10

1U_0402_6.3V6K
1 VCCIO VCCRTC
+1.05VS_VCCUSB3PLL B18 AE7 CC40 1 2 0.1U_0402_16V7K
VCCUSB3PLL DCPRTC

CC41
RC171 +1.05VS_VCCSATA3PLL B11
1 2 +1.05VS_VCCSATA3PLL VCCSATA3PLL
+1.05VS_MODPHY 2

47U_0805_6.3V6M
2.2UH_LQM2MPN2R2NG0L_30% RC173 Y20 SPI Y8

1U_0402_6.3V6K
0_0402_5% 1 @ 2 +1.05VS_APPLOPI AA21 VCCAPLL OPI VCCSPI +3V_PCH SPI ROM power rail
1 CC42 1 +1.05VS VCCAPLL 1
W21
VCCAPLL

CC43
AG14 +1.05VS @ CC44
2 @ 1 VCCASW AG13
USB3 VCCASW 0.1U_0402_16V7K
2 2 10U_0402_6.3V6M CC45 2
2 @ 1 J13

10U_0603_6.3V6M
+1.05V_DCPSUS3

1U_0402_6.3V6K

1U_0402_6.3V6K
1U_0402_6.3V6K CC46 DCPSUS3 J11
VCC1P05 +1.05VS
short@ H11 1 1 1
AXALIA/HDA CORE VCC1P05

CC48

CC49

CC50
+3VS RC172 1 2 0_0402_5% +VCCSUSHDA AH14 H15
VCCSUSHDA VCC1P05 AE8 RC174 CC52

1U_0402_6.3V6K
1 VCC1P05 AF22 0_0402_5% 1U_0402_6.3V6K
VRM/USB2/AZALIA VCC1P05 2 2 2

CC51
+1.05VS 1 @ 2 +1.05V_DCPSUS2 AH13 AG19 2 short@ 1 1 2
RC183 1 @ 2 DCPSUS2 DCPSUSBYP AG20 short@
C 2 DCPSUSBYP C
0_0201_5% CC47 1U_0201_6.3V6M AE9 +1.05VS_VCCASW RC175 1 2

1U_0402_6.3V6K
VCCASW +1.05VS
RC176 AF9
VCCASW

CC54
1 2 AC9 AG8

22U_0805_6.3V6M
+1.05VS +1.05VS_APPLOPI +3V_PCH 1 1 0_0805_5%
VCCSUS3_3 VCCASW

CC53
22U_0805_6.3V6M

AA9 AD10 +1.05V_DCPSUS1 1 @ 2 +1.05VS


VCCSUS3_3 DCPSUS1

CC55
22U_0805_6.3V6M
2.2UH_LQM2MPN2R2NG0L_30% +3V_DSW_P AH10 AD8 RC189
1U_0402_6.3V6K

1 VCCDSW3_3 DCPSUS1 1
V8 GPIO/LCC 0_0402_5%
1 1 VCC3_3 2 2
CC57

+3VS W9 @
VCC3_3
CC58

CC59
22U_0805_6.3V6M
1 J15 +1.5VS CC75
2 THERMAL SENSOR VCCTS1_5 K14 2 1U_0402_6.3V6K
2 2 VCC3_3 +3VS
K16
VCC3_3
2 1 2
SDIO power rail
ICC
+1.05VS_AXCKDCB J18 SDIO/PLSS CC76 0.1U_0402_16V7K RC178 short@
K19 VCC1P05 U8 +3V_1V8_SDIO 1 2 0_0603_5%
VCC1P05 VCCSDIO +3VS
RC280 +1.05VS_AXCK_LCPLL A20 T9

1U_0402_6.3V6K
1 short@ 2 +V1.05S_SSCF100 +V1.05S_SSCF100 J17 VCCACLKPLL VCCSDIO
+1.05VS VCCCLK 1
+V1.05S_SSCFF R21
VCCCLK LPT LP POWER

CC60
0_0603_5% T21
1U_0402_6.3V6K

K18 VCCCLK SUS OSCILLATOR AB8 +1.05V_AOSCSUS


1 VCCCLK DCPSUS4 2
M20
VCCCLK
CC61

V21
RC281 AE20 VCCCLK AC20
2 +3V_PCH VCCSUS3_3 VCCAPLL
+1.05VS 1 2 +V1.05S_SSCFF AE21 AG16
VCCSUS3_3 USB2 VCCIO AG17
1U_0402_6.3V6K

B +1.05VS B
short@ VCCIO RC180

1U_0402_6.3V6K
1
0_0603_5% 1 +1.05V_AOSCSUS 1 @ 2 +1.05VS
CC62

CC65
13 OF 19 2.2UH_LQM2MPN2R2NG0L_30%

1U_0402_6.3V6K
2

100U_1206_6.3V6K
2 1 1

CC67
+3V_DSW_P

CC66
@ @
RC179
1 2 +1.05VS_AXCKDCB 2 2
+1.05VS
short@
47U_0805_6.3V6M

47U_0805_6.3V6M

2.2UH_LQM2MPN2R2NG0L_30% 1 RC285 1 2 0_0402_5%


1U_0402_6.3V6K

1 1 +3VDS Deep S3 RC285-->SMT Total 1.05VS=1838+2274=4111mA


CC63

CC77
CC64

11/07 +3V_DSW_P Non Deep S3 RC182-->SMT Total 1.5VS=3mA


2 2 2 1

1U_0402_6.3V6K
Total 1.8VS=7mA

CC70
+1.05VS_AXCK_LCPLL
2 Total 3VS=0mA
RC181 Total 3VALW=200+62=262mA
+1.05VS 1 2 +1.05VS_AXCK_LCPLL
47U_0805_6.3V6M

47U_0805_6.3V6M

10U_0402_6.3V6M

2.2UH_LQM2MPN2R2NG0L_30%
Total 3V_PCH=99mA
1U_0402_6.3V6K

1 1 1 1 Total 1.05V=540+109=649mA
CC68

CC78

CC79

A A
CC69

2 2 2 2
Security Classification Compal Secret Data
Issued Date 2011/06/29 Deciphered Date 2011/06/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-B181P 0.5
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 25, 2014 Sheet 12 of 62
5 4 3 2 1
5 4 3 2 1

WWW.AliSaler.Com
UCPU1NHASWELL_MCP_E

A11 AJ35 HASWELL_MCP_E


UCPU1O
A14 VSS VSS AJ39
A18 VSS VSS AJ41 AP22 AV59
A24 VSS VSS AJ43 AP23 VSS VSS AV8
A28 VSS VSS AJ45 AP26 VSS VSS AW16
A32 VSS VSS AJ47 AP29 VSS VSS AW24
A36 VSS VSS AJ50 AP3 VSS VSS AW33 UCPU1P HASWELL_MCP_E
D A40 VSS VSS AJ52 AP31 VSS VSS AW35 H17 D
A44 VSS VSS AJ54 AP38 VSS VSS AW37 D33 VSS H57
A48 VSS VSS AJ56 AP39 VSS VSS AW4 D34 VSS VSS J10
A52 VSS VSS AJ58 AP48 VSS VSS AW40 D35 VSS VSS J22
A56 VSS VSS AJ60 AP52 VSS VSS AW42 D37 VSS VSS J59
AA1 VSS VSS AJ63 AP54 VSS VSS AW44 D38 VSS VSS J63
AA58 VSS VSS AK23 AP57 VSS VSS AW47 D39 VSS VSS K1
AB10 VSS VSS AK3 AR11 VSS VSS AW50 D41 VSS VSS K12
AB20 VSS VSS AK52 AR15 VSS VSS AW51 D42 VSS VSS L13
AB22 VSS VSS AL10 AR17 VSS VSS AW59 D43 VSS VSS L15
AB7 VSS VSS AL13 AR23 VSS VSS AW60 D45 VSS VSS L17
AC61 VSS VSS AL17 AR31 VSS VSS AY11 D46 VSS VSS L18
AD21 VSS VSS AL20 AR33 VSS VSS AY16 D47 VSS VSS L20
AD3 VSS VSS AL22 AR39 VSS VSS AY18 D49 VSS VSS L58
AD63 VSS VSS AL23 AR43 VSS VSS AY22 D5 VSS VSS L61
AE10 VSS VSS AL26 AR49 VSS VSS AY24 D50 VSS VSS L7
AE5 VSS VSS AL29 AR5 VSS VSS AY26 D51 VSS VSS M22
AE58 VSS VSS AL31 AR52 VSS VSS AY30 D53 VSS VSS N10
AF11 VSS VSS AL33 AT13 VSS VSS AY33 D54 VSS VSS N3
AF12 VSS VSS AL36 AT35 VSS VSS AY4 D55 VSS VSS P59
AF14 VSS VSS AL39 AT37 VSS VSS AY51 D57 VSS VSS P63
AF15 VSS VSS AL40 AT40 VSS VSS AY53 D59 VSS VSS R10
AF17 VSS VSS AL45 AT42 VSS VSS AY57 D62 VSS VSS R22
AF18 VSS VSS AL46 AT43 VSS VSS AY59 D8 VSS VSS R8
C VSS VSS VSS VSS VSS VSS C
AG1 AL51 AT46 AY6 E11 T1
AG11 VSS VSS AL52 AT49 VSS VSS B20 E17 VSS VSS T58
AG21 VSS VSS AL54 AT61 VSS VSS B24 F20 VSS VSS U20
AG23 VSS VSS AL57 AT62 VSS VSS B26 F26 VSS VSS U22
AG60 VSS VSS AL60 AT63 VSS VSS B28 F30 VSS VSS U61
AG61 VSS VSS AL61 AU1 VSS VSS B32 F34 VSS VSS U9
AG62 VSS VSS AM1 AU16 VSS VSS B36 F38 VSS VSS V10
AG63 VSS VSS AM17 AU18 VSS VSS B4 F42 VSS VSS V3
AH17 VSS VSS AM23 AU20 VSS VSS B40 F46 VSS VSS V7
AH19 VSS VSS AM31 AU22 VSS VSS B44 F50 VSS VSS W20
AH20 VSS VSS AM52 AU24 VSS VSS B48 F54 VSS VSS W22
AH22 VSS VSS AN17 AU26 VSS VSS B52 F58 VSS VSS Y10
AH24 VSS VSS AN23 AU28 VSS VSS B56 F61 VSS VSS Y59
AH28 VSS VSS AN31 AU30 VSS VSS B60 G18 VSS VSS Y63
AH30 VSS VSS AN32 AU33 VSS VSS C11 G22 VSS VSS
AH32 VSS VSS AN35 AU51 VSS VSS C14 G3 VSS
AH34 VSS VSS AN36 AU53 VSS VSS C18 G5 VSS V58
AH36 VSS VSS AN39 AU55 VSS VSS C20 G6 VSS VSS AH46
AH38 VSS VSS AN40 AU57 VSS VSS C25 G8 VSS VSS V23
AH40 VSS VSS AN42 AU59 VSS VSS C27 H13 VSS VSS E62
VSS VSS VSS VSS VSS VSS_SENSE VSSSENSE <50>
AH42 AN43 AV14 C38 AH16
AH44 VSS VSS AN45 AV16 VSS VSS C39 16 OF 19 VSS
AH49 VSS VSS AN46 AV20 VSS VSS C57
VSS VSS VSS VSS

1
B AH51 AN48 AV24 D12 B
AH53 VSS VSS AN49 AV28 VSS VSS D14 RC158
AH55 VSS VSS AN51 AV33 VSS VSS D18 100_0402_1%
AH57 VSS VSS AN52 AV34 VSS VSS D2
AJ13 VSS VSS AN60 AV36 VSS VSS D21

2
AJ14 VSS VSS AN63 AV39 VSS VSS D23
AJ23 VSS VSS AN7 AV41 VSS VSS D25
AJ25 VSS VSS AP10 AV43 VSS VSS D26
AJ27 VSS VSS AP17 AV46 VSS VSS D27
AJ29 VSS VSS AP20 AV49 VSS VSS D29
VSS VSS AV51 VSS VSS D30
AV55 VSS VSS D31
VSS 15 OF 19 VSS
14 OF 19

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/05/27 Deciphered Date 2011/05/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
GND/VSSSEN
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.5
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B181P
Date: Tuesday, March 25, 2014 Sheet 13 of 62
5 4 3 2 1
5 4 3 2 1

WWW.AliSaler.Com
HASWELL_MCP_E
UCPU1Q CFG4

1
DC_TEST_AY2_AW2 AY2 A3 TP_DC_TEST_A3_B3
DC_TEST_AY3_AW3 AY3 DAISY_CHAIN_NCTF_AY2 DAISY_CHAIN_NCTF_A3 A4 RC185
AY60 DAISY_CHAIN_NCTF_AY3 DAISY_CHAIN_NCTF_A4 1K_0402_1%
DC_TEST_AY61_AW61 AY61 DAISY_CHAIN_NCTF_AY60 A60

2
DC_TEST_AY61_AW62 AY62 DAISY_CHAIN_NCTF_AY61 DAISY_CHAIN_NCTF_A60 A61 DC_TEST_A61_B61
B2 DAISY_CHAIN_NCTF_AY62 DAISY_CHAIN_NCTF_A61 A62
TP_DC_TEST_A3_B3 B3 DAISY_CHAIN_NCTF_B2 DAISY_CHAIN_NCTF_A62 AV1
DC_TEST_A61_B61 B61 DAISY_CHAIN_NCTF_B3 DAISY_CHAIN_NCTF_AV1 AW1
D DC_TEST_B62_B63 B62 DAISY_CHAIN_NCTF_B61 DAISY_CHAIN_NCTF_AW1 AW2 DC_TEST_AY2_AW2 D
B63 DAISY_CHAIN_NCTF_B62 DAISY_CHAIN_NCTF_AW2 AW3 DC_TEST_AY3_AW3
DC_TEST_C1_C2 C1 DAISY_CHAIN_NCTF_B63 DAISY_CHAIN_NCTF_AW3 AW61 DC_TEST_AY61_AW61 Display Port Presence Strap
C2 DAISY_CHAIN_NCTF_C1 DAISY_CHAIN_NCTF_AW61 AW62 DC_TEST_AY61_AW62
DAISY_CHAIN_NCTF_C2 DAISY_CHAIN_NCTF_AW62 AW63
17 OF 19 DAISY_CHAIN_NCTF_AW63 1 : Disabled; No Physical Display Port        
CFG4 attached to  Embedded Display Port
0 : Enabled; An external Display Port device is          
UCPU1R HASWELL_MCP_E
* connected to the Embedded Display Port  
N23
RSVD R23
RSVD T23
AT2 RSVD U10
AU44 RSVD RSVD
AV44 RSVD
D15 RSVD AL1 CFG0
RSVD RSVD AM11
RSVD

1
AP7
F22 RSVD AU10
H22 RSVD RSVD AU15 @ RC187
J21 RSVD RSVD AW14 1K_0402_1%
C RSVD TP2 C
AY14

2
TP1

18 OF 19

UCPU1S HASWELL_MCP_E

CFG0 AC60 AV63


<6> CFG0 CFG0 RSVD_TP
CFG1 AC62 AU63
<6> CFG1 CFG1 RSVD_TP
CFG2 AC63
<6> CFG2 CFG2
CFG3 AA63
<6> CFG3 CFG3
CFG4 AA60 C63
<6> CFG4 CFG4 RSVD_TP
CFG5 Y62 C62
<6> CFG5 CFG5 RSVD_TP
CFG6 Y61 B43
<6> CFG6 CFG6 EDP_SPARE
CFG7 Y60
<6> CFG7 CFG7
CFG8 V62 A51
<6> CFG8 CFG8 RSVD_TP
CFG9 V61 B51
<6> CFG9 CFG9 RSVD_TP
CFG10 V60
<6> CFG10 CFG10
B CFG11 U60 L60 B
<6> CFG11 CFG11 RSVD_TP
CFG12 T63
<6> CFG12 CFG12
CFG13 T62 N60
<6> CFG13 CFG13 RESERVED RSVD
CFG14 T61
<6> CFG14 CFG14
CFG15 T60 W23
<6> CFG15 CFG15 RSVD Y22 MCP_RSVD_29 RC296 2 @ 1 49.9_0402_1%
CFG16 AA62 RSVD AY15 PROC_OPI_COMP RC186 2 1 49.9_0402_1%
<6> CFG16
CFG18 U63 CFG16 OPI_COMP1 L DG V0.9 PROC_OPI_COMP
<6> CFG18 CFG18 Width=12mil,spacing=12mil
CFG17 AA61 AV62
<6> CFG17 CFG17 RSVD
CFG19 U62 D58
<6> CFG19 CFG19 RSVD Max length=500mil
2 1 CFG_RCOMP V63 P22
RC188 49.9_0402_1% CFG_RCOMP VSS N21
A5 VSS
RSVD P20
E1 HVM_CLK R20
D1 TP9 HVM_CLK_P
J20 TP10
H18 TP11
1 2 TD_IREF B12 TP12
RC191 8.2K_0402_5% TD_IREF
19 OF 19

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2011/06/29 Deciphered Date 2011/06/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
RSVD/CFG
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.5
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B181P
Date: Tuesday, March 25, 2014 Sheet 14 of 62
5 4 3 2 1
5 4 3 2 1

WWW.AliSaler.Com <5> DDR_A_D[0..63]

<5> DDR_A_DQS[0..7]

<5> DDR_A_DQS#[0..7]

<5> DDR_A_MA[0..15]

+1.35V_VDDQ
+V_VDDR_REFA_DQ +1.35V_VDDQ +1.35V_VDDQ

JDDRL1
+V_VDDR_REFA_DQ 1 2 +5VDS QD1
D
3 VREF_DQ VSS1 4 DDR_A_D9 MESS138-G 1N SOT23-3 D
VSS2 DQ4

0.1U_0402_16V7K
DDR_A_D13 5 6 DDR_A_D12
DQ0 DQ5

CD1
DDR_A_D8 7 8 1 3 RD20 1 2 66.5_0402_1% M_ODT0

S
1 DQ1 VSS3

1
9 10 DDR_A_DQS#1
11 VSS4 DQS#0 12 DDR_A_DQS1 RD21 RD22 1 2 66.5_0402_1% M_ODT1
13 DM0 DQS0 14 12/20

G
2
2 DDR_A_D14 15 VSS5 VSS6 16 DDR_A_D15 220K_0402_5% RD23 1 2 66.5_0402_1% M_ODT2
DQ2 DQ6 M_ODT2 <16>
DDR_A_D10 17 18 DDR_A_D11

2
19 DQ3 DQ7 20 RD24 1 2 66.5_0402_1% M_ODT3
VSS7 VSS8 M_ODT3 <16>
DDR_A_D29 21 22 DDR_A_D25
DDR_A_D28 23 DQ8 DQ12 24 DDR_A_D24
DQ9 DQ13

1
25 26
DDR_A_DQS#3 27 VSS9 VSS10 28 RD25 SM_PG_CTRL
DQS#1 DM1 SM_PG_CTRL <4,48>
DDR_A_DQS3 29 30 DDR3_DRAMRST# @
DQS1 RESET# DDR3_DRAMRST# <4,16>
31 32 2M_0402_5%
DDR_A_D30 33 VSS11 VSS12 34 DDR_A_D27

2
DDR_A_D31 35 DQ10 DQ14 36 DDR_A_D26
37 DQ11 DQ15 38
DDR_A_D44 39 VSS13 VSS14 40 DDR_A_D45
DDR_A_D41 41 DQ16 DQ20 42 DDR_A_D40
43 DQ17 DQ21 44
DDR_A_DQS#5 45 VSS15 VSS16 46
DDR_A_DQS5 47 DQS#2 DM2 48
49 DQS2 VSS17 50 DDR_A_D42
DDR_A_D43 51 VSS18 DQ22 52 DDR_A_D46
DDR_A_D47 53 DQ18 DQ23 54
55 DQ19 VSS19 56 DDR_A_D52
DDR_A_D51 57 VSS20 DQ28 58 DDR_A_D53
DDR_A_D50 59 DQ24 DQ29 60
61 DQ25 VSS21 62 DDR_A_DQS#6
63 VSS22 DQS#3 64 DDR_A_DQS6
65 DM3 DQS3 66
DDR_A_D49 67 VSS23 VSS24 68 DDR_A_D54
DDR_A_D48 69 DQ26 DQ30 70 DDR_A_D55
71 DQ27 DQ31 72
VSS25 VSS26

C C
DDR_CKE0_DIMMA 73 74 DDR_CKE1_DIMMA
<5> DDR_CKE0_DIMMA CKE0 CKE1 DDR_CKE1_DIMMA <5>
75 76
77 VDD1 VDD2 78 DDR_A_MA15
DDR_A_BS2 79 NC1 A15 80 DDR_A_MA14
<5> DDR_A_BS2 BA2 A14
81 82
DDR_A_MA12 83 VDD3 VDD4 84 DDR_A_MA11
DDR_A_MA9 85 A12/BC# A11 86 DDR_A_MA7
87 A9 A7 88
DDR_A_MA8 89 VDD5 VDD6 90 DDR_A_MA6
DDR_A_MA5 91 A8 A6 92 DDR_A_MA4
93 A5 A4 94
DDR_A_MA3 95 VDD7 VDD8 96 DDR_A_MA2
DDR_A_MA1 97 A3 A2 98 DDR_A_MA0
99 A1 A0 100
M_CLK_DDR0 101 VDD9 VDD10 102 M_CLK_DDR1
<5> M_CLK_DDR0 CK0 CK1 M_CLK_DDR1 <5>
M_CLK_DDR#0 103 104 M_CLK_DDR#1
<5> M_CLK_DDR#0 CK0# CK1# M_CLK_DDR#1 <5>
105 106
DDR_A_MA10 107 VDD11 VDD12 108 DDR_A_BS1
A10/AP BA1 DDR_A_BS1 <5>
<5> DDR_A_BS0 DDR_A_BS0 109 110 DDR_A_RAS# DDR_A_RAS# <5>
111 BA0 RAS# 112
DDR_A_WE# 113 VDD13 VDD14 114 DDR_CS0_DIMMA#
<5> DDR_A_WE# WE# S0# DDR_CS0_DIMMA# <5>
<5> DDR_A_CAS# DDR_A_CAS# 115 116 M_ODT0
117 CAS# ODT0 118
DDR_A_MA13 119 VDD15 VDD16 120 M_ODT1
DDR_CS1_DIMMA# 121 A13 ODT1 122 +V_VDDR_REFA_CA
<5> DDR_CS1_DIMMA# S1# NC2
123 124
125 VDD17 VDD18 126 +V_VDDR_REFA_CA
127 NCTEST VREF_CA 128
VSS27 VSS28

0.1U_0402_16V7K
DDR_A_D0 129 130 DDR_A_D5
DDR_A_D1 131 DQ32 DQ36 132 DDR_A_D4
DQ33 DQ37

CD3
133 134 1
DDR_A_DQS#0 135 VSS29 VSS30 136
DDR_A_DQS0 137 DQS#4 DM4 138
+1.35V_VDDQ 139 DQS4 VSS31 140 DDR_A_D3
DDR_A_D2 141 VSS32 DQ38 142 DDR_A_D7 2
DDR_A_D6 143 DQ34 DQ39 144
145 DQ35 VSS33 146 DDR_A_D18
B VSS34 DQ44 B
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

DDR_A_D21 147 148 DDR_A_D19


DQ40 DQ45
CD6

CD7

CD8

CD9

CD10

CD11

CD12

CD13

1 1 1 1 1 1 1 1 DDR_A_D20 149 150


151 DQ41 VSS35 152 DDR_A_DQS#2
@ @ 153 VSS36 DQS#5 154 DDR_A_DQS2
@ @ 155 DM5 DQS5 156
2 2 2 2 2 2 2 2 DDR_A_D17 157 VSS37 VSS38 158 DDR_A_D22
DDR_A_D16 159 DQ42 DQ46 160 DDR_A_D23
161 DQ43 DQ47 162
DDR_A_D36 163 VSS39 VSS40 164 DDR_A_D37
DDR_A_D33 165 DQ48 DQ52 166 DDR_A_D32
167 DQ49 DQ53 168
+1.35V_VDDQ DDR_A_DQS#4 169 VSS41 VSS42 170
DDR_A_DQS4 171 DQS#6 DM6 172
173 DQS6 VSS43 174 DDR_A_D35
VSS44 DQ54
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

DDR_A_D34 175 176 DDR_A_D39


DDR_A_D38 177 DQ50 DQ55 178
1 1 1 1 1 1 1 1 DQ51 VSS45
179 180 DDR_A_D63
VSS46 DQ60
CD55

CD56

CD57

CD58

CD63

CD64

CD65

CD66

DDR_A_D62 181 182 DDR_A_D59


DDR_A_D58 183 DQ56 DQ61 184
2 2 @ 2 @ 2 @ 2 2 2 2 185 DQ57 VSS47 186 DDR_A_DQS#7
187 VSS48 DQS#7 188 DDR_A_DQS7
189 DM7 DQS7 190
DDR_A_D60 191 VSS49 VSS50 192 DDR_A_D56 +0.675VS
DDR_A_D61 193 DQ58 DQ62 194 DDR_A_D57
RD1 short@ 195 DQ59 DQ63 196
1 2 197 VSS51 VSS52 198
0_0402_5% 199 SA0 EVENT# 200 PCH_SMBDATA
+3VS VDDSPD SDA PCH_SMBDATA <6,7,16,43>
0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

CD24

10U_0603_6.3V6M
201 202 PCH_SMBCLK
SA1 SCL PCH_SMBCLK <6,7,16,43>
CD17

CD19

CD21
1 203 204 1 1 1
+0.675VS VTT1 VTT2 +0.675VS
1

RD2 205 206


0_0402_5% GND1 GND2
2 FOX_AS0A626-U4R6-7H 2 2 2
short@
CONN@
2

A A

Security Classification Compal Secret Data


Issued Date 2011/06/29 Deciphered Date 2011/06/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDR3L DIMM0
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C 0.5
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B181P
Date: Tuesday, March 25, 2014 Sheet 15 of 62
5 4 3 2 1
5 4 3 2 1

WWW.AliSaler.Com

+V_VDDR_REFB_DQ +1.35V_VDDQ +1.35V_VDDQ

JDDRL2
D D
+V_VDDR_REFB_DQ 1 2
3 VREF_DQ VSS1 4 DDR_B_D12
VSS2 DQ4

0.1U_0402_16V7K
DDR_B_D8 5 6 DDR_B_D9
DQ0 DQ5

CD27
1 DDR_B_D14 7 8
9 DQ1 VSS3 10 DDR_B_DQS#1
11 VSS4 DQS#0 12 DDR_B_DQS1
13 DM0 DQS0 14
2 DDR_B_D10 15 VSS5 VSS6 16 DDR_B_D13
DDR_B_D11 17 DQ2 DQ6 18 DDR_B_D15
<5> DDR_B_D[0..63] DQ3 DQ7
19 20
DDR_B_D28 21 VSS7 VSS8 22 DDR_B_D25
<5> DDR_B_DQS[0..7] DQ8 DQ12
DDR_B_D29 23 24 DDR_B_D24
25 DQ9 DQ13 26
<5> DDR_B_DQS#[0..7] VSS9 VSS10
DDR_B_DQS#3 27 28
DDR_B_DQS3 29 DQS#1 DM1 30 DDR3_DRAMRST#
<5> DDR_B_MA[0..15] DQS1 RESET# DDR3_DRAMRST# <4,15>
31 32
DDR_B_D26 33 VSS11 VSS12 34 DDR_B_D30
DDR_B_D27 35 DQ10 DQ14 36 DDR_B_D31
37 DQ11 DQ15 38
DDR_B_D40 39 VSS13 VSS14 40 DDR_B_D45
DDR_B_D41 41 DQ16 DQ20 42 DDR_B_D44
43 DQ17 DQ21 44
DDR_B_DQS#5 45 VSS15 VSS16 46
DDR_B_DQS5 47 DQS#2 DM2 48
49 DQS2 VSS17 50 DDR_B_D47
DDR_B_D46 51 VSS18 DQ22 52 DDR_B_D43
DDR_B_D42 53 DQ18 DQ23 54
55 DQ19 VSS19 56 DDR_B_D61
DDR_B_D56 57 VSS20 DQ28 58 DDR_B_D60
DDR_B_D57 59 DQ24 DQ29 60
61 DQ25 VSS21 62 DDR_B_DQS#7
63 VSS22 DQS#3 64 DDR_B_DQS7
65 DM3 DQS3 66
DDR_B_D59 67 VSS23 VSS24 68 DDR_B_D63
DDR_B_D58 69 DQ26 DQ30 70 DDR_B_D62
71 DQ27 DQ31 72
VSS25 VSS26
C C

DDR_CKE0_DIMMB 73 74 DDR_CKE1_DIMMB DDR_CKE1_DIMMB <5>


<5> DDR_CKE0_DIMMB CKE0 CKE1
75 76
77 VDD1 VDD2 78 DDR_B_MA15
DDR_B_BS2 79 NC1 A15 80 DDR_B_MA14
<5> DDR_B_BS2 BA2 A14
81 82
DDR_B_MA12 83 VDD3 VDD4 84 DDR_B_MA11
DDR_B_MA9 85 A12/BC# A11 86 DDR_B_MA7
87 A9 A7 88
DDR_B_MA8 89 VDD5 VDD6 90 DDR_B_MA6
DDR_B_MA5 91 A8 A6 92 DDR_B_MA4
93 A5 A4 94
DDR_B_MA3 95 VDD7 VDD8 96 DDR_B_MA2
DDR_B_MA1 97 A3 A2 98 DDR_B_MA0
99 A1 A0 100
M_CLK_DDR2 101 VDD9 VDD10 102 M_CLK_DDR3
<5> M_CLK_DDR2 CK0 CK1 M_CLK_DDR3 <5>
M_CLK_DDR#2 103 104 M_CLK_DDR#3 M_CLK_DDR#3 <5>
<5> M_CLK_DDR#2 CK0# CK1#
105 106
DDR_B_MA10 107 VDD11 VDD12 108 DDR_B_BS1
A10/AP BA1 DDR_B_BS1 <5>
<5> DDR_B_BS0 DDR_B_BS0 109 110 DDR_B_RAS# DDR_B_RAS# <5>
111 BA0 RAS# 112
DDR_B_WE# 113 VDD13 VDD14 114 DDR_CS0_DIMMB#
<5> DDR_B_WE# WE# S0# DDR_CS0_DIMMB# <5>
<5> DDR_B_CAS# DDR_B_CAS# 115 116 M_ODT2 M_ODT2 <15>
117 CAS# ODT0 118
DDR_B_MA13 119 VDD15 VDD16 120 M_ODT3 +V_VDDR_REFA_CA
A13 ODT1 M_ODT3 <15>
DDR_CS1_DIMMB# 121 122
<5> DDR_CS1_DIMMB# S1# NC2
123 124
125 VDD17 VDD18 126 +V_VDDR_REFA_CA
127 NCTEST VREF_CA 128
VSS27 VSS28

0.1U_0402_16V7K
+1.35V_VDDQ DDR_B_D4 129 130 DDR_B_D5
DDR_B_D1 131 DQ32 DQ36 132 DDR_B_D0
DQ33 DQ37

CD29
133 134 1
DDR_B_DQS#0 135 VSS29 VSS30 136
DQS#4 DM4
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

DDR_B_DQS0 137 138


DQS4 VSS31
CD33

CD34

CD35

CD36

CD37

CD38

CD39

CD40

1 1 1 1 1 1 1 1 139 140 DDR_B_D2


DDR_B_D3 141 VSS32 DQ38 142 DDR_B_D6 2
DDR_B_D7 143 DQ34 DQ39 144
B
@ @ @ @ 145 DQ35 VSS33 146 DDR_B_D16 B
2 2 2 2 2 2 2 2 DDR_B_D21 147 VSS34 DQ44 148 DDR_B_D17
DDR_B_D20 149 DQ40 DQ45 150
151 DQ41 VSS35 152 DDR_B_DQS#2
153 VSS36 DQS#5 154 DDR_B_DQS2
155 DM5 DQS5 156
DDR_B_D22 157 VSS37 VSS38 158 DDR_B_D19
DDR_B_D23 159 DQ42 DQ46 160 DDR_B_D18
161 DQ43 DQ47 162
DDR_B_D36 163 VSS39 VSS40 164 DDR_B_D37
DDR_B_D33 165 DQ48 DQ52 166 DDR_B_D32
+1.35V_VDDQ 167 DQ49 DQ53 168
DDR_B_DQS#4 169 VSS41 VSS42 170
DDR_B_DQS4 171 DQS#6 DM6 172
DQS6 VSS43
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

173 174 DDR_B_D34


DDR_B_D35 175 VSS44 DQ54 176 DDR_B_D38
1 1 1 1 1 1 1 1 DQ50 DQ55
DDR_B_D39 177 178
DQ51 VSS45
CD59

CD60

CD61

CD62

CD67

CD68

CD69

CD70

179 180 DDR_B_D51


DDR_B_D52 181 VSS46 DQ60 182 DDR_B_D55 +0.675VS
2 2 2 2 2 @ 2 @ 2 2 DDR_B_D49 183 DQ56 DQ61 184
@ 185 DQ57 VSS47 186 DDR_B_DQS#6
187 VSS48 DQS#7 188 DDR_B_DQS6
189 DM7 DQS7 190
VSS49 VSS50

0.1U_0402_16V7K

0.1U_0402_16V7K

CD50

10U_0603_6.3V6M
DDR_B_D48 191 192 DDR_B_D54
DQ58 DQ62

CD45

CD46
DDR_B_D53 193 194 DDR_B_D50 1 1 1
195 DQ59 DQ63 196
RD3 1 short@ 2 0_0402_5% 197 VSS51 VSS52 198
199 SA0 EVENT# 200 PCH_SMBDATA
+3VS VDDSPD SDA PCH_SMBDATA <6,7,15,43> 2 2 2
0.1U_0402_16V7K

+3VS RD4 1 210K_0402_5% 201 202 PCH_SMBCLK


SA1 SCL PCH_SMBCLK <6,7,15,43>
CD44

1 +0.675VS 203 204 +0.675VS


VTT1 VTT2
205 206
GND1 GND2
2 FOX_AS0A626-U4R6-7H
CONN@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/05/27 Deciphered Date 2011/05/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDR3L DIMM1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.5
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B181P
Date: Tuesday, March 25, 2014 Sheet 16 of 62
5 4 3 2 1
5 4 3 2 1

WWW.AliSaler.Com

+1.35V_VDDQ
DDR3L VREF +1.35V_VDDQ
D D

1
12/20 RD5 RD6
1.8K_0402_1% 12/20 1.8K_0402_1%

RD7 RD8

2
<CPU> +V_DDR_REFA_R 1 2 +V_VDDR_REFA_DQ <DDR3L_A> +V_SM_VREF_CNT 1 2 +V_VDDR_REFA_CA <DDR3L_A_CA>
1
2_0402_1%
<CPU> 1
2_0402_1%
CD52 @ CD53 @
<DDR3L_B_CA>

1
0.022U_0402_25V7K 0.022U_0402_25V7K
2 RD9 2 RD10

1
1.8K_0402_1% 1.8K_0402_1%
RD11 RD12
24.9_0402_1% @ 24.9_0402_1% @

2
2

2
+1.35V_VDDQ
C C

1
RD13
1.8K_0402_1%
12/20
RD15 2
<CPU> +V_DDR_REFB_R 1 2 +V_VDDR_REFB_DQ <DDR3L_B>
1
2_0402_1%
CD54 @
1

0.022U_0402_25V7K
2 RD17
1

1.8K_0402_1%
RD19
24.9_0402_1% @
2
2

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2011/06/29 Deciphered Date 2011/06/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDR3L VREF
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.5
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B181P
Date: Tuesday, March 25, 2014 Sheet 17 of 62
5 4 3 2 1
5 4 3 2 1

WWW.AliSaler.Com
JPHW7 need to short
+3VS +3VS_RT Layout note
※ROM only  mode : PIN 47 4.7k pull low,  Pin 48 4.7k pull high.
EP mode               : PIN 47 4.7k pull high, Pin 48 4.7k pull low.
Layout note Close to
@ JPHW7
80mil 1 2
80mil Close to LT5 Close to Pin18 Close to Pin13 Close to Pin11  Pin27 Close to Pin7 EEPROM               : PIN 47 4.7k pull high, Pin 48 4.7k pull high.
1 2
JUMP_43X79 +SWR_VDD +SWR_VDD +SWR_V12
12/20
〈 ※Default mode 〉
+SWR_V12

10U_0603_6.3V6M

0.1U_0402_16V4Z

10U_0603_6.3V6M

0.1U_0402_16V4Z

0.1U_0402_16V4Z

10U_0603_6.3V6M

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
12/20
Layout note 1 1 1 1 1 1 1 1 1
+3VS_RT +3VS_RT

Close to Pin3

CT29

CT30

CT31

CT32

CT33

CT34

CT35

CT36

CT37
12/20

2
D +DP_V33 2 2 2 2 2 2 2 2 2 D
+DP_V33 RT27@ RT28
4.7K_0402_5%
10U_0603_6.3V6M

0.1U_0402_16V4Z

0.1U_0402_16V4Z
4.7K_0402_5%
1 1 1

1
MIIC_SDA MIIC_SCL
CT38

CT39

CT40

2
2 2 2
RT29 RT30@
4.7K_0402_5% 4.7K_0402_5%
PIN47 PIN48

1
+3VS_RT UT1 LVDS@

SWR / LDO Mode select RTD2136N


35 LVDS_A_CLKP LVDS_A_CLKP <19>
TXOC+
40mil 22
PVCC TXOC-
36 LVDS_A_CLKN LVDS_A_CLKN <19>
LDO SWR
80mil LT16 2 1 +SWR_VDD 100mil 18 41 LVDS_A_TXP0 LVDS_A_TXP0 <19>
FBMA-L11-201209-221LMA30T_0805 SWR_VDD TXO0+ 42 LVDS_A_TXN0
TXO0- LVDS_A_TXN0 <19>

PWR
LT17 2 1 +DP_V33 40mil 5
DP_V33 +SWR_VDD
2132S Do not support mount LT7 12/20 FBMA-L11-201209-221LMA30T_0805 39 LVDS_A_TXP1 LVDS_A_TXP1 <19>
+SWR_V12 RT31 1 2 +SWR_LX 40mil 17 TXO1+ 40 LVDS_A_TXN1
+SWR_V12 SWR_LX TXO1- LVDS_A_TXN1 <19>
4.7UH_1098AS-4R7M_1.3A_20%
UT5 @
40mil 15 SWR_VCCK TXO2+
37 LVDS_A_TXP2 LVDS_A_TXP2 <19> 8 1
2132R Use 0 ohm mount LT7 38 LVDS_A_TXN2 LVDS_A_TXN2 <19> VCC A0
43 TXO2- 7 2
40mil VCCK WP A1
33 TT4 PAD~D LCD_EDID_CLK 6 3
C TXO3+ LCD_EDID_DATA 5 SCL A2 4 C
40mil 11
DP_V12 TXO3-
34 TT5 PAD~D SDA GND
※ If use 2132R, please select LDO mode as default. CAT24C64WI-GT3_SO8
25 LVDS_B_CLKP LVDS_B_CLKP <19>
EDP_CPU_LANE_P0 7 TXEC+ 26 LVDS_B_CLKN
<4> EDP_CPU_LANE_P0 LANE0P TXEC- LVDS_B_CLKN <19>
EDP_CPU_LANE_N0 8

LVDS
<4> EDP_CPU_LANE_N0 LANE0N 31 LVDS_B_R_TXOUT0+
RP38 EDP_CPU_LANE_P1 9 TXE0+ 32 LVDS_B_R_TXOUT0-
eDP@ <4> EDP_CPU_LANE_P1 LANE1P TXE0-
EDP_CPU_LANE_P0 4 5 EDP_CPU_R_LANE_P0 EDP_CPU_LANE_N1 10
<4> EDP_CPU_LANE_N1 LANE1N +3VS_RT

DP
EDP_CPU_LANE_N0 3 6 EDP_CPU_R_LANE_N0 29 LVDS_B_R_TXOUT1+
EDP_CPU_AUX 4 TXE1+ 30 LVDS_B_R_TXOUT1-
EDP_CPU_LANE_P1 2 7 EDP_CPU_R_LANE_P1 <4> EDP_CPU_AUX AUX-CH_P TXE1-
EDP_CPU_LANE_N1 1 8 EDP_CPU_R_LANE_N1 EDP_CPU_AUX# 3 LCD_EDID_CLK RT32 1 LVDS@ 2 4.7K_0402_5%
<4> EDP_CPU_AUX# AUX-CH_N 27 LVDS_B_R_TXOUT2+
RT34 1 2 1K_0402_1% 1 TXE2+ 28 LVDS_B_R_TXOUT2- LCD_EDID_DATA RT33 1 LVDS@ 2 4.7K_0402_5%
<8> EDP_HPD DP_HPD TXE2-
0_0804_8P4R_5%
1

<to connector> 23 TT6 PAD~D


eDP@ RT35 TXE3+ 24 TT7 PAD~D
RP39 100K_0402_5% TXE3- +SWR_VDD
EDP_CPU_R_LANE_P1 4 5 LVDS_B_TXOUT1+ BKL_PWM_CPU 21
<4,8> BKL_PWM_CPU PWMIN
EDP_CPU_R_LANE_N1 3 6 LVDS_B_TXOUT1- PAD~D TT1 2 46 LCD_EDID_CLK
2

TESTMODE MIICSCL1 LCD_EDID_CLK <19>


EDP_CPU_R_LANE_P0 2 7 LVDS_B_TXOUT0+ 1 2 12 45 LCD_EDID_DATA LCD_EDID_DATA <19> RT37 1 LVDS@ 2 4.7K_0402_5% CIICSCL
DP_REXT MIICSDA1

OTHERS
EDP_CPU_R_LANE_N0 1 8 LVDS_B_TXOUT0- RT36 12K_0402_1% RT38 1 LVDS@ 2 4.7K_0402_5% CIICSDA
20 DP_ENVDD
PANEL_VCC DP_ENVDD <19>
19 INVTPWM INVTPWM <19>
0_0804_8P4R_5% MIIC_SCL 48 PWMOUT 44 TS_BKOFF#
MIIC_SDA 47 MIICSCL0 BL_EN DP_ENVDD RT39 1 LVDS@ 2 100K_0402_5%
MIICSDA0

@ TT2 CIICSCL 13 6
CIICSDA 14 CIICSCL1 DP_GND
@ TT3 CIICSDA1 16
EDP_CPU_AUX RT43 1 eDP@ 2 0_0402_5% EDP_CPU_R_AUX RT45 1 eDP@ 2 0_0402_5% LVDS_B_TXOUT2+ GND

GND
B EDP_CPU_AUX# RT44 1 eDP@ 2 0_0402_5% EDP_CPU_R_AUX# RT46 1 eDP@ 2 0_0402_5% LVDS_B_TXOUT2- 49 B
PAD
RTD2136N-CGT_QFN_48P_DP/LVDS_CTRL

LVDS_B_R_TXOUT1+ RT53 1 LVDS@ 2 0_0402_5% LVDS_B_TXOUT1+


LVDS_B_TXOUT1+ <19>
LVDS_B_R_TXOUT1- RT54 1 LVDS@ 2 0_0402_5% LVDS_B_TXOUT1-
LVDS_B_TXOUT1- <19>
LVDS_B_R_TXOUT0+ RT55 1 LVDS@ 2 0_0402_5% LVDS_B_TXOUT0+ PIN15
LVDS_B_R_TXOUT0- RT56 1 LVDS@ 2 0_0402_5% LVDS_B_TXOUT0-
LVDS_B_TXOUT0+ <19> PIN16 Accept voltage input (high level)
LVDS_B_TXOUT0- <19>
EDP_HPD RT49 1 eDP@ 2 0_0402_5% EDP_HPD_PANEL RT51 1 eDP@ 2 0_0402_5% EDP_HPD_PANEL_R EDP_HPD_PANEL_R <19>
2132S TL_ENVDD 2132S 3.3V
BKL_PWM_CPURT50 1 eDP@ 2 0_0402_5% INVTPWM <LVDS panel>
2132R +LCD_VDD * 2132R 1.5~3.3V
LVDS_B_R_TXOUT2+ RT47 1 LVDS@ 2 0_0402_5% LVDS_B_TXOUT2+
LVDS_B_TXOUT2+ <19>
LVDS_B_R_TXOUT2- RT48 1 LVDS@ 2 0_0402_5% LVDS_B_TXOUT2-
LVDS_B_TXOUT2- <19>
* Version R internal Power Switch, can * Version R has internal level shifter, remove
output 1A, Rds(on)=0.2 ohm level shifter circuit on AMD platform
INVTPWM

LVDS@
RT41 1 @ 2 0_0402_5% R163
Different between 2132S and 2132R
100K_0402_5%
1

12/20
CT41
RT42 1 eDP@ 2 100K_0402_5% +3VS 1 @ 2 2132S 2132R
0.1U_0402_16V7K
2
5

LVDS@ 1. Support SWR mode 1. Support LDO mode and SWR mode
VCC

TS_BKOFF# 1
IN1
2. Internal ROM
A 4 A
<RTS2132> ENBKL 2 OUT EC_TS_BKOFF# <19> <LVDS Panel> 3. Support LCD_VDD(internal Power switch)
GND

<8> ENBKL IN2


<PCH CTRL> 4. Integrates Level shifter
UT6 11/28
PD 100K on LVDS page
3

MC74VHC1G08DFT2G_SC70-5

Security Classification Compal Secret Data Compal Electronics, Inc.


RT52 1 eDP@ 2 0_0402_5% 2013/3/1 2015/3/1 Title
Issued Date Deciphered Date
LVDS Translator-RTD2132R
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-B181P 0.5
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 25, 2014 Sheet 18 of 62
5 4 3 2 1
5 4 3 2 1

WWW.AliSaler.Com W=60mils
INVPWR_B+ B+
W=60mils

12/20 @EMI@
LVDS Power DP_ENVDD RG5 1 LVDS@ 2 0_0603_5% LCD_CLK 0_0805_5% 2 1 L1

+3VS LCD_DATA @EMI@ 0_0805_5%


Layout trace 40mil 2 1 L2
C4948 U4113 1 1
1 2 5 1 +LCDVDD @RF@C119
@RF@C119 @RF@C120
@RF@C120 1 1
IN OUT 10P_0402_50V8J 10P_0402_50V8J @EMI@ C117 C118
D SM010014520 3000ma D
1U_0402_6.3V4Z 2 680P_0402_50V7K 68P_0402_50V8J
12/20 GND RG1 2 2 220ohm@100mhz
RG3 1 @ 2 0_0402_5% 4 3 2 @ 1 1 1 1
2 2 DCR 0.04
<18> DP_ENVDD EN OC +3VS
1 CG2 CG3 @RF@
SY6288C20AAC_SOT23-5 0_0402_5% C555

4.7U_0603_6.3V6K

0.1U_0402_16V7K
R172 1 eDP@ 2 0_0402_5% CG1 100P_0402_50V8J
<8> ENVDD_CPU 2 2 2
1500P_0402_50V7K
2 +5VS +3VS

1 1
RF@ RF@
C139 C140
0.1U_0402_10V6K 0.1U_0402_10V6K
2 2
LCD/LED PANEL Conn.
JLVDS1
1
2 1
3 2
INVPWR_B+ 3
4
<18> EDP_HPD_PANEL_R 4
5
6 5
+LCDVDD 6
C +3VS 7 C
INVTPWM 8 7
<18> INVTPWM 8
DISPOFF# 9
10 9
+5VS 10
+3VS 11
LA2 1 2 FBMA-L10-160808-301LMT_2P D_MIC_L_DATA 12 11
Touch <26> D_MIC_DATA
<26> D_MIC_CLK
LA1 1 2 FBMA-L10-160808-301LMT_2P D_MIC_L_CLK 13
14
12
13
<8> CAMERA_ON 14
15
USB20_P6_R 16 15
USB20_N6_R 17 16
18 17
LCD_EDID_CLK R168 1 short@ 2 0_0402_5% LCD_CLK 19 18
+3VS <18> LCD_EDID_CLK 19
D12 <18> LCD_EDID_DATA LCD_EDID_DATA R169 1 short@ 2 0_0402_5% LCD_DATA 20
R166 LID_SW# 1 2 21 20
EC_TS_BKOFF# 1 2 DISPOFF# JTS1 22 21
<18> EC_TS_BKOFF# <18> LVDS_B_TXOUT2+ 22
CH751H-40PT_SOD323-2 1 23
1 <18> LVDS_B_TXOUT2- 23
3.3K_0402_5% R175 1 2 3.3K_0402_5% LID_SW#_D 2 <18> LVDS_B_TXOUT1+ 24
<9> TOUCH_RST# 2 24
1

1 3 25
<9> TOUCH_DET# 3 <18> LVDS_B_TXOUT1- 25
R167 4 26
4 <18> LVDS_B_TXOUT0+ 26
@ C122 USB20_N5_TS 5 27
100K_0402_5% <10> USB20_N5_TS 5 <18> LVDS_B_TXOUT0- 27
220P_0402_50V7K USB20_P5_TS 6 28
2 <10> USB20_P5_TS 6 <18> LVDS_B_CLKP 28
7 29
<18> LVDS_B_CLKN
2

8 GND 30 29
GND 30

2
31
<18> LVDS_A_TXP2 31
D5 ACES_50208-00601-P01 32
D2 <18> LVDS_A_TXN2 32
PESD5V0U2BT_SOT23-3 CONN@ 33
LID_SW# 1 2 34 33
B <32,43> LID_SW# @ESD@ <18> LVDS_A_TXP1 34 B
CH751H-40PT_SOD323-2 35
SCA00000U10 <18> LVDS_A_TXN1 35
36

1
37 36
<18> LVDS_A_TXP0 37
38
<18> LVDS_A_TXN0 38
39
40 39
Camera R170 1 @ 2 0_0402_5%
<18> LVDS_A_CLKP
41 40
<18> LVDS_A_CLKN 41
0_0402_5% 42
L12 EMI@ R82 1 short@ 2 PLT_ID2_R 43 42 45
<9,32> PLT_ID2 43 GND
1 2 USB20_P6_R <9> PLT_ID3 R86 1 short@ 2 PLT_ID3_R 44 46
<10> USB20_P6 1 2 44 GND
0_0402_5%
ACES_51540-04441-001
4 3 USB20_N6_R CONN@
<10> USB20_N6 4 3 D_MIC_L_DATA
DLW21HN900HQ2L_4P D_MIC_L_CLK

R171 1 @ 2 0_0402_5%

2
D3
PESD5V0U2BT_SOT23-3
@ESD@
GPIO92 GPIO93 SCA00000U10

1
PLT_ID2 PLT_ID3

A Rolo 14" 0 1 A

Reeses 15" 1 0
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2013/02/26 Deciphered Date 2015/07/08 Title
Raisinet 17" 1 1 LVDS Connector
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-B181P 0.5
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 25, 2014 Sheet 19 of 62
5 4 3 2 1
5 4 3 2 1

WWW.AliSaler.Com PCH_DPB_P0 0.1U_0402_16V7K 1 2 CG27 PCH_DPB_P0_C +3VS


<4> PCH_DPB_P0
PCH_DPB_N0 0.1U_0402_16V7K 1 2 CG28 PCH_DPB_N0_C
<4> PCH_DPB_N0
PCH_DPB_P1 0.1U_0402_16V7K 1 2 CG29 PCH_DPB_P1_C
<4> PCH_DPB_P1
PCH_DPB_N1 0.1U_0402_16V7K 1 2 CG30 PCH_DPB_N1_C
<CPU> <4> PCH_DPB_N1

1
PCH_DPB_P2 0.1U_0402_16V7K 1 2 CG31 PCH_DPB_P2_C RG47
<4> PCH_DPB_P2
PCH_DPB_N2 0.1U_0402_16V7K 1 2 CG32 PCH_DPB_N2_C
<4> PCH_DPB_N2
1M_0402_5%
PCH_DPB_P3 0.1U_0402_16V7K 1 2 CG33 PCH_DPB_P3_C
<4> PCH_DPB_P3

2
D PCH_DPB_N3 0.1U_0402_16V7K 1 2 CG34 PCH_DPB_N3_C D
<4> PCH_DPB_N3

2
1 6 HP_DETECT
+3VS <8> PCH_DDPB_HPD

5
6
7
8

5
6
7
8

20K_0402_5%
QG1A
1

1
ME2N7002D1KW-G 2N_SOT363-6

5
RG56 CM17 @
5V Level
220P_0402_50V7K

4
3
2
1

4
3
2
1
3 4 2
RP3 RP4

2
470_0804_8P4R_5% 470_0804_8P4R_5% QG1B
ME2N7002D1KW-G 2N_SOT363-6
12/20 Follow Intel HASWELL PDG Rev2.3

+HDMI_5V_OUT

PCH_DPB_N3_C RG59 1 @ 2 0_0402_5% HDMI_R_CK-


+3VS
LM13 EMI@ RG105
4 3 1 8 HDMI_SDATA
4 3 2 7 HDMI_SCLK
3 6 PCH_DDPB_CLK +3VS
1 2 4 5 PCH_DDPB_DAT
1 2
DLW21HN900HQ2L_4P 2.2K_0804_8P4R_5%
PCH_DPB_P3_C RG60 1 @ 2 0_0402_5% HDMI_R_CK+
C C

5
QG2B
PCH_DPB_P0_C RG61 1 @ 2 0_0402_5% HDMI_R_D0+ PCH_DDPB_CLK 4 3 HDMI_SCLK
<8> PCH_DDPB_CLK
LM14 EMI@ @ESD@ D4808 ME2N7002D1KW-G 2N_SOT363-6
1 2 HDMI_R_D0+ 9 1 HDMI_R_D0+
1 2
HDMI_R_D0- 8 2 HDMI_R_D0-
4 3 +3VS
4 3 HDMI_R_CK+ 7 4 HDMI_R_CK+
DLW21HN900HQ2L_4P
PCH_DPB_N0_C RG63 1 @ 2 0_0402_5% HDMI_R_D0- HDMI_R_CK- 6 5 HDMI_R_CK-

2
PCH_DPB_N1_C RG64 1 @ 2 0_0402_5% HDMI_R_D1-
3 PCH_DDPB_DAT 1 6 HDMI_SDATA
<8> PCH_DDPB_DAT
LM15 EMI@
4 3 TVWDF1004AD0_DFN9 ME2N7002D1KW-G 2N_SOT363-6
4 3 SC300002800 QG2A

1 2
1 2 5V PULL UP IN CONNECTER SIDE
DLW21HN900HQ2L_4P @ESD@ D4809
PCH_DPB_P1_C RG65 1 @ 2 0_0402_5% HDMI_R_D1+ 9 1

HDMI_SDATA 8 2 HDMI_SDATA
PCH_DPB_N2_C RG66 1 @ 2 0_0402_5% HDMI_R_D2-
HDMI_SCLK 7 4 HDMI_SCLK
B LM16 EMI@ B
4
4 3
3 HP_DETECT 6 5 HP_DETECT HDMI Conn.
1 2 JHDMI1
1 2 3 HP_DETECT 19
DLW21HN900HQ2L_4P 18 HP_DET
+HDMI_5V_OUT +5V
PCH_DPB_P2_C RG70 1 @ 2 0_0402_5% HDMI_R_D2+ TVWDF1004AD0_DFN9 17
SC300002800 HDMI_SDATA 16 DDC/CEC_GND
HDMI_SCLK 15 SDA
14 SCL
13 Utility
@ESD@ D4810 HDMI_R_CK- 12 CEC
HDMI_R_D1+ 9 1 HDMI_R_D1+ @ @ 11 CK-
W=40mils CK_shield

10P_0402_50V8J

10P_0402_50V8J
1 1 HDMI_R_CK+ 10
FG1 +HDMI_5V_OUT CK+
HDMI_R_D1- 8 2 HDMI_R_D1- CM26 CM27 HDMI_R_D0- 9
8 D0-
3 HDMI_R_D2+ 7 4 HDMI_R_D2+ HDMI_R_D0+ 7 D0_shield
OUT 2 2 HDMI_R_D1- 6 D0+
1 HDMI_R_D2- 6 5 HDMI_R_D2- 5 D1-
+5VS IN D1_shield
1 HDMI_R_D1+ 4 23
2 HDMI_R_D2- 3 D1+ GND1 22
GND 2 D2- GND2 21
CG46 3 HDMI_R_D2+ 1 D2_shield GND3 20
0.1U_0402_16V7K 2 D2+ GND4
AP2330W-7_SC59-3 TVWDF1004AD0_DFN9 CONCR_099A3AC19CBLBNF
SC300002800 CONN@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2011/06/29 Deciphered Date 2011/06/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDMI Conn/Level shift
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.5
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B181P
Date: Tuesday, March 25, 2014 Sheet 20 of 62
5 4 3 2 1
5 4 3 2 1

WWW.AliSaler.Com
WLAN WWAN WWAN_DISABLE RN16 1 2 0_0402_5% WWAN_FULL_PWR

+3V_WWAN
JMINI2
1
+3VDS <6> WWAN_DET# GND (Presence)
3 2
5 GND 3P3VAUX 4
+3V_PCH GND 3P3VAUX R1374
7 6 WWAN_FULL_PWR 2 WWAN@1
WWAN@ +3V_WWAN
<10> USB20_P5_WWAN USB_D+ FULL_CARD_PWR_OFF#

1
9 8 M_WXMIT_OFF# 10K_0402_5%
+3VS_WLAN +3VS_WLAN <10> USB20_N5_WWAN USB_D- W_DISABLE1#
RN3 11 10 LED_WWAN_LINK#
GND LED1#

1
10K_0402_5%
R130
JMINI1 100K_0402_5%

2
D D
<32> WLAN_WAKE# WLAN_WAKE# 1 12
3 1 2 13 AUDIO0 14
<9> WWANSSD_M2

2
RN13 1 @ 2 0_0402_5% 5 3 2 4 15 GND_WWAN AUDIO1 16
<8,32> PCH_PCIE_WAKE# 5 4 RSV (WAKE# /OD)) AUDIO2
MINI1_CLKREQ#_R 7 6 R1375 1 WWAN@2 30K_0402_5% WWAN_RSVD2 17 18
7 6 +3V_WWAN RSV(DPR) AUDIO3 (W_DISABLE#2) GPS_XMIT_OFF# <7,9>
9 8 19 20
9 8 GND IUM_RFU

2
11 10 Q4111 D22 USB3TXDN2_C_R 21 22 UIM_RST

G
<7> CLK_PCIE_MINI1# 11 10 USB3_TX- UIM_RESET
13 12 2N7002KW_SOT323-3 BAT54WS-7-F_SOD323-2 USB3TXDP2_C_R 23 24 UIM_CLK
<7> CLK_PCIE_MINI1 13 12 USB3_TX+ UIM_CLK
15 14 1 3 2 1 WLAN_TRANSMIT_OFF# <9> 25 26 UIM_DATA
15 14 16 USB3RXDN2_C 27 GND UIM_DATA 28 UIM_PWR

S
16 USB3RXDP2_C 29 USB3RX- UIM_PWR 30 1 RA37 2mSATA_DEVSLP1
USB3RX+ DEVSLP mSATA_DEVSLP1 <8,9>
31 32 0_0402_5%
17 CS20 2WWAN@
1 0.01U_0402_16V7K SATA_PRX_C_DTX_P3 33 GND GNSS0 34 WWAN@
17 <6> SATA_PRX_DTX_P3 PETn0/SATA_B+ GNSS1
11/28 19 18 CS25 2WWAN@
1 0.01U_0402_16V7K SATA_PRX_C_DTX_N3 35 36
19 18 <6> SATA_PRX_DTX_N3 PETn0/SATA_B- GNSS2
21 20 R264 1 2 100K_0402_5% 37 38
21 20 +3VS_WLAN GND GNSS3
23 22 PLT_RST# CS27 2WWAN@
1 0.01U_0402_16V7K SATA_PTX_C_DRX_N3 39 40
<10> PCIE_PRX_DTX_N4 23 22 <6> SATA_PTX_DRX_N3 PERn0/SATA_A- GNSS4
25 24 CS26 2WWAN@
1 0.01U_0402_16V7K SATA_PTX_C_DRX_P3 41 42
<10> PCIE_PRX_DTX_P4 25 24 <6> SATA_PTX_DRX_P3 PERn0/SATA_A+ PERST#
27 26 43 44
29 27 26 28 45 GND CLKREQ# 46
31 29 28 30 47 REFCLKN PEWake# 48
<10> PCIE_PTX_C_DRX_N4 31 30 REFCLKP Config_0 T155 @ PAD
<10> PCIE_PTX_C_DRX_P4 33 32 49 50
33 32 GND Config_1 T147 @ PAD
35 34 PAD @
@T152
T152 51 52
37 35 34 36 USB20_N3_R RN4 1 short@ 2 0_0402_5% 53 ANTCTL0 COEX3 54
37 36 USB20_N3 <10> PAD @
@T153
T153 ANTCTL1 COEX2
39 38 USB20_P3_R RN5 1 short@ 2 0_0402_5% 55 56
39 38 USB20_P3 <10> ANTCTL2 COEX1
41 40 57 58 SIM_DET
+3VS_WLAN 43 41 40 42 PLT_RST# R1409 1 2 0_0402_5% 59 ANTCTL3 SIM_DET 60
<6,8,23,30,32,33,43> PLT_RST# @
45 43 42 44 WL_LED_ALL# NGFF_WWAN_PEDET 61 RESET# SUSCLK 62
47 45 44 46 63 PEDET 3P3VAUX 64
47 46 GND 3P3VAUX
2

R85 49 48 65 66
51 49 48 50 NGFF_WWAN_USB3_OC 67 GND 3P3VAUX
51 50 PAD @
@T135
T135 OC_USB3
10K_0402_5% 52
53 52 69 68
54 GND1 GND2 GND1
1

BT_ON GND2
LOTES_APCI0018-P003H
FOX_AS0B226-S52QW-7H +3V_WWAN CONN@
CONN@
6

1
C C
2 RN6
<8> BT_OFF
10K_0402_5%
Q90A CS10
1

ME2N7002D1KW-G 2N_SOT363-6 12/20 2 1 USB3_TX2_C_P RS10 1 @ 2 0_0402_5% USB3TXDP2_C_R


<10> USB3_TX2_P

2
RN14
3

R91 1 @ 2 NGFF_WWAN_PEDET 0.1U_0402_16V7K LM4 EMI@


<6> mSATA_DET#
1 2 +3VDS 4 3
0_0402_5% 4 3

<40> SUSP 5 10K_0402_5%

1
D 1 2
Q90B 2 1 2
WLAN_DISABLE <32>
4

ME2N7002D1KW-G 2N_SOT363-6 Q4 G CS22 DLW21HN900HQ2L_4P


2N7002KW_SOT323-3 S 2 1 USB3_TX2_C_N RS5 1 @ 2 0_0402_5% USB3TXDN2_C_R
<10> USB3_TX2_N

3
1

R371 0.1U_0402_16V7K
1K_0402_5%
C69 UIM_CLK
2

1 2
+3VS_WLAN
1 C76
2

U5@
0.047U_0402_16V7K
G

18P_0402_50V8J
1 6 @
1 3 CH1 CH4
+3VDS 2
D

2 5 +3V_WWAN
Vn Vp
1
C85 Q28 3 4
0.1U_0402_16V4Z SI2305CDS-T1-GE3_SOT23-3 CH2 CH3
S DIO(BR) NUP4301MR6T1 TSOP-6 RS4 1 @ 2 0_0402_5% USB3RXDP2_C
2 <10> USB3_RX2_P
LM5 EMI@
JSIM1 C2 4 3
+3VS_WLAN 2 1 SIM_DET 1 2 470P_0402_50V8J 4 3
+3VS_WLAN NC DETECT
UIM_DATA 4 3 1 2
I/O NC +3V_WWAN 1 2
1

UIM_VPP 6 5 UIM_CLK DLW21HN900HQ2L_4P


VPP CLK
0.1U_0402_16V7K

RN7 RS9 1 @ 2 0_0402_5% USB3RXDN2_C


B <10> USB3_RX2_N B
CN3

1 1 10K_0402_5% 8 7 UIM_RST D9 @
CN2 GND RST 3
2

10 9 UIM_PWR 1
G

4.7U_0603_6.3V6K NC VCC 2

1
2 2 MINI1_CLKREQ# 1 3 MINI1_CLKREQ#_R 12 11
<7> MINI1_CLKREQ# GND GND
R83 DAN217T146_SC59-3
D

47K_0402_5% @ +3V_WWAN

0.1U_0402_10V6K

4.7U_0805_10V4Z
14 13
GND GND +3V_WWAN

C78

C77
Q5 1 1
2N7002KW_SOT323-3 16 15
2 GND GND WWAN@ WWAN@

0.01U_0402_16V7K

0.1U_0402_10V6K

4.7U_0805_10V4Z
RN15 1 @ 2 0_0402_5% 18 17
GND GND 2 2

C72 WWAN@

C73 WWAN@

C74 WWAN@
1 1 1 C75 C70 C71
T-SOL_159-1000302602 1 1 1

39P_0402_50V8J

39P_0402_50V8J

39P_0402_50V8J
CONN@
@ @ @
2 2 2
UIM_PWR 2 2 2
+3VS

+3VDS @ JP4102 +3V_WWAN


JUMP_43X118
1 2
1 2
1

R87 R88
2

47K_0402_5% 47K_0402_5% R81


D13
10K_0402_5% @WWAN@ WWAN@
2

M_WXMIT_OFF# 2 1 WWAN_TRANSMIT_OFF# <9>


WL_LED_ALL# <43>
1

CH751H-40PT_SOD323-2

6
04/23 HP
3

S
R84 G
<32> WWAN_DISABLE 1 @WWAN@
2 2 Q27 Q4112A
SI2305CDS-T1-GE3_SOT23-3 ME2N7002D1KW-G 2N_SOT363-6 2 SUSP
0.1U_0402_10V6K

WWAN_TRANSMIT_OFF# 5 220K_0402_1% @WWAN@


C79

02/13 HP 1

1
D
A Q4112B A
4

ME2N7002D1KW-G 2N_SOT363-6 @WWAN@


+3VDS
LED_WWAN_LINK# 2 7W

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2013/02/26 Deciphered Date 2015/07/08 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
WLAN
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.5
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B181P
Date: Tuesday, March 25, 2014 Sheet 21 of 62
5 4 3 2 1
5 4 3 2 1

WWW.AliSaler.Com JHDD

2.5" SATA HDD connector +5VS_HDD1 1


GND
<6> SATA_PTX_DRX_P0 C155 1 2 0.01U_0402_16V7K SATA_PTX_C_DRX_P0 2
C156 1 2 0.01U_0402_16V7K SATA_PTX_C_DRX_N0 3 A+
<6> SATA_PTX_DRX_N0 A-
4
C153 1 2 0.01U_0402_16V7K SATA_PRX_C_DTX_N0 5 GND
<6> SATA_PRX_DTX_N0 B-

10U_0603_6.3V6M

0.1U_0402_16V7K
+5VS C154 1 2 0.01U_0402_16V7K SATA_PRX_C_DTX_P0 6
<6> SATA_PRX_DTX_P0 B+

C150
1 1 7
GND

C149
0_0603_5%
D R201 1 short@ 2 D
+5VS_HDD1
0_0603_5% 8
R212 1 short@ 2 2 2 9 V33
10 V33
<9> HDD_DEVSLP0 V33
11
12 GND
13 GND
14 GND
15 V5
+5VS_HDD1 V5
16
17 V5
18 GND
19 Reserved
20 GND
21 V12 23
22 V12 GND 24
V12 GND

ALLTO_C166KS-12231-L
CONN@

C C
+5VS_ODD
+5VS Q34 Pleace near ODD Connector
SI2305CDS-T1-GE3_SOT23-3
+5VS_ODD

S
3 1

D
0.1U_0402_16V7K

1
1

CS21

G
1

2
C4820

1000P_0402_50V7K

0.1U_0402_25V6K

10U_0805_10V6K
R5078 1 1
10U_0603_6.3V6M 10K_0402_5% CS23 CS24 1 1 1
2

CS13
2

1U_0603_10V6K

CS16

CS12
2

2 2

10U_0603_6.3V6M
2 2 2
R448
ODD_EN# 1 2

100K_0402_5% 1
@ JODD1
6

C151
Q63A 4.7U_0402_6.3V6M 1
ME2N7002D1KW-G 2N_SOT363-6 2 CS11 2 1 0.01U_0402_16V7K SATA_PTX_C_DRX_P1 2 GND
<6> SATA_PTX_DRX_P1 A+
2 <6> SATA_PTX_DRX_N1 CS14 2 1 0.01U_0402_16V7K SATA_PTX_C_DRX_N1 3
<9> ODD_EN A-
B 4 B
+5VS_ODD CS15 2 1 0.01U_0402_16V7K SATA_PRX_C_DTX_N1 5 GND
1

<6> SATA_PRX_DTX_N1 CS18 2 1 0.01U_0402_16V7K SATA_PRX_C_DTX_P1 6 B-


<6> SATA_PRX_DTX_P1 7 B+
GND
2

R5047 8
470_0603_5% 9 DP
+5VS_ODD +5V
10
ODD_DA# 11 +5V
1

<9> ODD_DA# 12 MD 14
13 GND GND 15
GND GND
3

12/21
Q63B 1
ME2N7002D1KW-G 2N_SOT363-6 CS17 SANTA_201902-1
ODD_EN# 5 0.1U_0402_25V6K CONN@
ESD@
2
4

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


12/20 Customer change GPIO table 2013/02/26 2015/07/08 Title
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ODD/SATA Conn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.5
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B181P
Date: Tuesday, March 25, 2014 Sheet 22 of 62
5 4 3 2 1
5 4 3 2 1

WWW.AliSaler.Com
+LAN_VDD_3V3 Rising time
+3VDS
+VDDREG

4.7U_0603_6.3V6K
+LAN_VDD_1V0

0.1U_0402_16V7K
Q35   need>0.5mS and <100mS 1 1

CL8

CL9
SI2305CDS-T1-GE3_SOT23-3
CL17 & CL18 close UL1 Pin22
2 2 CL19 & CL20 close UL1 Pin30

S
3 1 LL1

D
+LAN_VDD_3V3
+LAN_REGOUT 1 2

1U_0402_6.3V6K

1U_0402_6.3V6K
2.2UH +-5% NLC252018T-2R2J-N

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K
4.7U_0603_6.3V6K

0.1U_0402_16V7K
0.1U_0402_16V7K
G
1 1 1 1 1 1 1 1 1 1

2
@ @ @ @ @ @

CL12

CL13
CL10 CL14 CL15 CL16 CL17 CL18 CL19 CL20

1500P_0402_50V7K 2 2 2 2 2 2 2 2 2 2

D
11/28 CL8& CL9 close to UL1: Pin 23 D
RL28
2 1 +LAN_VDD_3V3
CL12 & CL13 close LL2
<32> LAN_PWR_EN_EC# Place CL14~CL16 close UL1 Pin 3, 8 , 22
10K_0402_5%

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
1

0.1U_0402_16V7K

0.1U_0402_16V7K
CL21 1 1 1 1
0.1U_0402_16V7K
2 CL22 @ CL23 CL24 CL25 @
2 2 2 2

XTLI
+LAN_VDD_3V3 QL1
2N7002K_SOT23-3 2 1 XTLO
CL22 & CL23 close to UL1: Pin 11,32 1M_0402_5% RL31
LED_LINK_LAN#_R 1 3 LED_LINK_LAN#

S
1

<9,10> LED_LINK_LAN#_R
@ CL24 close to UL1: Pin 32
RL40
10K_0402_5% CL25 close to UL1: Pin 11

G
+LAN_VDD_3V3=40mil

2
2

3
YL1
+LAN_VDD_1V0 +LAN_VDD_3V3
L +VDDREG=40mil

27P_0402_50V8J

27P_0402_50V8J
S

LAN_CLKREQ# 3 1 LAN_CLKREQ#_R +LAN_VDD_3V3 1 1

OSC

OSC
CL26 CL27
@ QL2 +VDDREG 1 short@ 2 +LAN_REGOUT=60mil
2N7002K_SOT23-3 RL32 0_0603_5% +LAN_VDD_3V3
G

GND

GND
2 2
2

22

30

11

32

23

4
1

8
UL1
12/20 @ @

DVDD10

AVDD10

AVDD10

AVDD10

AVDD33

AVDD33

VDDREQ
RL49 RL48 LAN_MDIP0 1 12 LAN_CLKREQ#_R RL34 2 short@ 1 0_0402_5% LAN_CLKREQ# <7> 25MHZ_20PF_FSX3M-25.M20FDO
Avoid turn on issue when S3 0_0402_5% 0_0402_5% MDIP0 CLKREQB
LAN_MDIN0 2 17 PCIE_PRX_C_DTX_P3 0.1U_0402_10V7K 2 1 CL28 PCIE_PRX_DTX_P3
PCIE_PRX_DTX_P3 <10>
2

MDIN0 HSOP
LAN_MDIP1 4 18 PCIE_PRX_C_DTX_N3 0.1U_0402_10V7K 2 1 CL29 PCIE_PRX_DTX_N3
MDIP1 HSON PCIE_PRX_DTX_N3 <10>
C +LAN_VDD_3V3 C
+LAN_VDD_3V3 +3VS LAN_MDIN1 5 21 LANWAKEB RL33 1 @ 210K_0402_5%
MDIN1 LANWAKEB RL43 1 short@ 2 0_0402_5% LANWAKEB_R
LAN_MDIP2 6 24 +LAN_REGOUT RL47 1 @ 210K_0402_5% +LAN_VDD_3V3
MDIP2 REGOUT
LAN_MDIN2 7 25 LED2 RL41 1 @ 2 0_0402_5%
MDIN2 LED2 TL2
LAN_MDIP3 9 26 LED_LINK_LAN#
MDIP3 LED1/GPO
LAN_MDIN3 10 27 LAN_ACT# LAN_ISOLATEB# 2 1 +3VS
MDIN3 LED0 TL1
1K_0402_5% RL29
PCIE_PTX_C_DRX_P3 13
<10> PCIE_PTX_C_DRX_P3 HSIP

2
+LAN_VDD_3V3
PCIE_PTX_C_DRX_N3 14 RL30
<10> PCIE_PTX_C_DRX_N3 HSIN
EC_PME# <9>

1
<7> CLK_PCIE_LAN CLK_PCIE_LAN 15 15K_0402_5%
REFCLK_P RL45

1
<7> CLK_PCIE_LAN# CLK_PCIE_LAN# 16 4.3K_0402_5%
REFCLK_n QL3

1
<6,8,21,30,32,33,43> PLT_RST# PLT_RST# 19 C MMBT3904_SOT23-3

2
PERSTB 2

1
0_0402_5% 2 @ 1 RL35 LAN_ISOLATEB# 20 B
TL4 ISOLATEB

1
E RL46

3
XTLI 28 RL44 @ 0_0402_5%
CKXTAL1
2K_0402_5%
XTLO 29

2
CKXTAL2

2
1 2 RSET 31 33 LANWAKEB_R +LAN_VDD_3V3
RL36 2.49K_0402_1% RSET GND

RTL8161GSH-CG_QFN32_4X4

1
10K_0402_5%
RL37
RJ-45 CONN.
SP050005L00 Footprint
TSL1

2
JRJ45
+V_DAC 1 24 CL31 1 2 0.01U_0402_50V7K LED_LINK_LAN# RL38 1 2 510_0402_5% LED_LINK_LAN#_CONN 12
B
LAN_MDIP3 2 TCT1 MCT1 23 RJ45_TX3+ Green LED- B
LAN_MDIN3 3 TD1+ MX1+ 22 RJ45_TX3- RPL1 1 2 11
TD1- MX1- +LAN_VDD_3V3 Green LED+
4 5 @ 680P_0402_50V7K CL30
4 21 CL32 1 2 0.01U_0402_50V7K 3 6 RJ45_TX3- 8
LAN_MDIP2 5 TCT2 MCT2 20 RJ45_TX2+ 2 7 PR4-
LAN_MDIN2 6 TD2+ MX2+ 19 RJ45_TX2- 1 8 RJ45_TX3+ 7
TD2- MX2- PR4+
7 18 CL33 1 2 0.01U_0402_50V7K 75_0804_8P4R_1% RJ45_RX1- 6
LAN_MDIP1 8 TCT3 MCT3 17 RJ45_RX1+ PR2-
LAN_MDIN1 9 TD3+ MX3+ 16 RJ45_RX1- RJ45_TX2- 5
TD3- MX3- PR3-
2
10 15 CL36 1 2 0.01U_0402_50V7K CL34 RJ45_TX2+ 4
LAN_MDIP0 11 TCT4 MCT4 14 RJ45_TX0+ SE167100J80 PR3+
LAN_MDIN0 12 TD4+ MX4+ 13 RJ45_TX0- 10P_1808_3KV RJ45_RX1+ 3
TD4- MX4- 1 PR2+
1 RJ45_TX0- 2
PR1-
3

EMI@ 13
NS892407 1G C4966 LL2 1 2 10K_0402_5% RJ45_TX0+ 1 SHLD2 14
1 +LAN_VDD_3V3 PR1+ SHLD1
EMI@ SP050006800 ESD@ DL2 120P_0402_50V8
CL38 2 LAN_ACT# RL39 1 2 510_0402_5% LAN_ACT#_R 10
YSLC05CH_SOT23-3 LANGND Yellow LED-
0.1U_0402_16V7K
2 SCA00000U10 1 2 9
+LAN_VDD_3V3 Yellow LED+
@ 680P_0402_50V7K CL35
SANTA_130456-611

2
CONN@
1

DL1 @ESD@

YSLC05CH_SOT23-3
SCA00000U10

1
@ESD@ @ESD@
SC300001G00 SC300001G00
DL4811 DL4812
A LAN_MDIP2 6 3 LAN_MDIN3 LAN_MDIP0 6 3 LAN_MDIN1 A
I/O4 I/O2 I/O4 I/O2

+3VDS 5 2 +3VDS 5 2
VDD GND VDD GND

LAN_MDIN2 4 1 LAN_MDIP3 LAN_MDIN0 4 1 LAN_MDIP1


I/O3 I/O1 I/O3 I/O1
AZC099-04S.R7G_SOT23-6 AZC099-04S.R7G_SOT23-6
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2013/02/26 Deciphered Date 2011/06/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LAN RTL8161GSH
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.5
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B181P
Date: Tuesday, March 25, 2014 Sheet 23 of 62
5 4 3 2 1
5 4 3 2 1

WWW.AliSaler.Com

D D

C C

B B

A A

Security Classification Compal Secret Data


Issued Date 2011/06/29 Deciphered Date 2011/06/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Card Reader RTS5237
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-B181P 0.5
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 25, 2014 Sheet 24 of 62
5 4 3 2 1
A B C D E

WWW.AliSaler.Com
USB3.0 RS7 @ 0_0402_5%
1 2 USB20_P2_C
<10> USB20_P2 CS1
LM3 EMI@ USB3_TX0_P 2 1 USB3_TX0_C_P RS1 1 @ 2 0_0402_5% USB3TXDP0_C_R DM1 @ESD@
<10> USB3_TX0_P
1 2 2 USB20_N2_C
1 2 LM1 EMI@ 1 +USB_VCCA
0.1U_0402_16V7K
4 3 3 USB20_P2_C
4 3 4 3 JUSB1
4 3 YSLC05CH_SOT23-3 1
DLW21HN900HQ2L_4P 1 2 SCA00000U10 USB20_N2_C 2 VBUS
1 2 USB20_N2_C 1 2 USB20_P2_C 3 D-
<10> USB20_N2 CS2 D+
RS8 @ 0_0402_5% DLW21HN900HQ2L_4P 4
USB3_TX0_N 2 1 USB3_TX0_C_N 1 2 USB3TXDN0_C_R USB3RXDN0_C 5 GND
1 <10> USB3_TX0_N @ StdA-SSRX- 1
RS2 0_0402_5% USB3RXDP0_C 6 10
0.1U_0402_16V7K 7 StdA-SSRX+ GND 11
DM2 ESD@ GND GND
USB3TXDN0_C_R 8 12
USB3RXDN0_C 1 1 109 USB3RXDN0_C USB3TXDP0_C_R 9 StdA-SSTX- GND 13
StdA-SSTX+ GND
RS3 @ 0_0402_5% USB3RXDP0_C 2 2 98 USB3RXDP0_C ACON_TAR2N-9R6391
1 2 USB3RXDP0_C CONN@
<10> USB3_RX0_P USB3TXDN0_C_R 4 4 77 USB3TXDN0_C_R
LM2 EMI@
4 3 USB3TXDP0_C_R 5 5 66 USB3TXDP0_C_R
4 3
USB3.0 need support 2.5A 3 3
change USB PWR SW SA00003TV00 1
1 2
2
8
low active DLW21HN900HQ2L_4P
1 2 USB3RXDN0_C IP4292CZ10-TB
+5VDS +USB_VCCA <10> USB3_RX0_N SC300002800
RS6 @ 0_0402_5%

W=100mils US1 W=100mils


1 8
2 GND NC 7
IN VOUT 1 1 1
3 6 CS4 CS5
IN VOUT

1000P_0402_50V7K

0.1U_0402_16V7K
EPAD

4 5 @ + C1572
1
<8,32,40,43,48> SLP_S4# EN FLG
CS3 2 2 150U_B2_6.3VM_R45M
AP2311MPG-13_MSOP8 2
0.1U_0402_16V7K
9

2
+USB_VCCA
CS8
<10> USB3_TX1_P USB3_TX1_P2 1 USB3_TX1_C_P RS21 1 @ 2 0_0402_5% USB3TXDP1_C_R JUSB2
1
0.1U_0402_16V7K LM8 EMI@ USB20_N1_C 2 VBUS
4 3 USB20_P1_C 3 D-
4 3 4 D+
DM3 @ESD@ USB3RXDN1_C 5 GND
1 2 2 USB20_N1_C USB3RXDP1_C 6 StdA-SSRX- 10
1 2 1 7 StdA-SSRX+ GND 11
CS7 DLW21HN900HQ2L_4P 3 USB20_P1_C USB3TXDN1_C_R 8 GND GND 12
2 2
USB3_TX1_N2 1 USB3_TX1_C_N 1 2 USB3TXDN1_C_R USB3TXDP1_C_R 9 StdA-SSTX- GND 13
<10> USB3_TX1_N @ StdA-SSTX+ GND
RS22 0_0402_5% YSLC05CH_SOT23-3
0.1U_0402_16V7K SCA00000U10 ACON_TAR2N-9R6391
CONN@

RS20 1 @ 2 0_0402_5% USB20_P1_C


<10> USB20_P1 DM4 ESD@
LM7 EMI@ RS19 1 @ 2 0_0402_5% USB3RXDP1_C USB3RXDN1_C 1 1 109 USB3RXDN1_C
<10> USB3_RX1_P
1 2
1 2 LM6 EMI@ USB3RXDP1_C 2 2 98 USB3RXDP1_C
4 3
4 3 4 3 USB3TXDN1_C_R 4 4 77 USB3TXDN1_C_R
4 3
DLW21HN900HQ2L_4P 1 2 USB3TXDP1_C_R 5 5 66 USB3TXDP1_C_R
1 2 USB20_N1_C 1 2
<10> USB20_N1 @
RS17 0_0402_5% DLW21HN900HQ2L_4P 3 3
1 @ 2 USB3RXDN1_C
<10> USB3_RX1_N 8
RS18 0_0402_5%

IP4292CZ10-TB
SC300002800

3 3

RS24 1 2 0_0402_5% USB20_N0_C

USB2.0 <10> USB20_N0 @ USB20_N0_C <43>


LM9 EMI@
1 2
1 2

4 3
4 3
DLW21HN900HQ2L_4P
1 @ 2 USB20_P0_C
<10> USB20_P0 RS23 USB20_P0_C <43>
0_0402_5%

RS25 1 @ 2 0_0402_5% USB20_N7_C


<10> USB20_N7 USB20_N7_C <43>
LM10 EMI@
1 2
1 2

4 3
4 3
DLW21HN900HQ2L_4P
1 @ 2 USB20_P7_C
<10> USB20_P7 USB20_P7_C <43>
RS27 0_0402_5%

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2013/02/26 Deciphered Date 2015/07/08 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
USB 3.0
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C 0.5
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B181P
Date: Tuesday, March 25, 2014 Sheet 25 of 62
A B C D E
5 4 3 2 1

WWW.AliSaler.Com +DVDD
+3VS

1 short@ 2
+DVDD +DVDD_IO

1 2
+3VS +1.5VS_AVDD

1 2
+1.5VS

1
LA3 LA5

.1U_0402_16V7K
CA43

10U_0603_6.3V6M
CA40

.1U_0402_16V7K
CA41

10U_0603_6.3V6M
CA44

.1U_0402_16V7K
CA52

4.7U_0603_6.3V6K
CA53
@ RA31 RA30 SUPPRE_ KC FBMA-10-100505-101T 0402 SUPPRE_ KC FBMA-10-100505-101T 0402
UA1 10K_0402_5% 0_0402_5% 1 1 1 1 PCB Footprint = R_0402 1 2 PCB Footprint = R_0402

20 1 +DVDD

2
19 MIC1_R DVDD 9
MIC1_L DVDD_IO +DVDD_IO 2 2 2 2 Place near Pin9 2 1
CA45 1 2 4.7U_0402_6.3V6M 18 26 EAPD
EXT_MIC_L RA28 1 short@ 2 0_0402_5% CA39 1 2 4.7U_0402_6.3V6M MICL_C 17 MIC2_R AVDD1 40
+AVDD_CODEC Place near Pin1
MIC2_L AVDD2 +1.5VS_AVDD Place near Pin40
REC_MUTE_LED_CTR 31 41 +5VS_PVDD
MUTE_LED_CNTR 30 MIC1_VREFO_L PVDD1 46
<43> MUTE_LED_CNTR MIC1_VREFO_R PVDD2

1
+MIC2_VREFO 29 GNDA
D
RA40 MIC2_VREFO D
12/20 @ 0_0402_5% 23 45 SPK_R+ SLP_S3#
LINE2_R SPK_OUT_R+ <8,32,35,40,41,49,52> SLP_S3#
24 44 SPK_R-
LINE2_L SPK_OUT_R-

2
+3VS +AVDD_CODEC
16 42 SPK_L+
<INT SPK> +5VS
MONO_OUT SPK_OUT_L+ 43 SPK_L- UA2
SPK_OUT_L-
1

PC_BEEP 12 CA46 RA32 W=40Mil 5


R134 PCBEEP 1U_0402_6.3V6K 0_0402_5% 1 VOUT
0_0402_5% 10 33 HPOUT_R RA65 1 2 75_0402_5% 1 2 1 short@ 2 HPOUT_R_1 VIN
<6> HDA_SYNC_AUDIO SYNC HPOUT_R 32 HPOUT_L RA66 1 2 75_0402_5% 1 2 1 short@ 2HPOUT_L_1 4 @
HDA_RST_AUDIO# 11 HPOUT_L RA33 1 @ 2 3 BYPASS CA28 CA29 C87 D11
<6> HDA_RST_AUDIO#
2

RESET# EN

2
CPVDD CA47 1U_0402_6.3V6K 0_0402_5% RA68 RA67 RA20 1

0.1U_0402_25V6

10U_0805_10V6K

680P_0603_50V7K

AZ2015-02S_SOT23-3
RA35 1 @ 2 4.7K_0402_5% 5 10K_0402_5% 2

22K_0402_5%

22K_0402_5%
2 +3VS SDATA_OUT HDA_SDOUT_AUDIO <6> GND 2

1
8 SDATA_IN RA36 1 2 33_0402_5% @
SDATA_IN HDA_SDI0 <6>
CA48 CA49 1 2 10U_0603_6.3V6M ALDO_CAP 7 @ @ 1 HPA01091DBVR SOT23 5P
LDO3-CAP

1
6 C88 2
4.7U_0603_6.3V6K HDA_BITCLK_AUDIO <6>

2
1 CA54 1 2 2.2U_0402_6.3V6M ACPVEE 34 BCLK CA31 1

1
CPVDD 36 CPVEE 22 680P_0603_50V7K 0.1U_0402_25V6

2
CBN 35 CPVDD LINE1_L 21 2
CA55 1 2 2.2U_0402_6.3V6M CBP 37 CBN LINE1_R 48 EAPD
CBP SPDIFO/GPIO2 GNDA GNDA
15 JDREF RA38 2 1 20K_0402_1% GNDA GNDA GNDA GNDA GNDA
2 JDREF 28 AVREF CA56 2 1 .1U_0402_16V7K
<19> D_MIC_DATA GPIO0/DMIC_DATA VREF
EMI@ 1 LA6 2 D_MIC_CLK_R 3 27 CA57 1 2 10U_0603_6.3V6M
<19> D_MIC_CLK GPIO1/DMIC_CLK LDO1_CAP +5VS_PVDD +5VS
D_MIC_DATA S SUPPRE_CHILISIN SBY100505T-301Y-N 0402 39 CA58 1 2 10U_0603_6.3V6M
LDO2_CAP LA7
D_MIC_CLK_R HP_SENSE# RA42 1 2 39.2K_0402_1% SENSEA 13 25 R174 1 2 100K_0402_5% 1 2
<43> HP_SENSE# SENSE_A AVSS1
MIC_JD RA39 2 1 20K_0402_1% SENSEB 14 38 FBMA-L11-201209601LMA20T_2P 600ohms @100MHz 2A
SENSE_B AVSS2

.1U_0402_16V7K
CA60

.1U_0402_16V7K
CA61

10U_0603_6.3V6M
CA62
10U_0603_6.3V6M
CA63
1 C125 1 C126 4 GNDA 1 1 2 2
P/N: SM01000EE00
@RF@ @RF@ 47 DVSS 49
+1.5VS +DVDD PDB Thermal Pad
10P_0402_50V8J

10P_0402_50V8J

2 2 ALC3227-CG_MQFN48P_6X6 AVREF CA59 1 2 2.2U_0402_6.3V6M 2 2 1 1


1
RA44
2.2K_0402_5% 1K_0402_5%
C C
RA45 GNDA
2 2

GNDA
2
B

QA1
E

HDA_RST_AUDIO# 3 1 PD#
C

MMBT3904WH_SOT323-3
Speaker Connector
1

SB000008E10

1 2 10K_0402_5% Power down (PD#) power stage for save power


<30,32> EC_MUTE#
DA2
CH751H-40PT_SOD323-2
RA46 0V: Power down power stage
3.3V: Power up power stage
 RA47/RA48/RA49/RA50 close to UA1 SPK conn
2

REC_MUTE_CTRL_KB <28>
SPK signal width=40mil
SM010007Z00 JSPKR1
SPK_R- EMI@ RA47 1 2 FBMA-L11160808601LMA10T_2P SPK_R-_CONN 4 6
4 GND

6
QA2A SPK_R+ EMI@ RA48 1 2 FBMA-L11160808601LMA10T_2P SPK_R+_CONN 3 5
+AVDD_CODEC SPK_L- EMI@ RA49 1 2 FBMA-L11160808601LMA10T_2P SPK_L-_CONN 2 3 GND
ME2N7002D1KW-G 2N_SOT363-6 SPK_L+ EMI@ RA50 1 2 FBMA-L11160808601LMA10T_2P SPK_L+_CONN 1 2
REC_MUTE_LED_CTR 2 1
1

SPK_R+_CONN SPK_L+_CONN ACES_88231-0400


R173 CONN@

1
1

220P_0402_50V7K

220P_0402_50V7K

220P_0402_50V7K

220P_0402_50V7K
2.2K_0402_5% SPK_R-_CONN SPK_L-_CONN
RA59
U4114

2
C10 2 1 1U_0402_6.3V6K +AVDD_CODEC 10K_0402_5% @ESD@ @ESD@ 1 1 1 1
2

@EMI@ C4949

@EMI@ C4950

@EMI@ C4951

@EMI@ C4952
18 8 D6 D7
17 CPP TEST1 7 MESC5V02BD03_SOT23-3 MESC5V02BD03_SOT23-3

2
CPN TEST2
HPOUT_L_1 C16 2 1 1U_0402_6.3V6K 1 12 2 2 2 2
1 RA29 2 0_0402_5% C18 2 1 1U_0402_6.3V6K 2 LEFTINM VDD 20
LEFTINP VDD
1 1
GNDA C11 1 2 2.2U_0402_6.3V6M 15 C12 C13
CPVSS
1U_0402_6.3V6K

0.1U_0402_25V6

16 3

1
CPVSS GND 9
GNDA GND 2 2
14 10
<43> HP_OUT_L HPLEFT GND
11 13
<43> HP_OUT_R HPRIGHT GND 19
B
HPOUT_R_1 C17 2 1 1U_0402_6.3V6K 5 GND B
1 RA34 2 0_0402_5% C19 2 1 1U_0402_6.3V6K 4 RIGHTINM +AVDD_CODEC
RIGHTINP
+3VS 6 21
#SD Thermal_Pad +MIC2_VREFO MIC Pre-AMP +VREF_EQ
MIC SENSE
1

8
HPA022642RTJR_QFN20 UA3A

1
RA62 GNDA GNDA 3

P
10K_0402_5% RA22 + 1 EXT_MIC_L
D40 2 OUT
2.2K_0402_5% -

G
EAPD 2 10/30 add U4114 1
2

1 TLV2462CDR_SO8

4
EC_MUTE# 3 MIC_JD CA76
100P_0402_50V8J
DAP202UGT106_SC70-3 EXT_MIC_L_C 2
<43> EXT_MIC_L_C
3

CA74 RA63
LA8 GNDA
RA24
QA2B EXT_MIC_L_C 1 2 1 2 1 2 RA69 1 2 100K_0402_5%
ME2N7002D1KW-G 2N_SOT363-6 5 1 2 BK1608HS601-T_2P 10K_0402_5%
0.47U_0603_16V7X 1 1 2
CA77 15P_0402_50V8J
4

22K_0402_5%

1
1 2 1 CA75
CA72 @EMI@ RA23 68P_0402_50V8J
1

.1U_0402_16V7K CA42 2
22K_0402_5%
short@ 4.7U_0402_6.3V6M +AVDD_CODEC
RA57 1 2 0_0402_5% RA60 2 2
0_0402_5% GNDA
2

RA58 1 2 0_0402_5%

8
HP_SENSE# GNDA GNDA RA70 100K_0402_5% UA3B
+AVDD_CODEC 1 2 5

P
+AVDD_CODEC +
1 2 7 +VREF_EQ
CA68 @EMI@ 6 OUT
-

G
.1U_0402_16V7K CA78 CA79
1

RA71 1 1 TLV2462CDR_SO8

4
2.2U_0402_6.3V6M

0.1U_0402_16V7K
RA21 100K_0402_5%
1 2 10K_0402_5%
A CA69 @EMI@ A

2
.1U_0402_16V7K RA51 2 2
2

47K_0402_5% GNDA
<SB Beep> 1 2 1 2 1 2 PC_BEEP
1 2 CA65 CA66
1

CA70 @EMI@ .1U_0402_16V7K .1U_0402_16V7K GNDA GNDA GNDA


6

.1U_0402_16V7K
Q91A RA52
1 2 ME2N7002D1KW-G 2N_SOT363-6 10K_0402_5%
CA71 EMI@ <9> HDA_SPKR 2
2

.1U_0402_16V7K
Security Classification Compal Secret Data Compal Electronics, Inc.
1

1 2 GNDA 2013/01/04 2015/01/04 Title


CA73 EMI@
Issued Date Deciphered Date
.1U_0402_16V7K Closed to Audio codec pin12
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AUDIO ALC3227
GNDA AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.5
GNDA
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B181P
Date: Tuesday, March 25, 2014 Sheet 26 of 62
5 4 3 2 1
5 4 3 2 1

WWW.AliSaler.Com

D D

C C

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/03/23 Deciphered Date 2012/10/21 Title
Audio SPK Conn/Jack/MIC
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C LA-B181P 0.5
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 25, 2014 Sheet 27 of 62
5 4 3 2 1
WWW.AliSaler.Com Keyboard conn

<32> KSI[0..7]
JKB1
KSI7 KSO11 1
KSI6 KSO0 2 1
KSI5 KSO2 3 2
KSI4 KSO5 4 3
KSI3 KSI_D_14 5 4
KSI2 KSI_D_8 6 5
KSI1 KSI_D_12 7 6
KSI0 KSI_D_10 8 7
KSI_D_0 9 8
KSI_D_4 10 9
<32> KSO[0..13] 10
KSI_D_2 11
KSO13 KSI_D_1 12 11
KSO12 KSI_D_3 13 12
KSO11 KSO3 14 13
KSO10 KSO8 15 14
KSO9 KSO4 16 15
KB backlight Conn KSO8 KSO7 17 16
17
KSO7 KSO6 18
KSO6 KSO10 19 18
+5VS +5VDS KSO5 KSO1 20 19
KSO4 KSI_D_5 21 20
KSO3 KSI_D_6 22 21
22

1
KSO2 KSI7 23
R407 KSO1 KSI_D_13 24 23
+5VS_KBL KSO0 KSI_D_11 25 24
Q47 100K_0402_5% 25
KSI_D_9 26
26
3

S KSO9 27

2
2 R408 1 2 200K_0402_5% 11/29 KSO12 28 27
G KSO13 29 28
JKBL1 D R660 1 2 360_0402_5% 30 29
<32> 8051_RECOVER#/_NUM_LOCK_LED#
1

1 31 30
1 +3VS 31

1
D
0.047U_0402_16V7K

2 ME2301D-G_SOT23-3 Q10 R203 1 2 360_0402_5% 32


2 <32> 8051RX_CAPLED#_R 32
3 1 2 33 35
3 KBL_DET# <9> KBD_PWM_LED <32> 33 GND
4 G 34 36
4 34 GND
C295

@ S

3
5 2N7002KW_SOT323-3 ACES_51503-03441-001
GND 6 2 CONN@
GND R1432 1 @ 2 0_0402_5%
CONN@
R1435
4 3 REC_MUTE_CTRL_KB_R 1 2 360_0402_5%
<26> REC_MUTE_CTRL_KB
Q91B
ME2N7002D1KW-G 2N_SOT363-6 8051_RECOVER#/_NUM_LOCK_LED#

5
8051RX_CAPLED#_R

+3VS_ISCT REC_MUTE_CTRL_KB_R

100P_0402_50V8J

100P_0402_50V8J

100P_0402_50V8J
1 1 1

C594

C595

C596
ESD@ ESD@ ESD@

2 2 2

D33 D36 D39


2 KSI_D_0 KSI_D_0 <43> 2 KSI_D_3 2 KSI_D_6
KSI0 1 KSI3 1 KSI6 1
3 KSI_D_8 3 KSI_D_11 3 KSI_D_14

DAP202UGT106_SC70-3 DAP202UGT106_SC70-3 DAP202UGT106_SC70-3

D34 D37
2 KSI_D_1 KSI_D_1 <43> 2 KSI_D_4
KSI1 1 KSI4 1
3 KSI_D_9 3 KSI_D_12

DAP202UGT106_SC70-3 DAP202UGT106_SC70-3

D35 D38
2 KSI_D_2 2 KSI_D_5
KSI2 1 KSI5 1
3 KSI_D_10 3 KSI_D_13

DAP202UGT106_SC70-3 DAP202UGT106_SC70-3

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2013/02/26 Deciphered Date 2015/07/08 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
KB/TP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.5
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B181P
Date: Tuesday, March 25, 2014 Sheet 28 of 62
A B C D E

WWW.AliSaler.Com
Power Button Connector Fan Control Circuit
+3VDS
+5VS +3VS

+3VDS
R217 U2

1
ON/OFFBTN_KBC# 1 2 CONN@
1 5 R4801
100K_0402_1% <32> FAN_PWM B Vcc ACES_88231-04001
C166 1 2 0.1U_0402_25V6 2 10K_0402_5%
<7> CPU_THERM# A
3 4 FAN_PWM_R 1
2

2 GND Y
1
@
@ JPWR1 FAN_PWM_R 2 1 1

2
PJ6 1 74AHC1G00GW_SOT353-5 3 2
PJ9 1 <32> TACH_FAN_IN
4 3

1
ON/OFFBTN_KBC# 2 @ C31 +FAN1
1

SHORT PADS SHORT PADS <32> ON/OFFBTN_KBC# 2 1 4


8051TX_STBYLED#_R 3 5 47P_0402_50V8J C4803
<32> 8051TX_STBYLED#_R 3 G1
4 6 @ 0.01U_0402_25V7K 5

2
4 G2 6 GND1
E-T_6916K-Q04N-03R 2 GND2
CONN@ JFAN1
PJ9 place Top layer,
+5VS
PJ6 place Bottom layer
Close to Connector
1A 40 mils

1000P_0402_50V7K
1 short@ 2 +FAN1
R4800 0_0603_5% C4801

2 2

3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2013/02/26 Deciphered Date 2015/07/08 Title
PWRBTN/FAN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.5
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B181P
Date: Tuesday, March 25, 2014 Sheet 29 of 62
A B C D E
5 4 3 2 1

WWW.AliSaler.Com
TPM1.2 +3VS

ACCELEROMETER
R113
+3VS_TPM 2 short@ 1
+3VDS
0_0402_5% R1428
1 2
D EC_MUTE# <26,32> D
1

1
C101 100K_0402_5%
1 1 1
C98 C99 C100 R1429
0.1U_0402_16V4Z 2K_0402_5%

1
0.1U_0402_16V4Z 0.1U_0402_16V4Z 2
2 2 2 +3VS_TPM RH219

1 2
100K_0402_5%
0.1U_0402_16V4Z D
11/29 2 Q62

2
1
+3VDS G

24
19
10
U13 2N7002KW_SOT323-3

5
R661 S

3
4.7K_0402_5%

VDD
VDD
VDD
VDD
26 U9
<7,32> LPC_LAD0 LAD0
23 1 9
<7,32> LPC_LAD1

2
20 LAD1 6 Vdd_IO INT2 11
<7,32> LPC_LAD2 LAD2 GPIO INT1 ACCEL_INT# <8>
17 4 14 +3VDS
<7,32> LPC_LAD3 LAD3 <7,32,34> PCH_KBC_I2CLK SCL/SPC VDD +3VDS
22 6
<7,32> LPC_LFRAME# LFRAME# <7,32,34> PCH_KBC_I2CDAT SDA/SDI/SDO
PLT_RST# 16 7 5
<6,8,21,23,32,33,43> PLT_RST# LRESET# SDO/SA0 GND
1 R118 2 1 10K_0402_5% 8 12 1 1
NC +3VDS CS GND

1
2 10 C103 C104 +3VS
NC 3 RES 13 0.1U_0402_16V7K 10U_0603_6.3V6M R90
NC RES

6
27 8 T108 PAD 2 15 47K_0402_5%
<7,9,32> SIRQ SERIRQ NC NC RES 2 2
9 2 @ 1 PLT_RST# R121 3 16
NC NC RES

1
12 R132 0_0402_5% @ 0_0402_5%

2
21 NC 13 R89 2 ME2N7002D1KW-G 2N_SOT363-6
<7> CLK_PCI_TPM LCLK NC HP3DC2 Q4115A
14 47K_0402_5%

2
NC

3
15

1
+3VS_TPM 1 @ 2 7 NC 28

2
PP NC

1
PP:default set to low R119 4.7K_0402_5%

GND
GND
GND
GND
R124 5 ME2N7002D1KW-G 2N_SOT363-6
11/28 @ 0_0402_5% Q4115B
1

25
18
11
4

4
R123 SLB9660TT1.2-FW-4.40_TSSOP28

2
4.7K_0402_5%
2

C C

CLK_PCI_TPM R120 1 @ 2 33_0402_5% C102 1 @ 2 22P_0402_50V8J

RF CAP
+VCC_CORE +VCC_CORE B+ B+ B+ B+ B+ B+ B+ B+

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
C80
0.1U_0402_10V6K

C556
100P_0402_50V8J

C81
0.1U_0402_10V6K

C558
100P_0402_50V8J

C90
0.1U_0402_10V6K

C564
100P_0402_50V8J

C91
0.1U_0402_10V6K

C565
100P_0402_50V8J

C92
0.1U_0402_10V6K

C566
100P_0402_50V8J

C93
0.1U_0402_10V6K

C567
100P_0402_50V8J

C95
0.1U_0402_10V6K

C569
100P_0402_50V8J

C110
0.1U_0402_10V6K

C578
100P_0402_50V8J

C111
0.1U_0402_10V6K

C579
100P_0402_50V8J

C108
0.1U_0402_10V6K

C576
100P_0402_50V8J
RF@ RF@ RF@ RF@ RF@ RF@ RF@ RF@ RF@ RF@ RF@ RF@ RF@ RF@ RF@ RF@
RF@ RF@ RF@ RF@
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

B+ B+ B+ B+ B+ B+ B+ B+ B+ B+
H1 H2 H3 H4 H5 H6 H7 H8 H9 H10
H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P2 H_3P0 H_4P0 H_4P2 H_3P8
B B
HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
C82
0.1U_0402_10V6K

C559
100P_0402_50V8J

C83
0.1U_0402_10V6K

C560
100P_0402_50V8J

C84
0.1U_0402_10V6K

C561
100P_0402_50V8J

C86
0.1U_0402_10V6K

C562
100P_0402_50V8J

C89
0.1U_0402_10V6K

C563
100P_0402_50V8J

C94
0.1U_0402_10V6K

C568
100P_0402_50V8J

C96
0.1U_0402_10V6K

C571
100P_0402_50V8J

C112
0.1U_0402_10V6K

C580
100P_0402_50V8J

C109
0.1U_0402_10V6K

C577
100P_0402_50V8J

C106
0.1U_0402_10V6K

C574
100P_0402_50V8J
RF@ RF@ RF@ RF@ RF@ RF@ RF@ RF@ RF@ RF@ RF@ RF@ RF@ RF@ RF@ RF@ RF@ RF@ RF@ RF@

@ @ @ @ @ @ @ @ @ @
1

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

H11 H12 H13 H14 H15 H16 H17 H18 H19 H20
H_4P2 H_3P7 H_3P8 H_3P0 H_4P0X3P0NH_3P0 H_3P7 H_3P7 H_4P0 H_3P0

HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA

B+ B+ +1.35V_VDDQ +1.35V_VDDQ +1.35V_VDDQ +1.35V_VDDQ +1.35V_VDDQ +0.675VS +0.675VS +0.675VS


@ @ @ @ @ @ @ @ @ @
1

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
C97
0.1U_0402_10V6K

C572
100P_0402_50V8J

C105
0.1U_0402_10V6K

C573
100P_0402_50V8J

C130
0.1U_0402_10V6K

C581
100P_0402_50V8J

C131
0.1U_0402_10V6K

C582
100P_0402_50V8J

C132
0.1U_0402_10V6K

C583
100P_0402_50V8J

C133
0.1U_0402_10V6K

C584
100P_0402_50V8J

C134
0.1U_0402_10V6K

C585
100P_0402_50V8J

C135
0.1U_0402_10V6K

C586
100P_0402_50V8J

C136
0.1U_0402_10V6K

C587
100P_0402_50V8J

C137
0.1U_0402_10V6K

C588
100P_0402_50V8J
RF@ RF@ RF@ RF@ RF@ RF@ RF@ RF@ RF@ RF@ RF@ RF@ RF@ RF@ RF@ RF@ RF@ RF@ RF@ RF@
H21 H22 H23 H24 H25 H26 H27 H28 H29 H30
H_3P0 H_5P2N H_3P0N H_3P0 H_3P4X3P0NH_3P6X3P2NH_3P4X3P0NH_3P6X3P2NH_3P4X3P0NH_3P6X3P2N
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA

@ @ @ @ @ @ @ @ @ @
1

H31
H_2P5N +0.675VS

HOLEA

1 1
C138
0.1U_0402_10V6K

C589
100P_0402_50V8J

@ RF@ RF@
1

A A
2 2

FD1 FD2 ZZZ ZZZ ZZZ

@ @
1

FIDUCIAL_C40M80 FIDUCIAL_C40M80
14" DAZ 15" DAZ 17" DAZ
FD3 FD4 14DAZ@ 15DAZ@ 17DAZ@
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2013/02/26 Deciphered Date 2015/07/08 Title
@ @
LED/Screw hole
1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
FIDUCIAL_C40M80 FIDUCIAL_C40M80 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.5
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B181P
Date: Tuesday, March 25, 2014 Sheet 30 of 62
5 4 3 2 1
5 4 3 2 1

WWW.AliSaler.Com
+3VS_6513 +1.8VS_6513
+1.8VS_RX_DVDD

L42 +1.8VS_6513 +1.8VS_DAC_VDDC +1.8VS_6513


1 2 +1.8VS_RX_AVCC

C4100
10U_0603_6.3V6M C4101 FCM2012CF-800T06_2P C4102 1 C4103 L43 1 2 L44 1 2

0.1U_0402_16V4Z

4.7U_0603_6.3V6K

0.1U_0402_16V4Z
1 1 1 FCM2012CF-800T06_2P FCM2012CF-800T06_2P 1 C4109

1
Rated current 500mA, DC 0.1ohm C4107 C4106 C4113 Rated current 500mA, DC 0.1ohm C4115

0.1U_0402_16V4Z
@ C15 1 1 1 1
2

1U_0402_6.3V6K

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1U_0402_6.3V6K
22U_0603_6.3V6M Note: Depend on

2
2 2 2 Project, if Vp-p small Note: Depend on 2
+1.8VS_RX_DVDD the 50mV change to 0 2 2 2
Project, if Vp-p small 2
ohm the 50mV change to 0
ohm
D D
+1.8VS_RX_AVCC
+1.8VS_DAC_VDDC
C4104 C4112 C4111
1 1 1 1 C4125

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
2 2 2 C4114 2
For Power consumption
1
Measurement

0.1U_0402_16V4Z
+3VS +3VS_CRT +3VS TO +3VS_6513 2
+1.8VS_RX_AVCC
JP4101
1 2 +3VS_CRT +3VS_6513 C4136
1 2 R4110 R4127 1

0.1U_0402_16V4Z
JUMP_43X39 2 short@ 1 ISPSCL_R 1M_0402_5%
@ ISPSDA_R XTALOUT_6513 @ XTALIN_6513
0_0603_5%
1 C4108 1

1
1
2
C4110
1U_0402_6.3V6K

22_0402_5%
R4100

R4101
22_0402_5%
X4100 @
0.1U_0402_25V6 +3VS_6513 +1.8VS_6513 +1.8VS_RX_DVDD Crystal
2 2 3 4
+3VS R4102 OUT GND

2
2
4.7K_0402_5% C4134 2 1 C4135
1 @ 2 GND IN
1

18P_0402_50V8J

18P_0402_50V8J
1 @ 2 1
R4103 @ 27MHZ_10PF_X3G027000BA1H-U
4.7K_0402_5% @
+5VS 2

13
48

35
36

38
39

12
14
44
46
U4101

1
2
2

DDCSDA
DDCSCL

OVDD
OVDD

IVDD33
IVDD33

IVDDO
IVDDO

IVDD
IVDD
IVDD
IVDD
VGA_HPD 40
HPD C4116
45 1 2 0.1U_0402_16V4Z
C4123 2 1 0.1U_0402_16V7K PCH_DPC_C_P0 26 MCUVDDH
C <4> PCH_DPC_P0 C
C4119 2 1 0.1U_0402_16V7KPCH_DPC_C_N0 27 RX0P
<4> PCH_DPC_N0 RX0N +5VS
<4> PCH_DPC_P1 C4120 2 1 0.1U_0402_16V7K PCH_DPC_C_P1 29 47 T4102
C4124 2 1 0.1U_0402_16V7KPCH_DPC_C_N1 30 RX1P MCURSTN
<4> PCH_DPC_N1 RX1N

4
3
2
1
CPU DDI1 28
URDBG T4101
+3VS R4108 2 @ 1 1M_0402_5% RP4101
RP4102
(2-Lane only) R4104 2 @ 1 100K_0402_5% C4121 15 ISPSCL_R 2.2K_0804_8P4R_5%
0.1U_0402_16V7K ISPSCL 16 ISPSDA_R 1 8
2 1 DDI1_AUX_C_DP 20 ISPSDA 2 7
<8> DDI1_AUX_DP

5
6
7
8
2 1 DDI1_AUX_C_DN 19 RXAUXP 23 3 6 CRT_CLK
<8> DDI1_AUX_DN RXAUXN VGADDCCLK
C4122 21 4 5 CRT_DATA
0.1U_0402_16V7K VGADDCSDA PCSDA CRT_DATA
+3VS R4113 2 @ 1 100K_0402_5% DDI1_AUX_DP 18 3 VSYNC PCSCL CRT_CLK
R4114 2 @ 1 1M_0402_5% DDI1_AUX_DN 17 DCAUXP VSYNC 4 HSYNC 22_0804_8P4R_5%
DCAUXN HSYNC
Note: ISPSCL/ISPSDA for F/W update
+1.8VS_RX_AVCC
+1.8VS_DAC_VDDC

25 10
R4120 1 2 0_0402_5% 31 AVCC VDDC
AVCC @ESD@
+5VS +1.8VS_RX_AVCC

22
PVCC
IT6513FN CRT_HSYNC_2 6
DT4

I/O4
SC300001G00
I/O2
3 CRT_VSYNC_2

11 VGA_RED +HDMI_5V_OUT
IORP
2
G

5 2
3 1 VGA_HPD +1.8VS_RX_DVDD 9 VGA_GRN VDD GND
<8> DDI1_HPD IOGP
S

@ 24
DVDD18
1

Q4100 8 VGA_BLU CRT_CLK 4 1 CRT_DATA


L2N7002LT1G_SOT23-3 R4122 IOBP I/O3 I/O1
4.7K_0402_5% 41
+1.8VS_RX_AVCC NC/VGADETECT AZC099-04S.R7G_SOT23-6
5 1 2
2

B
32 RSET R4118 100_0402_1% B
ASPVCC @ESD@
DT3
7 +1.8VS_DAC_VDDC SC300001G00
VDDA VGA_RE 6 3 VGA_GR
I/O4 I/O2
6 1 2 C4133 +HDMI_5V_OUT
PCSDA 43 COMP 0.1U_0402_16V4Z
PCSCL 42 PCSDA 5 2
PCSCL 34 XTALIN_6513 VDD GND
XTALIN 33 XTALOUT_6513
XTALOUT
PWDNB

4 1 VGA_BL
PAD

I/O3 I/O1

IT6513FN_QFN48_6X6 AZC099-04S.R7G_SOT23-6
37

49

+5VS RT57 1 2 10K_0402_5%


12/20
CRT Connector
12/20
JCRT
12/20 6
L29 150NH_LQG15HSR15J02D_5% 11
VGA_RED 1 2 VGA_RE 1
+5VS
7
L30 150NH_LQG15HSR15J02D_5% CRT_DATA 12
1 2 CRT_HSYNC_2 VGA_GRN 1 2 VGA_GR 2
RT26 LT14 10_0402_5% 8
R1369 L33 150NH_LQG15HSR15J02D_5%

R1370

R1371
1 2 2 1 CRT_HSYNC_2 13
CT27 0.1U_0402_16V4Z 1 2 CRT_VSYNC_2 VGA_BLU 1 2 VGA_BL 3
10K_0402_5% LT15 10_0402_5% 1 1 +HDMI_5V_OUT +HDMI_5V_OUT 9
5

UT2 C422 C416 C417 C418 C415 C420 CRT_VSYNC_2 14


1

74AHCT1G125GW_SOT353-5 CT26 @ @ CT28 1 1 1 1 1 1 1 W=40mils 1 C4132 4


P

OE#

22P_0402_50V8J

22P_0402_50V8J

22P_0402_50V8J

22P_0402_50V8J

22P_0402_50V8J

22P_0402_50V8J

0.1U_0402_16V4Z
HSYNC 2 4 CRT_HSYNC_1 10P_0402_50V8J 10P_0402_50V8J 10 G 16
A Y 2 2 @ CRT_CLK 15 17
G
G

5
12/20 2 2 2 2 2 2 2
+5VS
3

75_0402_5% 2

75_0402_5% 2

75_0402_5% 2

A SUYIN_070546HR015M26RZR A
CONN@

CT25 1 2 0.1U_0402_16V4Z
5

1
P

OE#

VSYNC 2 4 CRT_VSYNC_1
A Y
G

UT4
74AHCT1G125GW_SOT353-5
Security Classification Compal Secret Data Compal Electronics, Inc.
3

Issued Date 2011/06/30 Deciphered Date 2011/06/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
eDP to CRT
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C 0.5
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B181P
Date: Tuesday, March 25, 2014 Sheet 31 of 62
5 4 3 2 1
5 4 3 2 1

WWW.AliSaler.Com +3VDS
+RTCVCC

Layout note: Close to PIN106

Layout note: Close to PIN119


Layout note: Close to PIN68

Layout note: Close to PIN14

Layout note: Close to PIN37

Layout note: Close to PIN58

Layout note: Close to PIN84


LPC Debug Port

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
C179

C180

C181

C182

C183

C184

C185
1 1 1 1 1 1 1 1 PLT_RST#
+3VDS
RP8 C14 JTAG_RST# 1 2
8 1 KSI0 10U_0603_6.3V6M R216 100K_0402_5%

2
7 2 KSI1 2 2 2 2 2 2 2 2 11/28 B+

G
6 3 KSI2
5 4 KSI3 1 3
NMI_SMI_DBG# <6>
JP6

S
10K_0804_8P4R_5% 1
2 1
Q88 <7> CLK_PCI_DEBUG 2
RP7 3
1 8 KSI7 +RTCVCC 2N7002KW_SOT323-3 LPC_LFRAME# 4 3
D 2 7 KSI6 SIRQ 5 4 D
3 6 KSI5 PLT_RST# 6 5
<6,8,21,23,30,33,43> PLT_RST# 6
4 5 KSI4 NMI_SMI_DBG# 7
7

106

119
Layout note: 2vias to GND LPC_LAD0 8

68

58
84

14
37

49
10K_0804_8P4R_5% R5108 33_0402_5% U17 11/28 LPC_LAD1 9 8
PCH_SPI_SI_R 1 2 128 15 C187 1 2 1U_0402_6.3V6K LPC_LAD2 10 9

*VBAT

VCC1
VCC1
VCC1
VCC1
VCC1
VCC1

*JTAG_RST#
<7> PCH_SPI_SI_R FLDATAOUT CAP 10
127 LPC_LAD3 11
<23> LAN_PWR_EN_EC# *PVT_MOSI/GPIO54 11
PCH_SPI_CS0#_R 97 93 SIO_SLP_A# 12
<7> PCH_SPI_CS0#_R FLCS0# *GPIO145 SIO_SLP_A# <8> 12
PVT_CS0# 96 100mA 2mA 98 SUS_PWR_ACK 8051TX_STBYLED# 13
*PVT_CS0#/GPIO146 *GPIO157/BC_CLK SUS_PWR_ACK <8> 13
<7> PCH_SPI_SO_R PCH_SPI_SO_R 95 99 8051RX_CAPLED# 14
FLDATAIN *GPIO160/BC_DAT AC_PRES_OUT <8,34> 14
<9,19> PLT_ID2 94 100 KBC_PWR_ON 8051_RECOVER#/_NUM_LOCK_LED# 15
*PVT_MISO/GPIO164 *GPIO161/BC_INT# KBC_PWR_ON <42> 15
126 KBC_I2CDAT VCC1_PWRGD_SUS# R101 1 2 10_0402_5% 16
*GPIO24/I2C3_CLK0 KBC_I2CDAT <7> 16
125 KBC_I2CLK KSO0 R102 1 2 15_0402_5% 17
<28> KSO[0..13] *GPIO25/I2C3_DAT0 KBC_I2CLK <7> 17
KSO0 21 KSO1 R104 1 2 15_0402_5% 18
KSO1 20 KSO0 124 KSO3 R105 1 2 15_0402_5% 19 18
KSO1 *GPIO66 BATLOW# <8> 19
KSO2 19 KSO2 R106 1 2 15_0402_5% 20
+3VS KSO3 18 KSO2 123 JTAG_RST# 21 20
KSO4 17 KSO3 *GPIO44 122 KBRST# D21 1 @ 2 RB751V-40_SOD323-2 22 21
KSO4 *GPIO135/KBRST PM_APWROK <8> +3VDS 22

Keyboard/Mouse Interface
KSO5 16 121 FAN_PWM 23
KSO5 *GPIO34/TACH2PWM_OUT FAN_PWM <29> 23
KSO6 13 120 BAT_GRNLED# 24
KSO6 *GPIO133/PWM0 BAT_GRNLED# <6,44> 24
R5111 1 2 10K_0402_5% GPIO50 KSO7 12 118 KBD_PWM_LED 25

General Purpose I/O Interface


SMSC_1322-NU_TQFP-128P
KSO7 *GPIO136/PWM2 KBD_PWM_LED <28> G1
R5112 1 2 10K_0402_5% GPIO65 KSO8 10 26
R5113 1 2 10K_0402_5% GPIO46 KSO9 9 KSO8 107 CPPWR_EN T26 G2
R5114 1 2 10K_0402_5% GPIO47 KSO10 8 KSO9 *GPIO30 79 KBC_PWR_ON ACES_50238-02471-002
KSO10 VREF_PCEI +1.05VS
KSO11 7 80 H_PECI_R R238 1 2 43_0402_1% CONN@
KSO11 *GPIO131/PECI_DATA H_PECI <4>
KSO12 6 81
*KSO12/GPIO5 *GPIO7/KSO14 SLP_S3# <8,26,35,40,41,49,52>
KSO13 5 83 8051_RECOVER#/_NUM_LOCK_LED# 1
*KSO13/GPIO6 *GPIO10/KSO15 8051_RECOVER#/_NUM_LOCK_LED# <28>

C115
0.1U_0402_10V6K
<28> KSI[0..7]
85 RSMRST#_ECR610 1 2 470_0402_5% @ESD@
+3VS OUT1/RSMRST# PM_RSMRST# <8>
KSI0 29 86
KSI1 28 KSI0 *GPIO162/RXD 87 R252 1 2 10K_0402_5% 2
KSI2 27 KSI1 *GPIO165/TXD/HSD_CS1#
R5116 1 2 10K_0402_5% TP_CLK KSI3 26 KSI2 88 PCH_KBC_I2CDAT +3VDS
KSI3 *GPIO23/I2C1_DAT0 PCH_KBC_I2CDAT <7,30,34>
R5117 1 2 10K_0402_5% TP_DATA KSI4 25 89 PCH_KBC_I2CLK
KSI4 *GPIO22/I2C1_CLK0 PCH_KBC_I2CLK <7,30,34>
KSI5 24 90 KBC_PROC_HOT
KSI5 *GPIO21/I2C2_DAT0 KBC_PROC_HOT <4>
KSI6 23 91 U20
KSI6 *GPIO20/I2C2_CLK0 EC_MUTE# <26,30> +3VDS
KSI7 22 92 MAIN_BAT_DET# 1 5
KSI7 *GPIO105/FAN_TACH1 MAIN_BAT_DET# <45> NC VCC
101 TACH_FAN_IN
*GPIO140/TACH2PWM_IN TACH_FAN_IN <29>
102 PLT_DET 8051TX_STBYLED# 2
TP_CLK 35 *GPIO45/A20M/PVT_CS#1 KBC_I2CDAT R245 1 2 10K_0402_5% A 4 8051TX_STBYLED#_R
<43> TP_CLK *IMCLK/GPIO51 Y 8051TX_STBYLED#_R <29>
103 WLAN_WAKE# KBC_I2CLK R249 1 2 10K_0402_5% 3
*GPIO53/PS2CLK WLAN_WAKE# <21> GND
GPIO50 61 105
*GPIO50/KCLK *GPIO152/PS2DAT PCH_PCIE_WAKE# <8,21>
GPIO65 62 4 ON/OFFBTN# VCC1_PWRGD_SUS# R248 1 2 10K_0402_5% 74AUP1G07GW_TSSOP5
*GPIO65/KDAT *GPIO11/KSO16 ON/OFFBTN# <6,8>
GPIO46 66 74
*GPIO46/EMCLK *GPIO130 ADP_PRES <53>
GPIO47 67
*GPIO47/EMDAT 8051TX_STBYLED# R255 1 2 10K_0402_5% 11/28 +3VDS
8051RX_CAPLED# R257 1 2 10K_0402_5%
111 I2C_MAIN_DAT
*I2C0_DATA0 I2C_MAIN_DAT <45,46>
112 I2C_MAIN_CLK KBC_PWR_ON R263 1 2 30K_0402_5% U21
*I2C0_CLK0 I2C_MAIN_CLK <45,46>
Access Bus Interface 1 5
C +RTCVCC PM_CLKRUN# 55 109 ON/OFFBTN_KBC# R268 1 2 10K_0402_5% NC VCC C
<8> PM_CLKRUN# CLKRUN# *I2C0_DATA1
SIRQ 57 110 CHRG_ADP_DET R439 1 @ 2 10K_0402_5% 8051RX_CAPLED# 2
<7,9,30> SIRQ SER_IRQ *I2C0_CLK1 A
CLK_PCI_KBC 54 PCH_KBC_I2CDAT R440 1 2 10K_0402_5% 4 8051RX_CAPLED#_R
<7> CLK_PCI_KBC
EC_SCI# 76 PCI_CLK Power Mgmt/SIRQ 73 ON/OFFBTN_KBC# PCH_KBC_I2CLK R441 1 2 10K_0402_5% 3 Y 8051RX_CAPLED#_R <28>
1 <9> EC_SCI# EC_SCI# *GPIO110 ON/OFFBTN_KBC# <29> GND
LID_SW# R442 1 2 10K_0402_5%
C188 108 MAIN_BAT_DET# R443 1 2 30K_0402_5% 74AUP1G07GW_TSSOP5
*GPIO12/KSO17 KSO17 <43>
1U_0402_6.3V6K LPC_LAD3 51 59 OCP_PWM_OUT TACH_FAN_IN R445 1 @ 2 30K_0402_5%
2 <7,30> LPC_LAD3 LAD[3] *ADC_TO_PWM_OUT/GPIO41 OCP_PWM_OUT <9>
LPC_LAD2 50 75 ON/OFFBTN# R295 1 2 100K_0402_5%
<7,30> LPC_LAD2 LAD[2] *GPIO13 SLP_SUS# <8>
LPC_LAD1 48 60 R659 1 2 470_0402_5% 8051_RECOVER#/_NUM_LOCK_LED#R493 1 2 10K_0402_5%

Miscellaneous
<7,30> LPC_LAD1 LAD[1] *nRESET_OUT#/GPIO121 PM_PWROK <6,8>
LPC_LAD0 46 LPC 78 ADP_ID_CHK
<7,30> LPC_LAD0 LAD[0] *GPIO141/PWM3 ADP_ID_CHK <53>
77 VCC1_PWRGD_SUS#
LPC_LFRAME# 52 Bus VCC1_RST# 38 8051TX_STBYLED# R136 1 @ 2 0_0402_5% 8051TX_STBYLED#_R
<7,30> LPC_LFRAME# LFRAME# *ADC4/GPIO62 SLP_S4# <8,25,40,43,48>
<8> LPC_RESET# 53
LRESET# 69 KBC_XTAL2R624 1 short@ 2 0_0402_5% SUSCLK_KBC
*XTAL2 SUSCLK_KBC <8>
AMBER_BATLED# R5110 1 2 10K_0402_5% 8051RX_CAPLED# R137 1 @ 2 0_0402_5% 8051RX_CAPLED#_R
70
KBC_XTAL1 71 *VSS_VBAT 116 R625 1 @ 2 0_0402_5% LAN_PWR_EN_EC# R5123 1 2 10K_0402_5%
*XTAL1 *GPIO163 113 AMBER_BATLED#
*nBAT_LED#/GPIO154 AMBER_BATLED# <44> +3VDS
115 8051TX_STBYLED#
C189 1 2 2200P_0402_50V7K *nPWR_LED#/GPIO156 114 8051RX_CAPLED#
A_GND *GPIO155
<46> VOLTAGE_ADC 1 2 39 4.7K_0804_8P4R_5%
R267 300_0402_5% 1 *ADC3/GPIO61 I2C_MAIN_CLK 1 8
*GPIO36 iSCT_LED# <43>
2 41 iSCT_LED# R218 1 2 100K_0402_5% +3VDS I2C_MAIN_DAT 2 7
PCH_SPI_CLK_R 1 2 PCH_SPI_CLK_EC 3 *PVT_SCLK/GPIO153 *GPIO206 42 R270 1 2 300_0402_5% 3 6
*SHD_SCLK/GPIO122 *ADC2/GPIO60 ADP_A_ID <53>
WLAN_DISABLE R122 33_0402_5% 30 65 4 5
<21> WLAN_DISABLE *GPIO31 GPIO33
31 64 LID_SW#
<46> CHRG_ADP_DET *GPIO127 *GPIO27 LID_SW# <19,43>
TP_DATA 32 63 ADP_EN RP10
<43> TP_DATA *IMDAT/GPIO52 GPIO35 ADP_EN <46>
WWAN_DISABLE 33 40 +3VDS
<21> WWAN_DISABLE
*PWRGD

34 GPIO147 AVCC
R272 1 2 300_0402_5% 43 GPIO151 AVSS

0.1U_0402_16V4Z
<46> CURRENT_ADC
VSS
VSS
VSS
VSS
VSS
VSS
VSS

R273 1 2 300_0402_5% 44 *ADC1/GPIO57 C529


<53> OCP_A_IN *ADC0/ADC_TO_PWM_IN/GPIO56 1
Place close KBC pin +3VDS RSMRST#_EC R276 1 2 10K_0402_5%
MEC1322-NU VTQFP 128P ADP_ID_CHK R278 1 2 10K_0402_5%
72

11
47
56
104
82
117
36

45

KBC_PROC_HOT R446 1 2 100K_0402_5%

2
2 OCP_PWM_OUT R447 1 2 10K_0402_5%
R279
PWR_GD 10K_0402_5%
<6,8,41> PWR_GD
28W@
A_GND

1
A_GND PLT_DET

C190 1 2 2200P_0402_50V7K C191 1 2 2200P_0402_50V7K

1
C192 1 2 2200P_0402_50V7K 1 short@ 2 R219
R281 0_0402_5% 100K_0402_5%
+3V_PCH
15W@
Layout note: ADC nets are spaced at least 20mils from any high speed switching signals to prevent cross talk that could add noise

2
PCH_SPI_CS0#_R R5115 1 2 4.7K_0402_5%
B B

PVT_CS0# R5107 1 2 10K_0402_5%

KBC_XTAL1 C487 1 @ 2 10P_0402_25V8K

SPI ROM (8MByte )

2
Y5
10/29 Change to +3V_PCH @ 32.768KHZ_12.5PF_FC-135

1
+3V_PCH +3V_PCH
KBC_XTAL2 C488 1 @ 2 10P_0402_25V8K
+3V_PCH
0.1U_0402_16V4Z

UH5
8 4 1
VCC VSS C4965
<7> PCH_SPI_WP# PCH_SPI_WP# 3
W
RH223 1 2 PCH_SPI_WP# PCH_SPI_HOLD# 7 2
<7> PCH_SPI_HOLD# HOLD
3.3K_0402_5% PCH_SPI_CLK_EC
RH224 1 2 PCH_SPI_HOLD# PCH_SPI_CS0#_R 1
3.3K_0402_5% S
1 <7> PCH_SPI_CLK_R PCH_SPI_CLK_R 6
C419 C R283
33P_0402_50V8J PCH_SPI_SI_R 5 2 PCH_SPI_SO_R_12 1 PCH_SPI_SO_R
@ D Q 33_0402_5%
2 LOTES_ACA-SPI-004-P01_ROM
CONN@
+3V_PCH +3V_PCH +3V_PCH
U7
20mils CH97 CH98 CH114
SA00005VV10 : 128M W25Q128FVSIQ SOIC8P SPI ROM
0.1U_0402_16V4Z

22P_0402_50V8J

22P_0402_50V8J

1 1 1 SA00006PD00 : 128M EN25QH128A-104HIP SOP 8P


@ @
SA000039A30 : 64M W25Q64FVSSIQ SOIC 8P SPI ROM
2 2 2
SPI ROM : 64M EN25QH64-104HIP
45@
12/20 : 64M N25Q064A13ESEC0F

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2011/06/29 Deciphered Date 2011/06/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
EC SMSC_KB1322
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-B181P 0.5
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 25, 2014 Sheet 32 of 62
5 4 3 2 1
1 2 3 4 5

WWW.AliSaler.Com

U4103A PX@
AC Coupling Capacitor
PCIe Gen3: Recommended value is 220 nF
A A
PCIe Gen1 and Gen2 only: Recommended value is 100 nF
PEG_HTX_C_GRX_P7 AF30 AH30 PEG_GTX_HRX_P7 0.1U_0402_16V7K 1 2 CV2 PX@ PEG_GTX_C_HRX_P7
<10> PEG_HTX_C_GRX_P7 PCIE_RX0P PCIE_TX0P PEG_GTX_C_HRX_P7 <10>
PEG_HTX_C_GRX_N7 AE31 AG31 PEG_GTX_HRX_N7 0.1U_0402_16V7K 1 2 CV1 PX@ PEG_GTX_C_HRX_N7
<10> PEG_HTX_C_GRX_N7 PCIE_RX0N PCIE_TX0N PEG_GTX_C_HRX_N7 <10>

PEG_HTX_C_GRX_P8 AE29 AG29 PEG_GTX_HRX_P8 0.1U_0402_16V7K 1 2 CV4 PX@ PEG_GTX_C_HRX_P8


<10> PEG_HTX_C_GRX_P8 PCIE_RX1P PCIE_TX1P PEG_GTX_C_HRX_P8 <10>
PEG_HTX_C_GRX_N8 AD28 AF28 PEG_GTX_HRX_N8 0.1U_0402_16V7K 1 2 CV3 PX@ PEG_GTX_C_HRX_N8
<10> PEG_HTX_C_GRX_N8 PCIE_RX1N PCIE_TX1N PEG_GTX_C_HRX_N8 <10>

PEG_HTX_C_GRX_P9 AD30 AF27 PEG_GTX_HRX_P9 0.1U_0402_16V7K 1 2 CV6 PX@ PEG_GTX_C_HRX_P9


<10> PEG_HTX_C_GRX_P9 PCIE_RX2P PCIE_TX2P PEG_GTX_C_HRX_P9 <10>
PEG_HTX_C_GRX_N9 AC31 AF26 PEG_GTX_HRX_N9 0.1U_0402_16V7K 1 2 CV5 PX@ PEG_GTX_C_HRX_N9
<10> PEG_HTX_C_GRX_N9 PCIE_RX2N PCIE_TX2N PEG_GTX_C_HRX_N9 <10>

PEG_HTX_C_GRX_P10 AC29 AD27 PEG_GTX_HRX_P10 0.1U_0402_16V7K 1 2 CV8 PX@ PEG_GTX_C_HRX_P10


<10> PEG_HTX_C_GRX_P10 PCIE_RX3P PCIE_TX3P PEG_GTX_C_HRX_P10 <10>
PEG_HTX_C_GRX_N10 AB28 AD26 PEG_GTX_HRX_N10 0.1U_0402_16V7K 1 2 CV7 PX@ PEG_GTX_C_HRX_N10
<10> PEG_HTX_C_GRX_N10 PCIE_RX3N PCIE_TX3N PEG_GTX_C_HRX_N10 <10>
No Use GPU Display Port outpud
AB30 AC25 11/28
AA31 PCIE_RX4P PCIE_TX4P AB25
PCIE_RX4N PCIE_TX4N U4103F PX@
+VGA_CORE
AA29 Y23
Y28 PCIE_RX5P PCIE_TX5P Y24
PCIE_RX5N PCIE_TX5N AB11
VDDC AB12
Y30 AB27 VDDC
W31 PCIE_RX6P PCIE_TX6P AB26
PCIE_RX6N PCIE_TX6N

W29 Y27 AL15


V28 PCIE_RX7P PCIE_TX7P Y26 NC_UPHYAB_TMDPA_TX0N AK14
PCIE_RX7N PCIE_TX7N NC_UPHYAB_TMDPA_TX0P
B B
AH16
V30 W24 NC_UPHYAB_TMDPA_TX1N AJ15
U31 NC#V30 NC#W24 W23 NC_UPHYAB_TMDPA_TX1P
NC#U31 NC#W23 AL17
NC_UPHYAB_TMDPA_TX2N AK16
U29 V27 NC_UPHYAB_TMDPA_TX2P
T28 NC#U29 NC#V27 U26 AH18
NC#T28 NC#U26 NC_UPHYAB_TMDPA_TX3N AJ17
NC_UPHYAB_TMDPA_TX3P

PCI EXPRESS INTERFACE


T30 U24 AL19
R31 NC#T30 NC#U24 U23 NC_TXOUT_L3P AK18
NC#R31 NC#U23 NC_TXOUT_L3N

R29 T26 TMDP


P28 NC#R29 NC#T26 T27
NC#P28 NC#T27 AH20
NC_UPHYAB_TMDPB_TX0N AJ19
P30 T24 NC_UPHYAB_TMDPB_TX0P
N31 NC#P30 NC#T24 T23 AL21
NC#N31 NC#T23 NC_UPHYAB_TMDPB_TX1N AK20
NC_UPHYAB_TMDPB_TX1P
N29 P27 AH22
M28 NC#N29 NC#P27 P26 NC_UPHYAB_TMDPB_TX2N AJ21
NC#M28 NC#P26 NC_UPHYAB_TMDPB_TX2P
AL23
M30 P24 NC_UPHYAB_TMDPB_TX3N AK22
L31 NC#M30 NC#P24 P23 NC_UPHYAB_TMDPB_TX3P
NC#L31 NC#P23 AK24
NC_TXOUT_U3P AJ23
L29 M27 NC_TXOUT_U3N
K30 NC#L29 NC#M27 N26
NC#K30 NC#N26

216-0858070-A1-PRO-S3_FCBGA631
C CLOCK C
CLK_PEG_VGA AK30
<7> CLK_PEG_VGA PCIE_REFCLKP
CLK_PEG_VGA# AK32
<7> CLK_PEG_VGA# PCIE_REFCLKN +0.95VS_VGA

CALIBRATION
Y22 R5008 1 PX@ 2 1.69K_0402_1%
PCIE_CALR_TX
R5009 1 PX@ 2 1K_0402_1% N10 AA22 R5010 1 PX@ 2 1K_0402_1%
TEST_PG PCIE_CALR_RX

GPU_RST# AL27
PERSTB

216-0858070-A1-PRO-S3_FCBGA631

+3VS_VGA +3VS
+3VS
1

R5011 R5012 R5093


0_0402_5% @ PX@0_0402_5%
PX@0_0402_5%
2

2
5

U4104 PX@ PX@


5

PLT_RST# 2 U4106 R5094


P

<6,8,21,23,30,32,43> PLT_RST# B 4 GPU_RST# PLT_RST# 2 0_0402_5%


P

Y <6,8,21,23,30,32,43> PLT_RST# B
DGPU_HOLD_RST# 1 4 VGA_PWRGD_R 2 PX@ 1
<9> DGPU_HOLD_RST# A Y VGA_PWRGD <9,54>
G

GPU_PGD 1
<9,54> GPU_PGD A
1

1
3

R5013 R5095
3

MC74VHC1G08DFT2G_SC70-5 PX@100K_0402_5% PX@ 100K_0402_5%


D D
MC74VHC1G08DFT2G_SC70-5
2

11/28

Security Classification Compal Secret Data


Title
Compal Electronics, Inc.
Issued Date 2013/01/11 Deciphered Date 2013/12/31
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Topaz_PCIE/DP
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.5
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
LA-B181P
Tuesday, March 25, 2014 Sheet 33 of 62
1 2 3 4 5
1 2 3 4 5

WWW.AliSaler.Com +3VS_VGA
Resistor Divider Lookup Lable

R_pu (ohm) R_pd (ohm) Bitd [3:1]


PS_0[3:1]=001 +1.8VS_VGA
Strap Name :
U4103B PX@ PS_0[5:4]=11

1
R5014 R5015 PX@
PS_0[1]  ROM_CONFIG[0]
10K_0402_5% PX@ PX@10K_0402_5%
NC 4.75k 000 R5016
AF2 8.45K_0402_1%
PS_0[2]  ROM_CONFIG[1]
NC#AF2 8.45k 2k 001

2
AF4
PS_0[3]  ROM_CONFIG[2]

2
PX@ NC#AF4 PS_0
6 1 VGA_SMB_DA3 1 N9 AG3
4.53k 2k 010
<7,30,32> PCH_KBC_I2CDAT T4126 NC_DBG_DATA16 NC#AG3 PS_0[4]  N/A

1
1 L9 AG5 6.98k 4.99k 011
T4125 NC_DBG_DATA15 NC#AG5
Q4102A ME2N7002D1KW-G 2N_SOT363-6 1 AE9 DPA PX@ PS_0[5]  AUD_PORT_CONN_PINSTRAP[0]
T4127 NC_DBG_DATA14
1 Y11 AH3 R5017
T4105
1 AE8 NC_DBG_DATA13 NC#AH3 AH1
4.53k 4.99k 100 C=NC 2K_0402_1%
T4106 NC_DBG_DATA12 NC#AH1

5
1 AD9
T4107 3.24k 5.62k 101

2
A PX@ 1 AC10 DBG_DATA11 AK3 A
T4108 DBG_DATA10 NC#AK3
3 4 VGA_SMB_CK3 1 AD7 AK1 3.4k 10k 110
<7,30,32> PCH_KBC_I2CLK T4109 DBG_DATA9 NC#AK1
1 AC8
Q4102B ME2N7002D1KW-G 2N_SOT363-6 +1.8VS_VGA T4110
1 AC7 DBG_DATA8 DVO AK5
T4111
1 AB9 DBG_DATA7 NC#AK5 AM3
4.75k NC 111
T4112 DBG_DATA6 NC#AM3
1 AB8 0402 1% resistors are equired
T4113 DBG_DATA5
1 AB7 AK6
T4114 DBG_DATA4 NC#AK6

1
PCH_KBC_I2CDAT 1 @ 2 VGA_SMB_DA3 1 AB4 AM5 +1.8VS_VGA
R5018 0_0402_5% R5042 R5040
T4115
1 AB2 DBG_DATA3 NC#AM5 PS_1[3:1]=000 Strap Name :
T4116 DPB
10K_0402_5% PX@ PX@10K_0402_5% 1 Y8 DBG_DATA2 AJ7
T4117 DBG_DATA1 NC#AJ7 Capacitor Divider Lookup Lable PS_1[5:4]=11

1
PCH_KBC_I2CLK 1 @ 2 VGA_SMB_CK3 1 Y7 AH6 PS_1[1]  STRAP_BIF_GEN3_EN_A
T4118 DBG_DATA0 NC#AH6
R5019 0_0402_5% @

2
U1 AK8 R5020
U3 BP_0 DB NC#AK8 AL7
Cap (nF) Bitd [5:4] 8.45K_0402_1%
PS_1[2]  TRAP_BIF_CLK_PM_EN
BP_1 NC#AL7
PS_1[3]  N/A

2
680nF 00 PS_1
W6 PS_1[4]  STRAP_TX_CFG_DRV_FULL_SWING
NC#W6

1
V6
NC#V6 V4
82nF 01 PX@
AC6 NC#V4 U5 R5021
PS_1[5]  STRAP_TX_DEEMPH_EN
AC5 NC#AC5 NC#U5 10nF 10 C=NC 4.75K_0402_1%
NC#AC6 W3 NC 11

2
AA5 FB_GND V2
AA6 NC#AA5 NC#V2
DPC
NC#AA6 Y4
NC#Y4 W5
NC#W5 R5082 16.2K_0402_1%
AA3 1 PX@ 2
PAD T163 FB_VDDCI W1 PLL_ANALOG_OUT Y2
FB_VDDCI NC#Y2 +1.8VS_VGA
Y6 J8
PS_2[3:1]=000 Strap Name :
1PLL_ANALOG_IN AA1 NC#Y6 NC#J8
T4128 PLL_ANALOG_IN PS_2[5:4]=11
PS_2[1]  N/A
R=NC
PS_2[2]  N/A
+3VS_VGA
I2C
PS_2
PS_2[3]  STRAP_BIOS_ROM_EN
B 1 R1 B
T4129 SCL PS_2[4]  STRAP_BIF_VGA_DIS

1
1 R3 +1.8VS_VGA +3VS_VGA
T4130 SDA 1
R5084 PX@ R5085 0_0402_5% PS_2[5]  N/A
R5022 1 @ 2 100K_0402_5% AC_PRES_OUT AM26 1 2 1 @ 2 C4804 @ PX@R5024
PX@R5024
R5023 1 PX@ 2 100K_0402_5% VGA_AC_BATT GENERAL PURPOSE DIECRACKMON AK26 0.082U_0402_16V6K 4.75K_0402_1%
I/O NC_AVSSN 0_0402_5% 2
1 GPU_GPIO0 U6 R5086 R5087 R5088
T4131

2
GPIO_0

10K_0402_5%

10K_0402_5%

10K_0402_5%
R5083 1 @ 2 5.1K_0402_1% TESTEN +VGA_CORE U10 AL25
VDDC NC_G

2
T10 AJ25
VGA_SMB_DA3 U8 VDDC NC_AVSSN
@ D14 CH751H-40PT_SOD323-2 VGA_SMB_CK3 U7 SMBDAT AH24 PX@ @ @
VGA_AC_BATT pull up AC_PRES_OUT 1 2 T9 SMBCLK NC_B AG25
<8,32> AC_PRES_OUT GPIO_5_AC_BATT NC_AVSSN
T8

1
+3VS_VGA VGA_AC_BATT 1 PX@ 2 T7 GPIO_6_TACH DAC1 AH26 GPU_SVT
R5026 0_0402_5% P10 NC_GPIO_7 NC_HSYNC AJ27 GPU_SVD +1.8VS_VGA
P4 GPIO_8_ROMSO WAKEB GPU_SVC
PS_3[3:1]=010 Strap Name :
GPIO_9_ROMSI

2
P2 PS_3[5:4]=11
GPIO_10_ROMSCK
1

1
GPIO6_OCP N6 AD22 R177 R5089 R5090 R5091
GPIO_11 NC_RSET PS_3[1]  BOARD_CONFIG[0] (Memory ID)

10K_0402_5%

10K_0402_5%

10K_0402_5%
R5096 @ N5 4.7K_0402_5%
N3 GPIO_12 AG24 @ PX@ @ X76@ R5027
10K_0402_5%
Y9 GPIO_13 NC_AVDD AE22 4.53K_0402_1%
PS_3[2]  BOARD_CONFIG[1] (Memory ID)
+VGA_CORE

1
PAD T164 GPU_VID1 N1 VDDC NC_AVSSQ
PS_3[3]  BOARD_CONFIG[2] (Memory ID)
2

2
M4 GPIO_15_PWRCNTL_0 AE23 PS_3
R5097 GPIO_16 NC_VDD1DI
R5106 R6 AD23 PS_3[4]  AUD_PORT_CONN_PINSTRAP[1]
GPIO_17_THERMAL_INT NC_VSS1DI

1
2 1 GPIO6_OCP 1 PX@ 2 W10
<54> EC_THERM# VDDC
GPIO19_CTF M2
GPIO_19_CTF FutureASIC/SEYMOUR/PARK PS_3[5]  AUD_PORT_CONN_PINSTRAP[2]
0.1U_0402_16V4Z

1K_0402_5% 1 PAD T165 10K_0402_5% GPU_VID2 P8 AM12 C=NC X76@ R5030


PAD T166 GPU_VID5 P7 GPIO_20_PWRCNTL_1 NC_CEC_1 2K_0402_1%
@ C4960 N8 GPIO_21

2
@ PAD T167 GPU_VID4 AK10 GPIO_22_ROMCSB AK12 GPU_SVD
2 GPIO_29 GPIO_SVD GPU_SVD <54>
PAD T168 GPU_VID3 AM10 AL11 GPU_SVT
GPIO_30 GPIO_SVT GPU_SVT <54>
GPU_CLKREQ# 1 @ 2 GPU_CLKREQ#_R N7 AJ11 GPU_SVC
CLKREQB GPIO_SVC GPU_SVC <54>
R5032 0_0402_5%
JTAG_TRSTB L6
JTAG_TDI L5 JTAG_TRSTB
C4805 JTAG_TCK L3 JTAG_TDI
1 JTAG_TCK
+3V_PCH 68P_0402_50V8J JTAG_TMS L1 AL13
@ T4120 1 JTAG_TDO K4 JTAG_TMS NC_GENLK_CLK AJ13
TESTEN K7 JTAG_TDO NC_GENLK_VSYNC
C 2 AF24 TESTEN C
NC#AF24
2

AG13
R5121 NV_SWAPLOCKA AH12
@ 10K_0402_5% +VGA_CORE AB13 NC_SWAPLOCKB Memory ID Memory Type Configuration Size R5027 R5030 X76 P/N
W8 VDDC
W9 NC_GENERICB
1

W7 VDDC AC19 PS_0


GPU_CLKREQ# <7>
AD10 GENERICD PS_0 000 SA000068U80 Samsung K4W2G1646Q‐BC1A 1GB NC 4.75K X7655332L03
AJ9 NC_GENERICE_HPD4 AD19 PS_1
NC#AJ9 PS_1
2

AL9
NC_DBG_CNTL0 001 SA000076P00 Samsung K4W4G1646D‐BC1A 2GB 8.45K 2K X7655332L06
3

R5122 AE17 PS_2


AC14 PS_2
10K_0402_5% VDDC
PX@ 1 @ 2 PX_EN_R AB16 AE20 PS_3
5
@ <54> PX_EN
R5044 0_0402_5% PX_EN PS_3
(Default) 010 SA00006H440 Hynix  H5TC2G63FFR‐11C 1GB 4.53K 2K X7655332L01
<9> DGPU_PWROK
1

Q4109B AE19
011 SA00006E800 Hynix H5TC4G63AFR‐11C 2GB 6.98K 4.99K X7655332L04
4

1 AC16 TS_A
T4122 NC_DBG_VREFG
ME2N7002D1KW-G 2N_SOT363-6
100 SA000067540 Micron MT41J128M16JT‐093G:K 1GB 4.53K 4.99K X7655332L02
DDC/AUX
AE6
PLL/CLOCK NC_DDC1CLK AE5 101 SA000077K00 Micron MT41J256M16HA‐093G:E 2GB 3.24K 5.62K X7655332L05
NC_DDC1DATA
+3VS_VGA AD2
NC_AUX1P AD4 +VGA_CORE 110 Nanya 128x16 NT5CB128M16FP 1GB 3.4K 10K
NC_AUX1N
RP4103 AC11
R5028 1 PX@ 2 GPIO19_CTF 1 8 JTAG_TRSTB VDDC AC13 111 Nanya 256x16 NT5CB256M16CP 2GB 4.75K NC
10K_0402_5% 2 7 JTAG_TDI VDDC
R5029 1 PX@ 2 GPU_CLKREQ#_R 3 6 JTAG_TMS XTALIN AM28 AD13
10K_0402_5% 4 5 JTAG_TCK XTALOUT AK28 XTALIN NC_AUX2P AD11
R5031 1 PX@ 2 TESTEN XTALOUT NC_AUX2N
1K_0402_5% 10K_8P4R_5% AC22 AD20 VGA_VSSSENSE
XO_IN FB_GND VGA_VSSSENSE <54>
@ AB22 AC20 VGA_VCCSENSE ZZZ1 ZZZ2 ZZZ3 ZZZ4 ZZZ5 ZZZ6
XO_IN2 FB_VDDC VGA_VCCSENSE <54>
1
T4123
2

R5046 AE16
R5092 NC#AE16 AD16
NC#AD16
10K_0402_5%

D XTALIN R5033 1 PX@ 2 XTALOUT PX@ PX@10K_0402_5% D


1M_0402_5% SEYMOUR/FutureASIC AC1
+1.8VS_VGA 1 T4 NC_DDCVGACLK AC3
T4132
1

1 T2 DPLUS THERMAL NC_DDCVGADATA X761G@ X762G@ X761G@ X762G@ X761G@ X762G@


Y6 PX@ L4106 1 PX@ 2 13mA T4133 DMINUS
1G SAMSUNG 2G SAMSUNG 1G HYNIX 2G HYNIX 1G MICRON 2G MICRON
4 3 BLM15BD121SN1D_0402 X7655332L03 X7655332L06 X7655332L01 X7655332L04 X7655332L02 X7655332L05
NC OSC GPIO28 R5
1 2 C4808 2 PX@1 10U_0603_6.3V6M +TSVDD AD17 GPIO28_FDO
OSC NC AC17 TSVDD
27MHZ 10PF +-10PPM 7V27000050 C4809 2 PX@1 1U_0402_6.3V4Z TSVSS
2 2
C4806 SJ100009700 C4807
12P_0402_50V8J
PX@
12P_0402_50V8J
PX@
C4810 2 PX@1 0.1U_0402_10V6K Security Classification Compal Secret Data
Title
Compal Electronics, Inc.
1 1 216-0858070-A1-PRO-S3_FCBGA631
?
Issued Date 2013/01/11 Deciphered Date 2013/12/31 Topaz_MSIC
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.5
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
LA-B181P
Tuesday, March 25, 2014 Sheet 34 of 62
1 2 3 4 5
1 2 3 4 5

WWW.AliSaler.Com +1.5VS +1.5VS_VGA


+1.5VS to +1.5VS_VGA (2.096A)
U4103E PX@

U4105 PX@
AO4354_SO8
8 1 +5VDS AA27 A3
C4813 7 2 370mA (HDMI) No Use GPU Display Port outpud AB24 GND GND A30
GND GND

2
6 3 C4811 C4812 R5036 +1.8VS_VGA AB32 AA13
188mA (Display Port) GND GND

2
0.1U_0402_16V7K

10U_0603_6.3V6M

1U_0402_6.3V4Z

10_0603_5%
1 5 1 1 AC24 AA16
PX@ R5119 R5035 1 short@ 2 +DP_VDDR U4103G PX@ AC26 GND GND AB10
PX@ PX@ PX@ PX@ 100K_0402_5% 0_0603_5% AC27 GND GND AB15

4
NC/DP POWER AD25 GND GND AB6
DP POWER

3 1
2 2 2 C4814 1 AD32 GND GND AC9
1 C4815

1
AG15 AE11 AE27 GND GND AD6
A A
NC_DP_VDDR NC#AE11 GND GND

1U_0402_6.3V4Z

10U_0603_6.3V6M
PX@ PX@ AG16 AF11 AF32 AD8
AF16 NC_DP_VDDR NC#AF11 AE13 AG27 GND GND AE7
5 VGA_EN# 2 2 AG17 NC_DP_VDDR NC#AE13 AF13 AH32 GND GND AG12
1 PX@ 2 1.5VSG_GATE PX@ AG18 NC_DP_VDDR NC#AF13 AG8 K28 GND GND AH10
B+ NC_DP_VDDR NC#AG8 GND GND
R5037 200K_0402_5% Q4103B AG19 AG10 K32 AH28

4
ME2N7002D1KW-G 2N_SOT363-6 AF14 NC_DP_VDDR NC#AG10 L27 GND GND B10
DP_VDDR#AF14 GND GND
6

1
1 M32 B12

ME2N7002D1KW-G 2N_SOT363-6
R5038 N25 GND GND B14
GND GND

3
PX@ @ 1.5M_0402_5% PX@ C4816 N27 B16
VGA_EN# 2 0.047U_0402_16V7K P25 GND GND B18
2 AG20 AF6 P32 GND GND B20
2

VGA_EN 5 AG21 NC_DP_VDDC NC#AF6 AF7 R27 GND GND B22


<8,54> VGA_EN
1

Q4103A PX@ +0.95VS_VGA AF22 NC_DP_VDDC NC#AF7 AF8 T25 GND GND B24
280mA NC_DP_VDDC NC#AF8 GND GND

1
ME2N7002D1KW-G 2N_SOT363-6 Q4110B AG22 AF9 T32 B26

4
R5120 R5039 1 short@ 2 +DP_VDDC AD14 NC_DP_VDDC NC#AF9 U25 GND GND B6
100K_0402_5%PX@ 0_0603_5% DP_VDDC#AD14 U27 GND GND B8
V32 GND GND C1
W25 GND GND C32
1 1

2
D15 C4817 C4818 AG14 AE1 W26 GND GND E28
1 2 PX@ PX@ AH14 NC_DP_VSSR NC#AE1 AE3 W27 GND GND F10
NC_DP_VSSR NC#AE3 GND GND

1U_0402_6.3V4Z

0.1U_0402_10V6K
PX@ AM14 AG1 Y25 F12
CH751H-40PT_SOD323-2 2 2 AM16 NC_DP_VSSR NC#AG1 AG6 Y32 GND GND F14
AM18 NC_DP_VSSR NC#AG6 AH5 GND GND F16
R5118 NC_DP_VSSR NC#AH5 GND
AF23 AF10 F18
DGPU_PWR_EN 1 PX@ 2 AG23 NC_DP_VSSR NC#AF10 AG9 GND F2
<8> DGPU_PWR_EN NC_DP_VSSR NC#AG9 GND
AM20 AH8 F20
10K_0402_5% AM22 NC_DP_VSSR NC#AH8 AM6 M6 GND F22
AM24 NC_DP_VSSR NC#AM6 AM8 N13 GND GND F24
AF19 NC_DP_VSSR NC#AM8 AG7 N16 GND GND F26
AF20 NC_DP_VSSR NC#AG7 AG11 N18 GND GND F6
D10 AE14 NC_DP_VSSR NC#AG11 N21 GND GND
GND F8
SLP_S3# 1 2 DP_VSSR P6 GND GND G10
<8,26,32,40,41,49,52> SLP_S3# 0.95V_1.8V_VGA_EN <56,57> GND GND
PX@ P9 G27
CH751H-40PT_SOD323-2 PX@ R12 GND GND G31
B
C4821 1 2 1U_0402_6.3V4Z AF17 AE10 R15 GND GND G8 B
NC_UPHYAB_DP_CALR NC#AE10 R17 GND GND H14
R20 GND GND H17
T13 GND GND H2
T16 GND GND H20
216-0858070-A1-PRO-S3_FCBGA631 GND GND
T18 H6
T21 GND GND J27
T6 GND GND J31
U15 GND GND K11
U17 GND GND K2
+3VS to +3VS_VGA (25mA) U20
U9
GND
GND
GND
GND
K22
K6
V13 GND GND
V16 GND
V18 GND
Y10 GND
Y15 GND
+3VS +3VS_VGA Y17 GND
Q33 Y20 GND
SI2305CDS-T1-GE3_SOT23-3 R11 GND A32
T11 GND VSS_MECH AM1
60mA GND VSS_MECH
S

3 1 AA11 AM32
D

M12 GND VSS_MECH


N11 GND
GND
1

R5076 PX@ V11


G
2

GND
1

R5077
10K_0402_5%

PX@ 100_0402_5%
@
216-0858070-A1-PRO-S3_FCBGA631
2
2

R5075 D PX@
DGPU_PWR_EN# 1 PX@ 2 2 Q4104
G 2N7002KW_SOT323-3
C 1K_0402_5% C4819 S C
3
1

0.1U_0402_16V7K

1
R5074
@ 10K_0402_5% PX@
2
2

+5VDS
+VGA_CORE

2
R5041
PX@100K_0402_5% R5043
PX@470_0603_5%

ME2N7002D1KW-G 2N_SOT363-6

ME2N7002D1KW-G 2N_SOT363-6
3 1
DGPU_PWR_EN#

6 1
<8> DGPU_PWR_EN DGPU_PWR_EN 5
PX@ 2 DGPU_PWR_EN#

1
Q4106B PX@

4
R5045 Q4106A

1
100K_0402_5%PX@

2
D D

Security Classification Compal Secret Data


Title
Compal Electronics, Inc.
Issued Date 2013/01/11 Deciphered Date 2013/12/31
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Topaz_Power/GND
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.5
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
LA-B181P
Tuesday, March 25, 2014 Sheet 35 of 62
1 2 3 4 5
1 2 3 4 5

WWW.AliSaler.Com

+PCIE_PVDD:
+1.8VS_VGA
50mA (PCIE2.0)
+1.5VS_VGA 80mA (PCIE3.0)
C4837 C4843
A
+VGA_CORE 10uF 1uF 0.1uF 1 1
A

10U_0603_6.3V6M

1U_0402_6.3V4Z
C4829

C4847

C4845

C4832

C4833

C4834

C4835

C4836
1 1 2 1 1 1 1 1 PX@ PX@
VDDC TBD 5 (1@) 10 (2@) 0 PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ 2 2
U4103D PX@

10U_0603_6.3V6M

0.1U_0402_10V6K

0.01U_0402_16V7K

2.2U_0402_6.3V5M

2.2U_0402_6.3V5M

2.2U_0402_6.3V5M

2.2U_0402_6.3V5M

2.2U_0402_6.3V5M
2 2 1 2 2 2 2 2
AM30
VDDCI 3.5A 1 3 0 1A PCIE_PVDD

PCIE
H13 AB23
H16 VMEMIO NC#AB23 AC23
H19 VMEMIO NC#AC23 AD24
J10 VMEMIO NC#AD24 AE24 +PCIE_VDDC:
VMEMIO NC#AE24
+0.95VS_VGA 10uF 1uF 0.1uF J23
J24 VMEMIO NC#AE25
AE25
AE26
1.88A (PCIE2.0) +0.95VS_VGA
VMEMIO NC#AE26
J9
VMEMIO NC#AF25
AF25 2.5A (PCIE3.0)
K10 AG26
K23 VMEMIO NC#AG26
PCIE_VDDC 2.5A 2 (1@) 5 (1@) 0 K24 VMEMIO
VMEMIO

C4850

C4851

C4852

C4853

C4854

C4855

C4856

C4857

C4858
K9 L23
L11 VMEMIO PCIE_VDDC L24
VMEMIO PCIE_VDDC 1 1 1 1 1 1 1 1 1
L12 L25
BIF_VDDC 1.4A 0 0 0 L13 VMEMIO PCIE_VDDC L26 PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@
L20 VMEMIO PCIE_VDDC M22

10U_0603_6.3V6M

10U_0603_6.3V6M

1U_0402_6.3V6K

1U_0402_6.3V6K
1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z
L21 VMEMIO PCIE_VDDC N22 2 2 2 2 2 2 2 2 2
L22 VMEMIO PCIE_VDDC N23
SPLL_VDDC 100mA 1 1 1 VMEMIO PCIE_VDDC N24
PCIE_VDDC R22
+1.8VS_VGA PCIE_VDDC T22
13mA AA20 PCIE_VDDC U22
AA21 VDD_GPIO18 PCIE_VDDC V22
AB20 VDD_GPIO18 PCIE_VDDC
+1.5VS_VGA 10uF 1uF 0.1uF AB21 VDD_GPIO18 +VGA_CORE
C4860 VDD_GPIO18 AA15
B CORE VDDC N15 B
1 VDDC

1U_0402_6.3V4Z
N17
VDDR1 1.5A 3 5 5 PX@ +3VS_VGA VDDC R13
L4108 PX@ 25mA VDDC R16
2 1 2 +VDDR3 AA17 VDDC R18
BLM15BD121SN1D_0402 AA18 VDD_GPIO33 VDDC Y21
C4862 AB17 VDD_GPIO33 VDDC T12
AB18 VDD_GPIO33 VDDC T15
+1.8VS_VGA 10uF 1uF 0.1uF 0 ohm  P/N 1 VDD_GPIO33 VDDC

1U_0402_6.3V4Z
T17
PX@ V12 VDDC T20
Y12 NC_VDDR4 VDDC U13
2 U12 NC_VDDR4 VDDC U16
PCIE_PVDD 100mA 1 1 1 NC_VDDR4 VDDC U18 21A (VDDC + VDDCI
VDDC V21
VDDC V15 (Merged) ‐ PRO S3 (DDR3))
VDDC V17
MPLL_PVDD 130mA 1 1 1 VDDC V20
VDDC

POWER
Y13
VDDC Y16
VDDC Y18
SPLL_PVDD 75mA 1 1 1 VDDC AA12
VDDC M11
VDDC N12
VDDC U11
VDDR4 (300mA) 0 0 0 VDDC
+1.8VS_VGA
L4109 PX@ 90mA PLL
1 2 +MPLL_PVDD
VDD_CT 13mA 1 1 1
C4865

C4866

C4867

MBK1608221YZF_2P
+0.95VS_VGA
1 1 1
R21 1.4A
BIF_VDDC U21
+TSVDD 13mA 1 1 1 BIF_VDDC
10U_0603_6.3V6M

0.1U_0402_10V6K
1U_0402_6.3V4Z

2 2 2 L8
MPLL_PVDD
PX@

PX@

PX@

+1.8VS_VGA C4871 C4872 C4873


C
L4110 75mA +VGA_CORE
C

+DP_VDDR 0 0 0 ISOLATED

10U_0603_6.3V6M

1U_0402_6.3V4Z

1U_0402_6.3V4Z
1 PX@ 2 +SPLL_PVDD CORE I/O 1 1 1
BLM15BD121SN1D_0402 M13
H7 VDDCI M15 PX@ PX@ PX@
C4868 C4869 SPLL_PVDD VDDCI M16
+DP_VDDC 0 0 0 1 1
VDDCI M17 2 2 2
+0.95VS_VGA VDDCI
10U_0603_6.3V6M

1U_0402_6.3V4Z

M18
100mA VDDCI

C4953

C4954

C4955

C4956

C4957

C4958

C4959
PX@ PX@ L4111 M20
1 PX@ 2 +SPLL_VDDC H8 VDDCI M21
2 2 SPLL_VDDC VDDCI 1 1 1 1 1 1 1
BLM15BD121SN1D_0402 N20
J7 VDDCI PX@ PX@ PX@ PX@ PX@ PX@ PX@
+3VS_VGA 10uF 1uF 0.1uF C4875 C4876 SPLL_PVSS

10U_0603_6.3V6M

10U_0603_6.3V6M

0.1U_0402_10V6K

0.1U_0402_10V6K
1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z
2 2 2 2 2 2 2
1 1

1U_0402_6.3V4Z

0.1U_0402_10V6K
PX@ PX@
VDDR3 25mA 0 2 (1@) 1 216-0858070-A1-PRO-S3_FCBGA631
2 2

+1.5VS_VGA +3VS

C4870 1 @ 2 0.1U_0402_10V6K

C4874 1 @ 2 0.1U_0402_10V6K

+1.5VS_VGA +VGA_CORE

C4967 1 @ 2 0.1U_0402_10V6K

C4968 1 @ 2 0.1U_0402_10V6K
D D

Security Classification Compal Secret Data


Title
Compal Electronics, Inc.
Issued Date 2013/01/11 Deciphered Date 2013/12/31
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Topaz_Power
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.5
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
LA-B181P
Tuesday, March 25, 2014 Sheet 36 of 62
1 2 3 4 5
1 2 3 4 5

WWW.AliSaler.Com
M_DA[63..0]
<38,39> M_DA[63..0]
M_MA[15..0]
<38,39> M_MA[15..0]
M_DQM[7..0]
<38,39> M_DQM[7..0]
M_DQS[7..0]
<38,39> M_DQS[7..0]
A A
M_DQS#[7..0]
<38,39> M_DQS#[7..0]

U4103C PX@
GDDR5/DDR3 GDDR5/DDR3
M_DA0 K27 K17 M_MA0
M_DA1 J29 DQA0_0 MAA0_0 J20 M_MA1
M_DA2 H30 DQA0_1 MAA0_1 H23 M_MA2
M_DA3 H32 DQA0_2 MAA0_2 G23 M_MA3
M_DA4 G29 DQA0_3 MAA0_3 G24 M_MA4
M_DA5 F28 DQA0_4 MAA0_4 H24 M_MA5
M_DA6 F32 DQA0_5 MAA0_5 J19 M_MA6
+1.5VS_VGA +1.5VS_VGA M_DA7 F30 DQA0_6 MAA0_6 K19 M_MA7
M_DA8 C30 DQA0_7 MAA0_7 G20 M_MA13
M_DA9 F27 DQA0_8 MAA0_8 L17 M_MA15
M_DA10 A28 DQA0_9 MAA0_9
DQA0_10
1

1
M_DA11 C28 J14 M_MA8
PX@ PX@ M_DA12 E27 DQA0_11 MAA1_0 K14 M_MA9
R5048 R5049 M_DA13 G26 DQA0_12 MAA1_1 J11 M_MA10
40.2_0402_1% 40.2_0402_1% M_DA14 D26 DQA0_13 MAA1_2 J13 M_MA11
M_DA15 F25 DQA0_14 MAA1_3 H11 M_MA12
2

M_DA16 A25 DQA0_15 MAA1_4 G11 M_BA2


DQA0_16 MAA1_5 M_BA2 <38,39>
+MVREFDA +MVREFSA M_DA17 C25 J16 M_BA0
DQA0_17 MAA1_6 M_BA0 <38,39>
M_DA18 E25 L15 M_BA1
DQA0_18 MAA1_7 M_BA1 <38,39>
M_DA19 D24 G14 M_MA14
DQA0_19 MAA1_8
1

1 1 M_DA20 E23 L16 MAA1_9 T169 PAD


PX@ PX@ PX@ PX@ M_DA21 F23 DQA0_20 MAA1_9
R5050 C4877 R5051 C4878 M_DA22 D22 DQA0_21 E32 M_DQM0
100_0402_1% 1U_0402_6.3V4Z 100_0402_1% 1U_0402_6.3V4Z M_DA23 F21 DQA0_22 WCKA0_0 E30 M_DQM1

MEMORY INTERFACE
2 2 M_DA24 E21 DQA0_23 WCKA0B_0 A21 M_DQM2
2

M_DA25 D20 DQA0_24 WCKA0_1 C21 M_DQM3


M_DA26 F19 DQA0_25 WCKA0B_1 E13 M_DQM4
B
M_DA27 A19 DQA0_26 WCKA1_0 D12 M_DQM5 B
M_DA28 D18 DQA0_27 WCKA1B_0 E3 M_DQM6
M_DA29 F17 DQA0_28 WCKA1_1 F4 M_DQM7
M_DA30 A17 DQA0_29 WCKA1B_1
M_DA31 C17 DQA0_30 H28 M_DQS0
M_DA32 E17 DQA0_31 EDCA0_0 C27 M_DQS1
M_DA33 D16 DQA1_0 EDCA0_1 A23 M_DQS2
M_DA34 F15 DQA1_1 EDCA0_2 E19 M_DQS3
M_DA35 A15 DQA1_2 EDCA0_3 E15 M_DQS4
M_DA36 D14 DQA1_3 EDCA1_0 D10 M_DQS5
PX@ PX@ M_DA37 F13 DQA1_4 EDCA1_1 D6 M_DQS6
R5052 R5053 M_DA38 A13 DQA1_5 EDCA1_2 G5 M_DQS7
49.9_0402_1% 10_0402_1% M_DA39 C13 DQA1_6 EDCA1_3
1 2 2 1 DRAM_RST M_DA40 E11 DQA1_7 H27 M_DQS#0
<38,39> DRAM_RST# DQA1_8 DDBIA0_0
M_DA41 A11 A27 M_DQS#1
M_DA42 C11 DQA1_9 DDBIA0_1 C23 M_DQS#2
DQA1_10 DDBIA0_2
1

1 M_DA43 F11 C19 M_DQS#3


PX@ PX@ M_DA44 A9 DQA1_11 DDBIA0_3 C15 M_DQS#4
C4879 R5054 M_DA45 C9 DQA1_12 DDBIA1_0 E9 M_DQS#5
120P_0402_50V8J 5.1K_0402_1% M_DA46 F9 DQA1_13 DDBIA1_1 C5 M_DQS#6
2 M_DA47 D8 DQA1_14 DDBIA1_2 H4 M_DQS#7
2

M_DA48 E7 DQA1_15 DDBIA1_3


M_DA49 A7 DQA1_16 L18 VRAM_ODT0
DQA1_17 ADBIA0 VRAM_ODT0 <38>
M_DA50 C7 K16 VRAM_ODT1
DQA1_18 ADBIA1 VRAM_ODT1 <39>
M_DA51 F7
M_DA52 A5 DQA1_19 H26 M_CLK0
DQA1_20 CLKA0 M_CLK0 <38>
M_DA53 E5 H25 M_CLK#0
DQA1_21 CLKA0B M_CLK#0 <38>
M_DA54 C3
M_DA55 E1 DQA1_22 G9 M_CLK1
Place close to GPU (within 25mm) M_DA56 G7 DQA1_23 CLKA1 H9 M_CLK#1
M_CLK1 <39>
DQA1_24 CLKA1B M_CLK#1 <39>
and place componment close to each other M_DA57 G6
DQA1_25
M_DA58 G1 G22 M_RAS#0
DQA1_26 RASA0B M_RAS#0 <38>
M_DA59 G3 G17 M_RAS#1
DQA1_27 RASA1B M_RAS#1 <39>
M_DA60 J6
M_DA61 J1 DQA1_28 G19 M_CAS#0
C C
DQA1_29 CASA0B M_CAS#0 <38>
M_DA62 J3 G16 M_CAS#1
DQA1_30 CASA1B M_CAS#1 <39>
M_DA63 J5
DQA1_31 H22 M_CS#0
CSA0B_0 M_CS#0 <38>
+MVREFDA K26 J22
+MVREFSA J26 MVREFDA CSA0B_1
MVREFSA G13 M_CS#1
CSA1B_0 M_CS#1 <39>
J25 K13
R5055 1 PX@ 2 120_0402_1% K25 NC#J25 CSA1B_1
MEM_CALRP0 K20 M_CKE0
CKEA0 M_CKE0 <38>
J17 M_CKE1
CKEA1 M_CKE1 <39>
G25 M_WE#0
WEA0B M_WE#0 <38>
DRAM_RST L10 H10 M_WE#1
DRAM_RST WEA1B M_WE#1 <39>
R5056 @ 1 2 51.1_0402_1% C4880 @1 2 0.1U_0402_16V4Z K8
R5057 @ 1 2 51.1_0402_1% C4881 @1 2 L7 CLKTESTA
0.1U_0402_16V4Z CLKTESTB
Route 50ohms single‐ended/100ohm diff and keep short
216-0858070-A1-PRO-S3_FCBGA631
debug only, for clock observation,if not need, DNI.

D D

Security Classification Compal Secret Data


Title
Compal Electronics, Inc.
Issued Date 2013/01/11 Deciphered Date 2013/12/31
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Topaz_MEM
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.5
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
LA-B181P
Tuesday, March 25, 2014 Sheet 37 of 62
1 2 3 4 5
1 2 3 4 5

WWW.AliSaler.Com
Memory Partition A - Lower 32 bits
M_DA[63..0]
<37,39> M_DA[63..0]
M_MA[15..0]
<37,39> M_MA[15..0]
UH1 UM1
M_DQM[7..0]
<37,39> M_DQM[7..0]
M_DQS[7..0]
<37,39> M_DQS[7..0]
M_DQS#[7..0]
<37,39> M_DQS#[7..0]
@ Hynix @ Micron

A A

+1.5VS_VGA
+1.5VS_VGA
U4109 U4110

1
1

+FBA_VREF0 M8 E3 M_DA17 PX@ +FBA_VREF1 M8 E3 M_DA30


PX@ +FBQ_VREF0 H1 VREFCA DQL0 F7 M_DA23 R5059 +FBQ_VREF1 H1 VREFCA DQL0 F7 M_DA27
R5058 VREFDQ DQL1 F2 M_DA21 4.99K_0402_1% VREFDQ DQL1 F2 M_DA31
4.99K_0402_1% M_MA0 N3 DQL2 F8 M_DA22 M_MA0 N3 DQL2 F8 M_DA24

2
M_MA1 P7 A0 DQL3 H3 M_DA18 +FBA_VREF1 M_MA1 P7 A0 DQL3 H3 M_DA29
2

+FBA_VREF0 M_MA2 P3 A1 DQL4 H8 M_DA19 M_MA2 P3 A1 DQL4 H8 M_DA26


M_MA3 N2 A2 DQL5 G2 M_DA16 M_MA3 N2 A2 DQL5 G2 M_DA28
A3 DQL6 A3 DQL6

1
M_MA4 P8 H7 M_DA20 1 M_MA4 P8 H7 M_DA25
A4 DQL7 A4 DQL7
1

1 M_MA5 P2 PX@ PX@ M_MA5 P2


PX@ PX@ M_MA6 R8 A5 R5061 C4883 M_MA6 R8 A5
R5060 C4882 M_MA7 R2 A6 D7 M_DA5 4.99K_0402_1% 0.1U_0402_10V6K M_MA7 R2 A6 D7 M_DA8
4.99K_0402_1% 0.1U_0402_10V6K M_MA8 T8 A7 DQU0 C3 M_DA3 2 M_MA8 T8 A7 DQU0 C3 M_DA14

2
2 M_MA9 R3 A8 DQU1 C8 M_DA4 M_MA9 R3 A8 DQU1 C8 M_DA9
2

M_MA10 L7 A9 DQU2 C2 M_DA1 M_MA10 L7 A9 DQU2 C2 M_DA12


M_MA11 R7 A10/AP DQU3 A7 M_DA6 M_MA11 R7 A10/AP DQU3 A7 M_DA10
M_MA12 N7 A11 DQU4 A2 M_DA0 M_MA12 N7 A11 DQU4 A2 M_DA15
M_MA13 T3 A12 DQU5 B8 M_DA7 M_MA13 T3 A12 DQU5 B8 M_DA11
M_MA14 T7 A13 DQU6 A3 M_DA2 M_MA14 T7 A13 DQU6 A3 M_DA13
M_MA15 M7 A14 DQU7 M_MA15 M7 A14 DQU7
A15/BA3 +1.5VS_VGA A15/BA3 +1.5VS_VGA
+1.5VS_VGA
+1.5VS_VGA M_BA0 M2 B2 M_BA0 M2 B2
<37,39> M_BA0 BA0 VDD BA0 VDD
M_BA1 N8 D9 M_BA1 N8 D9
<37,39> M_BA1 BA1 VDD BA1 VDD

1
M_BA2 M3 G7 M_BA2 M3 G7
<37,39> M_BA2 BA2 VDD BA2 VDD
1

K2 PX@ K2
PX@ VDD K8 R5100 VDD K8
R5099 VDD N1 4.99K_0402_1% VDD N1
4.99K_0402_1% M_CLK0 J7 VDD N9 M_CLK0 J7 VDD N9
<37> M_CLK0

2
B
M_CLK#0 K7 CK VDD R1 +FBQ_VREF1 M_CLK#0 K7 CK VDD R1 B
<37> M_CLK#0
2

+FBQ_VREF0 M_CKE0 K9 CK VDD R9 M_CKE0 K9 CK VDD R9


<37> M_CKE0 CKE/CKE0 VDD +1.5VS_VGA CKE/CKE0 VDD +1.5VS_VGA

1
1
1

1 VRAM_ODT0 K1 A1 PX@ PX@ VRAM_ODT0 K1 A1


<37> VRAM_ODT0 ODT/ODT0 VDDQ ODT/ODT0 VDDQ
PX@ PX@ M_CS#0 L2 A8 R5101 C4962 M_CS#0 L2 A8
<37> M_CS#0 CS/CS0 VDDQ CS/CS0 VDDQ
R5098 C4961 M_RAS#0 J3 C1 4.99K_0402_1% 0.1U_0402_10V6K M_RAS#0 J3 C1
<37> M_RAS#0 RAS VDDQ 2 RAS VDDQ
4.99K_0402_1% 0.1U_0402_10V6K M_CAS#0 K3 C9 M_CAS#0 K3 C9
<37> M_CAS#0

2
2 M_WE#0 L3 CAS VDDQ D2 M_WE#0 L3 CAS VDDQ D2
<37> M_WE#0
2

WE VDDQ E9 WE VDDQ E9
VDDQ F1 VDDQ F1
M_DQS2 F3 VDDQ H2 M_DQS3 F3 VDDQ H2
M_DQS0 C7 DQSL VDDQ H9 M_DQS1 C7 DQSL VDDQ H9
DQSU VDDQ DQSU VDDQ

M_DQM2 E7 A9 M_DQM3 E7 A9
M_DQM0 D3 DML VSS B3 M_DQM1 D3 DML VSS B3
DMU VSS E1 DMU VSS E1
VSS G8 VSS G8
M_DQS#2 G3 VSS J2 M_DQS#3 G3 VSS J2
M_DQS#0 B7 DQSL VSS J8 M_DQS#1 B7 DQSL VSS J8
DQSU VSS M1 DQSU VSS M1
VSS M9 VSS M9
VSS P1 VSS P1
T2 VSS P9 DRAM_RST# T2 VSS P9
<37,39> DRAM_RST# RESET VSS RESET VSS
T1 T1
L8 VSS T9 L8 VSS T9
ZQ/ZQ0 VSS ZQ/ZQ0 VSS
1

1
J1 B1 J1 B1
M_CLK0 PX@ L1 NC/ODT1 VSSQ B9 PX@ L1 NC/ODT1 VSSQ B9
M_CLK#0 R5062 J9 NC/CS1 VSSQ D1 R5063 J9 NC/CS1 VSSQ D1
243_0402_1% L9 NC/CE1 VSSQ D8 243_0402_1% L9 NC/CE1 VSSQ D8
NCZQ1 VSSQ E2 NCZQ1 VSSQ E2
2

2
VSSQ VSSQ
1

C E8 E8 C
R5064 R5065 VSSQ F9 VSSQ F9
40.2_0402_1% 40.2_0402_1% VSSQ G1 VSSQ G1
PX@ PX@ VSSQ G9 VSSQ G9
VSSQ VSSQ
2

96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3
H5TC2G63FFR-11C_FBGA96 H5TC2G63FFR-11C_FBGA96
1 X76@ X76@
PX@
C4884
0.01U_0402_25V7K
2 +1.5VS_VGA
+1.5VS_VGA
U4109 side
U4110 side
C4885

C4886

C4887

C4888

C4889

C4890

C4891

C4892

C4893

C4894

C4895

C4896

C4897

C4898

C4899

C4900

C4901

C4902

C4903

C4904

C4905

C4906

C4907

C4908

C4909

C4910

C4911

C4912

C4913

C4914
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
10U_0603_6.3V6M

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K
1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
PX@

PX@

PX@

PX@

PX@

PX@

PX@

PX@

PX@

PX@

PX@

PX@

PX@

PX@

PX@

10U_0603_6.3V6M

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K
1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z
PX@

PX@

PX@

PX@

PX@

PX@

PX@

PX@

PX@

PX@

PX@

PX@

PX@

PX@

PX@
D D

Security Classification Compal Secret Data


Title
Compal Electronics, Inc.
Issued Date 2013/01/11 Deciphered Date 2013/12/31
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Topaz_VRAM
Size Document Number
A Lower Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.5
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
LA-B181P
Tuesday, March 25, 2014 Sheet 38 of 62
1 2 3 4 5
1 2 3 4 5

Memory Partition A - Upper 32 bits


WWW.AliSaler.Com

U4112
U4111
A M_DA[63..0] +FBA_VREF3 M8 E3 M_DA49 A
<37,38> M_DA[63..0] VREFCA DQL0
+FBA_VREF2 M8 E3 M_DA38 +FBQ_VREF3 H1 F7 M_DA53
M_MA[15..0] +FBQ_VREF2 H1 VREFCA DQL0 F7 M_DA36 VREFDQ DQL1 F2 M_DA51
<37,38> M_MA[15..0] VREFDQ DQL1 DQL2
F2 M_DA37 M_MA0 N3 F8 M_DA54
M_DQM[7..0] M_MA0 N3 DQL2 F8 M_DA35 M_MA1 P7 A0 DQL3 H3 M_DA50
<37,38> M_DQM[7..0] A0 DQL3 A1 DQL4
M_MA1 P7 H3 M_DA39 M_MA2 P3 H8 M_DA55
M_DQS[7..0] M_MA2 P3 A1 DQL4 H8 M_DA32 M_MA3 N2 A2 DQL5 G2 M_DA48
<37,38> M_DQS[7..0] A2 DQL5 A3 DQL6
M_MA3 N2 G2 M_DA34 M_MA4 P8 H7 M_DA52
M_DQS#[7..0] M_MA4 P8 A3 DQL6 H7 M_DA33 M_MA5 P2 A4 DQL7
<37,38> M_DQS#[7..0] A4 DQL7 A5
M_MA5 P2 M_MA6 R8
M_MA6 R8 A5 M_MA7 R2 A6 D7 M_DA60
M_MA7 R2 A6 D7 M_DA41 M_MA8 T8 A7 DQU0 C3 M_DA59
M_MA8 T8 A7 DQU0 C3 M_DA44 +1.5VS_VGA M_MA9 R3 A8 DQU1 C8 M_DA63
M_MA9 R3 A8 DQU1 C8 M_DA43 M_MA10 L7 A9 DQU2 C2 M_DA56
+1.5VS_VGA M_MA10 L7 A9 DQU2 C2 M_DA45 M_MA11 R7 A10/AP DQU3 A7 M_DA62
A10/AP DQU3 A11 DQU4

1
M_MA11 R7 A7 M_DA42 M_MA12 N7 A2 M_DA57
M_MA12 N7 A11 DQU4 A2 M_DA46 PX@ M_MA13 T3 A12 DQU5 B8 M_DA61
A12 DQU5 A13 DQU6
1

M_MA13 T3 B8 M_DA40 R5067 M_MA14 T7 A3 M_DA58


PX@ M_MA14 T7 A13 DQU6 A3 M_DA47 4.99K_0402_1% M_MA15 M7 A14 DQU7
R5066 M_MA15 M7 A14 DQU7 A15/BA3 +1.5VS_VGA

2
4.99K_0402_1% A15/BA3 +1.5VS_VGA +FBA_VREF3
M_BA0 M2 B2
2

+FBA_VREF2 M_BA0 M2 B2 M_BA1 N8 BA0 VDD D9


<37,38> M_BA0 BA0 VDD BA1 VDD

1
M_BA1 N8 D9 1 M_BA2 M3 G7
<37,38> M_BA1 BA1 VDD BA2 VDD
M_BA2 M3 G7 PX@ PX@ K2
<37,38> M_BA2 BA2 VDD VDD
1

1 K2 R5069 C4916 K8
PX@ PX@ VDD K8 4.99K_0402_1% 0.1U_0402_10V6K VDD N1
R5068 C4915 VDD N1 2 M_CLK1 J7 VDD N9

2
4.99K_0402_1% 0.1U_0402_10V6K M_CLK1 J7 VDD N9 M_CLK#1 K7 CK VDD R1
2 <37> M_CLK1 CK VDD CK VDD
M_CLK#1 K7 R1 M_CKE1 K9 R9
<37> M_CLK#1
2

M_CKE1 K9 CK VDD R9 CKE/CKE0 VDD +1.5VS_VGA


<37> M_CKE1 CKE/CKE0 VDD +1.5VS_VGA
VRAM_ODT1 K1 A1
VRAM_ODT1 K1 A1 M_CS#1 L2 ODT/ODT0 VDDQ A8
<37> VRAM_ODT1 ODT/ODT0 VDDQ CS/CS0 VDDQ
M_CS#1 L2 A8 M_RAS#1 J3 C1
B <37> M_CS#1 CS/CS0 VDDQ RAS VDDQ B
M_RAS#1 J3 C1 M_CAS#1 K3 C9
<37> M_RAS#1 RAS VDDQ CAS VDDQ
M_CAS#1 K3 C9 M_WE#1 L3 D2
<37> M_CAS#1 CAS VDDQ WE VDDQ
M_WE#1 L3 D2 E9
<37> M_WE#1 WE VDDQ +1.5VS_VGA VDDQ
E9 F1
VDDQ F1 M_DQS6 F3 VDDQ H2
M_DQS4 F3 VDDQ H2 M_DQS7 C7 DQSL VDDQ H9
DQSL VDDQ DQSU VDDQ

1
M_DQS5 C7 H9
+1.5VS_VGA DQSU VDDQ PX@
R5104 M_DQM6 E7 A9
M_DQM4 E7 A9 4.99K_0402_1% M_DQM7 D3 DML VSS B3
DML VSS DMU VSS
1

M_DQM5 D3 B3 E1

2
PX@ DMU VSS E1 +FBQ_VREF3 VSS G8
R5102 VSS G8 M_DQS#6 G3 VSS J2
4.99K_0402_1% M_DQS#4 G3 VSS J2 M_DQS#7 B7 DQSL VSS J8
DQSL VSS DQSU VSS

1
M_DQS#5 B7 J8 1 M1
2

+FBQ_VREF2 DQSU VSS M1 PX@ PX@ VSS M9


VSS M9 R5105 C4964 VSS P1
VSS P1 4.99K_0402_1% 0.1U_0402_10V6K DRAM_RST# T2 VSS P9
VSS RESET VSS
1

DRAM_RST# T2 P9 2 T1
1 <37,38> DRAM_RST#

2
PX@ PX@ RESET VSS T1 L8 VSS T9
R5103 C4963 L8 VSS T9 ZQ/ZQ0 VSS
4.99K_0402_1% 0.1U_0402_10V6K ZQ/ZQ0 VSS

1
2 J1 B1
2

NC/ODT1 VSSQ
1

J1 B1 PX@ L1 B9
PX@ L1 NC/ODT1 VSSQ B9 R5073 J9 NC/CS1 VSSQ D1
R5072 J9 NC/CS1 VSSQ D1 243_0402_1% L9 NC/CE1 VSSQ D8
243_0402_1% L9 NC/CE1 VSSQ D8 NCZQ1 VSSQ E2

2
NCZQ1 VSSQ E2 VSSQ E8
2

VSSQ E8 VSSQ F9
VSSQ F9 VSSQ G1
VSSQ G1 VSSQ G9
VSSQ G9 VSSQ
VSSQ 96-BALL
96-BALL SDRAM DDR3
C SDRAM DDR3 H5TC2G63FFR-11C_FBGA96 C
H5TC2G63FFR-11C_FBGA96 X76@
X76@

M_CLK1
M_CLK#1
1

R5070 R5071
40.2_0402_1% 40.2_0402_1%
PX@ PX@ +1.5VS_VGA +1.5VS_VGA

U4111 side U4112 side
2

C4918

C4919

C4920

C4921

C4922

C4923

C4924

C4925

C4926

C4927

C4928

C4929

C4930

C4931

C4932

C4933

C4934

C4935

C4936

C4937

C4938

C4939

C4940

C4941

C4942

C4943

C4944

C4945

C4946

C4947
1
PX@ 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
C4917
0.01U_0402_25V7K
2
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
10U_0603_6.3V6M

10U_0603_6.3V6M
0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K
1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z
PX@

PX@

PX@

PX@

PX@

PX@

PX@

PX@

PX@

PX@

PX@

PX@

PX@

PX@

PX@

PX@

PX@

PX@

PX@

PX@

PX@

PX@

PX@

PX@

PX@

PX@

PX@

PX@

PX@

PX@
D D

Security Classification Compal Secret Data


Title
Compal Electronics, Inc.
Issued Date 2013/01/11 Deciphered Date 2013/12/31
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Topaz_VRAM
Size Document Number
A Upper Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.5
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
LA-B181P
Tuesday, March 25, 2014 Sheet 39 of 62
1 2 3 4 5
A B C D E

WWW.AliSaler.Com +3VS

10U_0603_6.3V6M
1

C575
+5VDS +5VDS +3VDS
2
Q21
1 14
2 VIN1 VOUT1 13
VIN1 VOUT1
SLP_S3# 3 12 C557 1 2 680P_0402_50V7K
ON1 CT1 SYSON# SUSP
1 1
SUSP <21>
4 11
VBIAS GND

3
Q18A Q18B
SLP_S3# 5 10 C554 1 2 100P_0402_50V8J ME2N7002D1KW-G 2N_SOT363-6
ON2 CT2 ME2N7002D1KW-G 2N_SOT363-6
6 9 SLP_S4# 2 5 SLP_S3#
VIN2 VOUT2 <8,25,32,43,48> SLP_S4# SLP_S3# <8,26,32,35,41,49,52>
7 8
VIN2 VOUT2

4
15
GPAD
+5VS
APE8990GN3B DFN 14P

22U_0805_6.3V6M
1 1

10U_0603_6.3V6M
C570

CC56
2 2 RF@

+5VDS

RPH16
SUSP 8 1
SYSON# 7 2
SLP_S3# 6 3
SLP_S4# 5 4

100K_0804_8P4R_5%

2 2

CPU +V1.05DX_MODPHY +1.05VS


+5VDS
Max Rdson <6m ohm
1840mA
1

3 3
+5VDS R410 U44
100K_0402_5% AON6554_DFN5X6-8-5
2
1

4
R409
6

100K_0402_5% +1.05VS_MODPHY
2

3
2
1

MPHY_PWREN# 2 Q4116A
ME2N7002D1KW-G 2N_SOT363-6 C4822
3

Q4116B 2 1
1

ME2N7002D1KW-G 2N_SOT363-6
1

0.1U_0402_16V7K
5
<9> MPHY_PWREN
R4816 @
330_0402_5%
4

2
1

D
@ 2 MPHY_PWREN#
Q3 G
2N7002KW_SOT323-3 S
3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2011/06/29 Deciphered Date 2011/06/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC Interface
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.5
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B181P
Date: Tuesday, March 25, 2014 Sheet 40 of 62
A B C D E
5 4 3 2 1

WWW.AliSaler.Com

D D

+3VS

2
1 R285
C194 R284 1 2

2
14.7K_0402_1% 1M_0402_5%
3300P_0402_25V7K R286
2 +5VDS 3.3K_0402_5%

1
1 2
+5VS
R288 76.8K_0402_1%

1
8
U19A
1 2 1 2 3

P
+3VS +
R297 51.1K_0402_1% R290 10K_0402_5% 1 PWR_GD
O PWR_GD <6,8,32>
1 2 1.75VREF 2
+5VL -

G
<52> PGD_1.5V 1 2 R291 105K_0402_1%
R550 3.3K_0402_5% LM393DR2G_SO8

4
D42

1
R551 1
1 2 2 31.6K_0402_1% C195
<8,26,32,35,40,49,52> SLP_S3# R292
3.3K_0402_5% 1000P_0402_50V7K
1

2
2
3

+5VDS
DAP202UGT106_SC70-3

8
U19B
1 2 5

P
<48> DDR_PGD +
R293 3.3K_0402_5% 7
6 O
C C
-

G
1 2
<49> +1.05V_PGD
R553 3.3K_0402_5% LM393DR2G_SO8

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date Title
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
WAKE and RST-1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C 0.5
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B181P
Date: Tuesday, March 25, 2014 Sheet 41 of 62
5 4 3 2 1
A B C D E

WWW.AliSaler.Com

+3VDS Q30 +3V_PCH


ME2301D-G_SOT23-3
1 1
+3VDS 3 1

D
20mils

G
2
1

2
C590
R559
100K_0402_5% 1U_0402_6.3V6K
2

1
1
D

0.1U_0402_16V7K
<32> KBC_PWR_ON 2 1
0.47U_0402_10V5Y G

C591
1 S Q31 @

3
2N7002_SOT23-3
2
C592

@
2

2 2

3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2011/06/29 Deciphered Date 2011/06/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC DC Device-1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.5
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B181P
Date: Tuesday, March 25, 2014 Sheet 42 of 62
A B C D E
A B C D E

WWW.AliSaler.Com
Audio Board

+3V_PCH
+5VDS Card Reader Board
1
+3VS +5VDS

C113
0.1U_0402_10V6K
1
C107 ESD@
1 JAUDIO1 1
0.1U_0402_16V4Z 1 2 JSD1
2 2 1 CR_PWREN# 1
2 <9> CR_PWREN# 1
3 2
4 3 3 2
4 +3VS 3
5 4
6 5 5 4
6 +3VS_ISCT 5
USB20_N0_C 7 6
<25> USB20_N0_C 7 6
USB20_P0_C 8 <7> CLK_PCIE_CR CLK_PCIE_CR 7
<25> USB20_P0_C 8 7
9 CLK_PCIE_CR# 8
USB20_N7_C 10 9 Card Reader <7> CLK_PCIE_CR#
9 8
USB CONN <25> USB20_N7_C
<25> USB20_P7_C
USB20_P7_C 11 10
11 <10> PCIE_PTX_C_DRX_P2
PCIE_PTX_C_DRX_P2 10 9
10
12 PCIE_PTX_C_DRX_N2 11
12 <10> PCIE_PTX_C_DRX_N2 11
<10> USB20_N4 USB20_N4 13 12
USB20_P4 14 13 PCIE_PRX_DTX_P2 13 12
<10> USB20_P4 14 <10> PCIE_PRX_DTX_P2 13
15 PCIE_PRX_DTX_N2 14
15 <10> PCIE_PRX_DTX_N2 14
16 15
Finger printer <9> FPR_LOCK#
FPR_LOCK# 17 16
17
CR_RST# 16 15
16
<9> FPR_OFF FPR_OFF 18 CR_CLKREQ# 17
18 <7> CR_CLKREQ# 17
SLP_S4# 19 TP_CLK 18
<8,25,32,40,48>SLP_S4# 19 <32> TP_CLK 18
EXT_MIC_L_C 20 TP_DATA 19
<26>
<26>
EXT_MIC_L_C
HP_OUT_L 21 20
21
Touch Pad <32>
<10>
TP_DATA
CR_WAKE#
CR_WAKE# 20 19
20
<26> HP_OUT_R 22 SATA_ACT# 21
22 <6,7> SATA_ACT# 21
23 HDD_HALTLED 22
Combo Jack <26> HP_SENSE# HP_SENSE# 24 23
24
<8>
<6,7,15,16>
HDD_HALTLED
PCH_SMBCLK
23 22
23
<6,7,15,16> PCH_SMBDATA 24
25 24
26 GND1 25
GND2 26 GND1
D43 GND2
2 ACES_88514-02401-071 2
CONN@ <6,8,21,23,30,32,33> PLT_RST# 3 ACES_88514-02401-071
1 CR_RST# CONN@
<7> CR_RST#_D 2

DAP202UGT106_SC70-3
HDD_HALTLED

1
R68 TP_CLK
10K_0402_5%
+3VDS +3VS_ISCT TP_DATA

2
ESD@
JAPP1 D4
1 YSLC05CH_SOT23-3
2 1
3 2
4 3
<21> WL_LED_ALL# 4
<26> MUTE_LED_CNTR 5
6 5
<28> KSI_D_0 6
<28> KSI_D_1 7

1
8 7
<32> KSO17 8 +3VDS +3VS +3VS_ISCT
<19,32> LID_SW# LID_SW# 9 Q181
10 9
10 ME2301D-G_SOT23-3
11 13
11 G1

1
12 14 3 1

D
3 12 G2 R1430 3
E-T_6916K-Q12N-00L 47K_0402_5%

G
CONN@

2
R1431 C593

2
1 2

0.047U_0402_16V7K
1
D 330K_0402_5% 1
LID_SW# 2
<32> iSCT_LED#
G Q180 @
1 S 2N7002KW_SOT323-3

3
2
ESD@ CC124
100P_0402_25V8K
2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2011/06/29 Deciphered Date 2011/06/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC DC Device-1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.5
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B181P
Date: Tuesday, March 25, 2014 Sheet 43 of 62
A B C D E
5 4 3 2 1

WWW.AliSaler.Com EMI@
PL1
5A/0.02ohm
HCB2012KF-121T50_0805
1 2

EMI@
VIN
PJP1 ACES_59012-0080N-006 @ PL2
HCB2012KF-121T50_0805
7 8 ADPIN 1 2
5 7 8 6
ADP_SIGNAL 3 5 6 4 ADP_SIGNAL
3 4

PC8 EMI@

1000P_0402_50V7K

PC9 EMI@

2200P_0402_50V7K
100P_0402_50V8J
0.022U_0603_50V7K

0.022U_0603_50V7K
D AC_LED 1 2 CHG_LED D
1 2

PC5 EMI@
100P_0402_50V8J
1

1
PC1 EMI@

PC6 EMI@

@EMI@
PC161
EMI@
PC4
1000P_0402_50V7K

2
2

3
ESD@ ESD@
PD2 PD1
L30ESD24VC3-2_SOT23-3 L30ESD24VC3-2_SOT23-3
1

1
+5VL

PR14 @

3
E
10K_0402_5% @
B
1 2 2 PQ2
C MMBT3906H_SOT23-3 C

3
C

1
PQ1B
5 ME2N7002DKW-G 2N SOT363-6

4
+5VL
+5VL

1
1

1
@
PR12
PR11 PR13 510_0402_1%
680_0402_1% 510_0402_1%

2
AC_LED
2

2
CHG_LED
6

1
D
PQ1A <6,32> BAT_GRNLED# 2 PQ6
<32> AMBER_BATLED# 2 ME2N7002DKW-G 2N SOT363-6 G 2N7002KW 1N SOT323-3
S

3
1

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2013/09/09 Deciphered Date 2016/09/30 Title
DC Conn
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-B181P 0.5
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 25, 2014 Sheet 44 of 62
5 4 3 2 1
5 4 3 2 1

WWW.AliSaler.Com

1
ESD@ ESD@
PD10 PD11
L30ESD24VC3-2_SOT23-3 L30ESD24VC3-2_SOT23-3 EMI@ 5A/0.02ohm
PL4

3
D
VMB_A HCB2012KF-121T50_0805 BATT D
1 2

EMI@
PJP2 @ PL5
ACES_59012-0080N-006 HCB2012KF-121T50_0805
7 8 1 2
5 7 8 6 I2C_MAIN_DAT-1
MAIN_BAT_DET#-1 3 5 6 4 I2C_MAIN_CLK-1
3 4

1
0.01U_0402_50V7K
1 2 MAIN_BAT_DET#-1
1 2

EMI@ PC7
EMI@ PC10
PC3 0.1U_0603_50V7K

2
1000P_0402_50V7K EMI@

2
1

1
PR3 PR4 PR5
1K_0402_5% 100_0402_5% 100_0402_5%
2

2
I2C_MAIN_DAT <32,46>
C C

I2C_MAIN_CLK <32,46>

MAIN_BAT_DET# <32>

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2013/09/09 Deciphered Date 2016/09/30 Title
BATT Conn
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-B181P 0.5
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 25, 2014 Sheet 45 of 62
5 4 3 2 1
5 4 3 2 1

WWW.AliSaler.Com
VIN P1
30V/50A/0.0105 ohm/Vgs=2.5V
kelvin connection
30V/14.6A/0.0153 ohm/Vgs=-2.6V
PQ101
PQ102
AON6414AL_DFN8-5
P2 Ilimit=8A
8/8
B+
SI4483ADY-T1-GE3_SO8 PR102 EMI@
1 8 1 PL101
0.01_1206_1%
2 7 2 1UH_PCMB053T-1R0MS_7A_20%
3 6 3 5 1 4 1 2
5
220K_0402_5%

220K_0402_5%
2 3
0.1U_0402_25V6
1

PC107 EMI@

PC129 EMI@
10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

PC130 @RF@

PC131 @RF@
0.022U_0402_25V7K

0.022U_0402_25V7K

68P_0402_50V8J

82P_0402_50V8J
4

4
1
PR101

PC101

PR103

2200P_0402_50V7K
1000P_0402_25V8J

BAT54WS-7-F_SOD323-2

1
PC103

PC104

PC105
PC102

1
D D

@EMI@
PC108

PC160
0.1U_0402_25V6
2

2
@ 1 2
2

2
4.12K_0603_1%

4.12K_0603_1%
1

1
@ PD101
@

2
ACFET_CHG

PR104

PR105

0.1U_0402_25V6

0.1U_0402_25V6
1
6

1
PC109

PC110
PQ103A
2 ME2N7002DKW-G 2N SOT363-6

2
30V/14.6A/0.0153 ohm/Vgs=-2.6V
1
ME2N7002DKW-G 2N SOT363-6

B+ P2 PQ105

5
SI4483ADY-T1-GE3_SO8

CHRG_ADP_DET

ACDRV_CHG

CMSRC_CHG

ACP_CHG

ACN_CHG
3

100K_0402_5%

+3VDS 30V/12A/0.024 ohm 1 8


PQ103B

ACDET>1.8V(ACPRES open) 2 7
PR107

PQ104 3 6
ACDET<1.8V(ACPRES close)
5
1
PR108
2 4
SIS412DN-T1-GE3_POWERPAK8-5 P1 5
2

1
2.2_0402_1%
4

4
PU102 PR109

21
5

1
BQ24736RGRR_QFN20_3P5X3P5 10_1206_1%
ACDET<0.6V(UVLO)

ACPRES

ACDRV

ACP
CMSRC

ACN

PAD

3
2
1
PC111 3265mA(max)charge 3S2P BATT

2
ACDET<3.15V(OVP) 1U_0603_25V6K Ilimit=4A
ADP_EN <32> 6000mA(mzx)discharge 3S2P
6 20 VCC_CHG 1 2
ACDET VCC PR110
PL102
0.02_1206_1%
4.7U 20% VMPI0703AR-4R7M-Z01 5.5A
ICS 7 19 LX_CHG 1 2 CHG 1 4
IOUT PHASE
2 3

4.7_1206_5%
1
<32,45> I2C_MAIN_DAT 8 18 DH_CHG

CSON1
CSOP1
SDA HIDRV

EMI@
PR111
PR112 PC112
2.2_0402_1% 0.047U_0402_25V7K

kelvin connection
9 17 BST_CHG 1 2BST_CHG-1 1 2

RB551V-30_SOD323-2
SI7716ADN-T1-GE3_POWERPAK8-5
<32,45> I2C_MAIN_CLK SCL BTST

10U_0805_25V6K
@

0.1U_0402_25V6
0.1U_0402_25V6
2

1
PQ106
C C
+3VDS

PC115

10U_0805_25V6K PC116
1

1
2200P_0402_50V7K PC117

@EMI@
PC113

PC114

PD102
10 16 REGN_CHG

0.01U_0402_50V7K PC118
LDO=6V

1 SNB_CHG
<53> SRSET

close to IC

close to IC
ILIM REGN

LODRV
4/11 PD103
DLIM

GND
SRN

SRP

EMI@ 2

2
1

RB751V-40_SOD323-2 4
0.01U_0402_50V7K

2
2 1
1

PC119

PR113
+5VS VIN
11

12

13

14

15

EMI@
680P_0402_50V7K
22K_0402_1%

PC121
PC120
2

3
2
1
DL_CHG
1U_0603_25V6K
SRN_CHG

SRP_CHG

2
CHRG_ADP_DET <32>
1

PR114 PR115
18.2K_0402_1% 127K_0402_1% PR116 PR117
1M_0402_5% 10K_0402_5%
PD104 <53> V_3.9K 1 2
2

LL4148_LL34-2
2 1 30V/16A/0.0165 ohm
0.01U_0402_50V7K
100P_0402_50V8J
1

PC123

PR120
1

PC122

10_0402_5%
PR118 PR119 1 2
2

10K_0402_1% 20K_0402_1%
2

1
2

PR121 PC124
6.8_0402_5% 0.1U_0603_25V7K
2

1 2

PR122
VIN Vacdet Vchag_adp_det Vvoltage_adc 46.4K_0402_1%
1 2
CURRENT_ADC <32>
100P_0402_50V8J

H 2.58V 2.99V 1.4V


1

1
PC125

PC126
B B
0.22U_0402_16V7K
2

L 1.07V 0V

VIN
PR124 PR125
49.9K_0402_1% 576K_0402_1%
1 2 1 2
VOLTAGE_ADC <32>
100P_0402_50V8J

1
1

1
PC127

PR126 PC128
49.9K_0402_1% 0.22U_0402_6.3V6K
2

2
2

Ilimit=20*(Vsrp-Vsrn)=20*Ich*Rch
up to Ilimit=1.6V(disable)
R=10m ohm I=8A
R=20m ohm I=4A
fs=750k
Iripple=Vin*D(1-D)/(fs*L),
A
D=0.5 (worst) A
Iripple=1.418A
Isat(L)=Ichg+0.5*Iripple=4+0.5*1.418=4.709A
ILIM>1.6V disable
ILIM<75mV disable
ILIM>105mV enable

DLIM>1.1V disable Security Classification Compal Secret Data Compal Electronics, Inc.
DLIM<870mV disable
DLIM>896mV enable(buck to boost) Issued Date 2013/09/09 Deciphered Date 2016/09/30 Title
CHARGER
default dischager current limit 4.096A THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-B181P 0.5
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 25, 2014 Sheet 46 of 62
5 4 3 2 1
5 4 3 2 1

WWW.AliSaler.Com

D D

Leave ENTRIP1(2) floating or drive it


PC320
100P_0402_50V8J above 4.5V to shut down channel 1(2)
1 2

PR304 PR305
13.7K_0402_1% 30K_0402_1% +5VDSP
1 2 2 1
+3VDSP

PR308 196K_0402_1%

68K_0603_5%

PR309 174K_0402_1%
B+ B++ PR306 PR307 B++
20K_0402_1% 20K_0402_1%

1
2 1 1 2
EMI@ PL301
HCB2012KF-121T50_0805 Vfb=2v

2200P_0402_50V7K
PR310
1 2
2200P_0402_50V7K

10U_0805_25V6K

10U_0805_25V6K
ENTRIP2 2

ENTRIP1 2
10U_0805_25V6K

10U_0805_25V6K

1
PC306

PC307

PC308
1

1
@EMI@

@EMI@
PC305

PC304

PC303

FB_3V

FB_5V

1
PC321

2
5
1U_0402_10V6K
2

5
PQ301

2
11/07
SIS412DN-T1-GE3_POWERPAK8-5

1
<8> 3V_PG

FB2

ENTRIP2

ENTRIP1

FB1
TON
4 21
C 6 PAD 4 PQ302 C
PC310 PR313 PGOOD 20
0.1U_0603_25V7K 2.2_0603_5% BYP1 PR312 PC311 SIS412DN-T1-GE3_POWERPAK8-5
2 1BST_3V-1 1 2 BST_3V 7 2.2_0603_5% 0.1U_0603_25V7K
1
2
3

BOOT2 19 BST_5V 1 2 BST_5V-1 1 2


Rdc=22m ohm

3
2
1
BOOT1
PL303 UG_3V 8 Rdc=15.5m ohm
3.3UH_PCMB063T-3R3MS_6.5A_20% UGATE2 18 UG_5V
UGATE1 8785mA(max)
1 2 PL302
+3VDSP LX_3V 9 2.2UH +-20% ETQP3W2R2WFN 8.5A
PHASE2 +5VDSP
17 LX_5V 1 2
SI7716ADN-T1-GE3_POWERPAK8-5

PHASE1
1

5
4.7_1206_5%

7308mA+1000=8308mA

1
EMI@

PQ303
PR314

4.7_1206_5%
LG_3V 10
150U_D2_6.3VY_R17M

LGATE2

EMI@

PR315
16 LG_5V

SI7716ADN-T1-GE3_POWERPAK8-5

150U_D2_6.3VY_R17M
ENLDO
LGATE1

5
LDO5

LDO3
ENM

PQ304
VIN
220U_6.3V_M

1 1 PU301
2

220U_6.3V_M
PCZ74

4 1 1

2
PC314

+ +

PCZ75
RT8243AZQW_WQFN20_3X3

11

12

13

14

15
+3VLP +3VL
1
680P_0402_50V7K
EMI@ PC313

PC315
+ +

680P_0402_50V7K
@ 4
2 2

PC312
PJP304 @ @
2

1
2
3

PC106 JUMP_43X39 2 2

2
PR321 0.1U_0402_25V6 1 2
1 2

EMI@
499K_0402_1%

3
2
1
1 2 ENLDO_3V_5V Typ: 175mA
B++

1
2
PC302

1
100K_0402_1%

1U_0402_10V6K
0.1U_0603_25V7K

Rds(on)=16.5m-13.5 ohm(low side) 4.7U_0805_10V6K

2
1

1
PC319

PC316
PR325
Ventrip=Ientrp*Rentrip=0.5-2.7V,Ientrp=10uA

ENM
2

<53>
100K_0402_1% PR324
2

2
B OVP=3.3*1.16=3.83V(max) +5VLP +5VL Rds(on)=16.5m-13.5 ohm(low side) B

2
D=VO/Vin=3.3/19=0.174 PJP306 @ Ventrip=Ientrp*Rentrip=0.5-2.7V,Ientrp=10uA
△I=(Vin-Vo)*ton/L=(Vin-Vo)*DT/L=2.21A JUMP_43X39
1 2 settting OCP=8.785*1.2=10.54A
Ilimit=7.3-2.21/2=6.195A 1 2

+3VLP
Iocp=6.195*1.2=7.434A Typ: 225mA Rlimit=(Ron*Ilimit)*10/10u=(13.5m*10.54)*10/10u=143k

1
Rlimit=(Ron*Ilimit)*10/10u=(13.5m*7.434)*10/10u=100k OVP=5*1.16=5.8V(max)
PC317
4.7U_0805_10V6K

2
OVP=5*1.16=5.8V(max)
D=VO/Vin=5/19=0.263
△I=(Vin-Vo)*ton/L=(Vin-Vo)*DT/L=5.21A
Ilimit=8.785-5.21/2=6.18A
Iocp=6.195*1.2=7.416A
Rlimit=(Ron*Ilimit)*10/10u=(13.5m*7.416)*10/10u=100k
PJP302 @
JUMP_43X118
<1>5V=283KHz 3V=330KHz (Vin=6.5 ~ 12v) +5VDSP 1
1 2
2 +5VDS
<2>5V=321KHz 3V=375KHz (Vin=12 ~ 25v)
(By Rton= 68K ohm) PJP303 @
+3VDSP JUMP_43X118
1 2
+3VDS
1 2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2013/09/09 Deciphered Date 2016/09/30 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
3VDSP/5VDSP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-B181P 0.5
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 25, 2014 Sheet 47 of 62
5 4 3 2 1
5 4 3 2 1

WWW.AliSaler.Com

EMI@
PLM1
HCB2012KF-121T50_0805 PCM2 PRM1
B+ 1 2 B+_DDR 0.22U_0402_10V6K 2.2_0402_1%
1 2 BST_DDR-1 1 2
D D

1
@EMI@
PCM13 PCM1 PCM3
2 2200P_0402_50V7K 10U_0805_25V6K 4.7U_0805_25V6-K

2
+1.35VP
+0.675VSP

5
PQM1

BST_DDR
DH_DDR
400mA

LX_DDR

10U_0805_6.3V6K

10U_0805_6.3V6K
1

1
PCM4

PCM5
4

16

17

18

19

20

2
SIS412DN-T1-GE3_POWERPAK8-5

PHASE

UGATE

BOOT

VTT
VLDOIN
1
2
3
21
PAD
PLM2 DL_DDR 15 1
2.2UH_ETQP3W2R2WFN_8.5A_20% LGATE VTTGND
1 2
+1.35VP 14 2

SI7716ADN-T1-GE3_POWERPAK8-5
PGND VTTSNS
1

5
PRM3

PQM2
EMI@ 13.3K_0402_1%
220U_D2 SX_2VY_R9M

6296mA PRM2 1 2 CS_DDR 13 PUM1 3


4.7_1206_5% CS RT8207MZQW_WQFN20_3X3 GND
+5VDS
330U_2.5V_M

1 1
1SNB_DDR 2
PCZ76

4 12 4 VTTREF_DDRT
VDDP VTTREF
PCM6

C + + PRM4 C
5.1_0603_5%
@
2 2
1 2 VDD_DDR 11
VDD VDDQ
5 +1.35VP

PGOOD
1
2
3

1
EMI@

TON
PCM7 +5VDS PCM8 PCM9 PCM10

FB
S5

S3
680P_0603_50V7K 1U_0603_10V6K 1U_0603_10V6K 0.033U_0402_16V7K
2

2
Rds(on)0.0165-0.0135 ohm

10

6
Vfb=0.75V

FB_DDR
S5_DDR

S3_DDR
TON_DDR
Vop=1.2*1.35=1.62V 11/07 PRM5
<41> DDR_PGD
8.06K_0402_1%
Rilim=limit*Rds(on)/10uA,limit=13300/0.0165*10u=8.06A(min) 1 2 +1.35VP

1
ton=3.85p*Rton*Vddq/(Vin-0.5)=3.85p*887k*1.35/(19-0.5)=249n
PRM8
f=Vddq/(Vin*ton)=285.3Khz 10K_0402_1%
@

2
PRM6 PJPM2
887K_0402_1% JUMP_43X118
B+_DDR 1 2 1 2
+1.35VP 1 2 +1.35V_VDDQ
B B

@
PJPM1
JUMP_43X39
PRM9 1 2
<8,25,32,40,43> SLP_S4#
0_0402_5% +0.675VSP 1 2
+0.675VS
1 2

PRM11
0_0402_5%
<4,15> SM_PG_CTRL 1 2

11/07
1

1
@ @
PCM11 PCM12
0.1U_0402_10V7K 0.1U_0402_10V7K
2

2
A A

Security Classification Compal Secret Data


Title
Compal Electronics, Inc.
Issued Date 2013/09/09 Deciphered Date 2016/09/30
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+1.35V/+0.675VS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-B181P 0.5
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 25, 2014 Sheet 48 of 62
5 4 3 2 1
5 4 3 2 1

WWW.AliSaler.Com

D D

PRH1
0_0402_5%
1 2 SLP_S3# <8,26,32,35,40,41,52>

1
@
PRH2 PCH1
1M_0402_1% 0.22U_0402_10V6K

2
2
EMI@ PRH4 PCH3
PLH1 PUH1 0_0603_5% 0.1U_0603_25V7K
HCB2012KF-121T50_0805 SY8206DQNC_QFN10_3X3 1 2 BST_1.05Vn1 2
+1.05VSP +1.05VS
B+ 1 2 B+_1.05V 8
IN EN
1

10U_0805_25V6K
6 BST_1.05V PLH2 @ PJH1
BS
1

PCH6
@EMI@ 1UH_PCMB063T-1R0MS_12A_20% JUMP_43X118
PCH4 PCH5 9 10 LX_1.05V 1 2 1 2
2200P_0402_50V7K 10U_0805_25V6K GND LX 1 2
2

1
TDC 6A
@EMI@

1
4 FB_1.05V PRH3 4738mA
FB 4.7_1206_5% PCH7 PCH9 PCH8 PCH10 PCH11
ILMT_1.05V3 7 330P_0402_50V7K 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M

2
C ILMT BYP Rup C
2 5 +3VLDO_1.05V PRH5

1SNB_1.05V
PG LDO FB_1.05V 1 2

1
11/07
PCH12 FB = 0.6V 15K_0402_1%

1
4.7U_0603_6.3V6K Vout=0.6V* (1+Rup/Rdown)

2
@EMI@
+3VLDO_1.05V PCH2 PRH7
680P_0603_50V7K 20K_0402_1%

2
<41> +1.05V_PGD Rdown

2
1

@
PRH8
0_0402_5%
low:6A floating:8A High:12A
2

ILMT_1.05V
OCP:8A
1

fs=800Khz
@ Ipk=Vo*(1-Vo/Vin,max)/(fs*L)=19*(1-3.3/19)/(800k*1u)=1.24A
PRH9
0_0402_5%
Imax=Io,max+Ipk/2=7.64A
2

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2013/09/09 Deciphered Date 2016/09/30 Title
+1.05VS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-B181P 0.5
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 25, 2014 Sheet 49 of 62
5 4 3 2 1
5 4 3 2 1

WWW.AliSaler.Com
PRZ5:Vo-usr=1.7*(150/(150+9.53))=1.598V
Vusr=540mV
PRZ11:disable OSR&PT,Rosr=150k
PRZ10:setting fs R=150==>1Mhz
Ramp setting:
EMI@
PRZ9=100K type:160mV PHZ1 is between PUZ2 and PUZ3 PLZ1

PCZ12 100K_0402_1%_NCP15WF104F03RC
PRZ9>=150K type:40mV HCB2012KF-121T50_0805
VREF CPU_B+ 1 2
D boot voltage setting: B+ D

1
Vb-ram=1V==>2V 1 1
@ PRZ1

4700P_0402_16V7K
1

1
+ +

1M_0402_1%
10K_0402_1% @EMI@

390K_0402_1%

100K_0402_1%
Vb-ram=0V==>1.7V

9.53K_0402_1%
1

1
PHZ1
PCZ3 PCZ5 PCZ10 PCZ11 PCZ6 PCZ7 PCZ8
Vb-ram>1.525V==>0V

15W@

15W@
PCZ1

PRZ2

PRZ3

PRZ4

PRZ5
2200P_0402_50V7K 10U_0805_25V6K 10U_0805_25V6K 10U_0805_25V6K 10U_0805_25V6K 100U_25V_M 100U_25V_M

2
2 2

15W@
Iccmax=32A(15w),Iccmax=40A(28w)

2
@

2
IccTDC=10A(15w),IccTDC=16A(28w)

1
IccDyn=27A(15w),IccDyn=32A(28w) PRZ6
39K_0402_1%

1
39K_0402_1%

150K_0402_1%
9.1K_0402_1%
OCP voatge seeting:

.1U_0402_16V7K
1

1
15W@
PRZ8

PRZ9

150K_0402_1%

150K_0402_1%
2
PRZ8=39K ==>18.9mV

1
PRZ7

PRZ10

PRZ11
Vimon=1.7V

2
Rp_n=10.74k Rcs(eff)=0.6m ohm

2
1.7V=10*(1+Rimon/39k)*0.6m*32,Rimon=345k
ALERT goes low,THERM=1.08V

B-RAM
PRZ12 SLEWA EMI@ EMI@

OCP-I
VR_HOT goes low,THERM=1.1V 10K_0402_1% F-IMAX PCZ13 PRZ13
CPU_B+ 2 1 680P_0402_50V7K 4.7_1206_5%
O-USR 1 2 1 2

slew rate(15w,150K)=96mV/uS,slew rate(28w,100K)=84mV/uS


CPU_B+

16

15

14

13

12

11

10
address selection(15w):1.7*100/(100+150)=0.68V

9
PU1 0.15UH_ETQP4LR15AFM_29A_20%
PLZ2

9
address selection(28w):1.7*100/(100+100)=0.85V

IMON

O-USR
VBAT

OCP-I
SLEWA

THERM

B-RAMP

F-IMAX
PRZ14 5 PGND2 4 VSW1_LX 1 4
C
On-tome(ton):ON-time is fixed based on 2.2_0402_1% VIN VSW +VCC_CORE C
CSP1 17 8 2 1 6 3 2 3
the input voltage (at the VBAT pin) @15W@ CSP1 VR_ON VR12.5_VR_ON <11> BOOT_R PGND1 +5VS

PRZ17 15W@
PRZ36 CSN1 18 7 SKIP 1 2 7 2 CSN1
CSN1 SKIP# BOOT VDD

3K_0402_1%
Vssense and Vccsense need to 0_0402_5%

10K_0402_1%_TSM0A103F34D1RZ
1
1 2 CSN2 19 6 PWM1 PCZ14 8 1

0.15U_0402_10V6K

0.15U_0402_10V6K
be difference pair CSN2 PWM1 PWM SKIP#

1
.1U_0402_16V7K
1 2 CSP2 20 5 PWM2 PUZ2 PRZ16 PCZ15
PRZ15 0_0402_5% 15W@ CSP2 PWM2 CSD97374CQ4M_SON8_3P5X4P5
Droop:Error amplifier output. 0_0402_5% 1U_0603_10V6K

2
21 TPS51622ARSMR_QFN32_4X4 4 PWM1
+3VS

2
NC MODE

1
15W@

PCZ16

PCZ17
2
PRZ19 22 3 SKIP PRZ18
<13> VSSSENSE NC PGOOD VR12.6PG_MCP <11>

1
0_0402_5% 10K_0402_1%

2
1 2 GFB 23 2 @
GFB VDD

VR_HOT#

2
ALERT#
1 2 VFB 24 1 VR_SVID_DAT
DROOP

VFB
COMP

VDIO

2
VREF

VCLK

1_0402_5%

PHZ2
PRZ23 15W@

GND

PAD

2
V5A
PRZ20

PRZ21
2.67K_0402_1%
0_0402_5% 2 1 CSP1
<11> VCCSENSE 11/07
25

26

27

28

29

KBC_PROC_HOT# 30

31

32

33

1
PCZ18

1
1U_0402_6.3V6K PHZ2 is next to PLZ2

VR_SVID_ALRT#

2
@ PCZ19 VR_SVID_CLK
100P_0402_50V8J
1 2 PRZ24 15W@ 28WEMI@ 28WEMI@
5.36K_0402_1% +3VS PCZ20 PRZ26
NTC
PRZ25 1 2 680P_0402_50V7K 4.7_1206_5% B value=3435 K
10K_0402_1% 1 2 2 1
1 2 VREF
DCR=0.72m ohm
B PRZ27 15W@ CPU_B+ 28W@ B
PCZ21
1

4.87K_0402_1% 0.15UH_ETQP4LR15AFM_29A_20%
PLZ3

9
1 2 1 2 PCZ22
0.33U_0402_10V6K 28W@ PRZ28 5 PGND2 4 VSW2_LX 1 4
+VCC_CORE
2

15W@ 2.2_0402_1% VIN VSW


4700P_0402_25V7K 2 1 6 3 2 3
PRZ29 BOOT_R PGND1 +5VS 40000mA
10_0603_1% 1 2 7 2 CSN2
BOOT VDD

PRZ31 28W@
1 2
+5VS +1.05VS_VCCST

10K_0402_1%_TSM0A103F34D1RZ
8 1

3K_0402_1%
ALERT between VCLK and VDIO to reduce cross-talk. PCZ23

0.15U_0402_10V6K

0.15U_0402_10V6K
PWM SKIP#
1

1
.1U_0402_16V7K 28W@ 28W@

28W@
PCZ24 28W@ PUZ3 PRZ30 PCZ25
1U_0603_10V6K CSD97374CQ4M_SON8_3P5X4P5

61.9K_0402_1%
0_0402_5% 1U_0603_10V6K
2

PCZ28 @
PWM2 28W@
54.9_0402_1%
2

1
28W@
130_0402_1%

PRZ32

PCZ27
2

1 2
1

PRZ33

PRZ34
SKIP
PCZ26

2
.1U_0402_16V7K
2

28W@
1

28W@

PHZ3
28W@ PRZ27 PRZ35

2
10K_0402_1% VR_SVID_CLK 2.1K_0402_1%~N
<11> VR_SVID_CLK 2 1 CSP2
VR_SVID_ALRT#
<11> VR_SVID_ALRT#
28W@ PCZ21 VR_SVID_DAT PHZ3 is next to PLZ3
1500P_0402_50V7K
<11> VR_SVID_DAT
KBC_PROC_HOT#
28W@ PRZ24 28W@ PRZ9
<4> KBC_PROC_HOT#
4.12K_0402_1% 100K_0402_1%
1

@ PCZ29
A 28W@ PRZ2 47P_0402_50V8J A
187K_0402_1% 28W@ PRZ17
2

3K_0402_1%

28W@ PRZ23
28W@ PRZ4 2.1K_0402_1%
806K_0402_1%
28W@ PRZ18 Security Classification Compal Secret Data Compal Electronics, Inc.
28W@ PRZ5 61.9K_0402_1% 2013/09/09 2016/09/30 Title
280K_0402_1%
Issued Date Deciphered Date
+CPU_CORE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
not mount需特別注意(15w@,28w@) AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-B181P 0.5
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 25, 2014 Sheet 50 of 62
5 4 3 2 1
5 4 3 2 1

WWW.AliSaler.Com
+VCC_CORE

1
PCZ51 PCZ52 PCZ53 PCZ54 PCZ55 PCZ56 PCZ57 PCZ58 PCZ59 PCZ60
D 2 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M D

150U 2V M D2 ESR9M SX H1.9


1

@ PCZ73
1

1
@ @ @ @ +
PCZ61 PCZ62 PCZ63 PCZ64 PCZ65 PCZ66 PCZ67 PCZ68 PCZ69 PCZ70
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2

2
2

C C

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2013/09/09 Deciphered Date 2016/09/30 Title
PROCESSOR DECOUPLING
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-B181P 0.5
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 25, 2014 Sheet 51 of 62
5 4 3 2 1
A B C D

WWW.AliSaler.Com UMA@
PR1502
0_0402_5%
1 2 SLP_S3# <8,26,32,35,40,41,49>

1
1
11/07 @UMA@ UMA@
PC1502 PR1503
0.1U_0402_16V7K 1M_0402_5%

2
UMA@

2
PU1501
1
<41> PGD_1.5V 1

9
FB_1.5V 1 PGND 8
FB SGND UMA@ +1.5VSP @ +1.5VS
PJP305 @ PGD_1.5V 2 7 EN_1.5V PL1501 PJ1502
JUMP_43X39 PG EN 1UH_PH041H-1R0MS_3.8A_20% JUMP_43X79
1 2 VIN_1.5V 3 6 LX_1.5V 1 2 1 2
+3VDS 1 2 IN LX 1 2
4 5 Short@UMA
PGND NC

1
UMA@ 68P_0402_50V8J 3mA

1
PC1501 @UMAEMI@ UMA@ UMA@ UMA@
22U_0603_6.3V6M SY8003DFC_DFN8_2X2 PR1504 PC1503 PC1504 PC1505 OCP:3A

2
4.7_0603_5% UMA@ 22U_0603_6.3V6M 22U_0603_6.3V6M

2
30K_0402_1%
Rup

2
PR1505
FB_1.5V 1 2
FB=0.6V
Vout=0.6V*(1+Rup/Rdown)

1
1
@UMAEMI@ UMA@
PC1506 PR1506
680P_0402_50V7K 20K_0402_1%

2
Rdown

2
2 2

DIS@
PRW3
0_0402_5%
1 2 SLP_S3# <8,26,32,35,40,41,49>

1
DIS@ @DIS@
PRW4 PCW4
1M_0402_1%

2
0.22U_0402_10V6K

2
DIS@ DIS@
DISEMI@ DIS@ PRW5 PCW5
PLW1 PUW1 0_0603_5% 0.1U_0603_25V7K
HCB2012KF-121T50_0805 SY8206DQNC_QFN10_3X3 1 2 BST_VRPn 1 2
+VRAMP +1.5VS
B+ 1 2 B+_VRP 8
IN EN
1
DIS@
6 BST_VRP PLW2 PJPW1 @
BS
1

@DISEMI@ @DIS@ DIS@ 1UH_PCMB063T-1R0MS_12A_20% JUMP_43X118


PCW1 PCW2 PCW3 9 10 LX_VRP 1 2 1 2
2200P_0402_50V7K 10U_0805_25V6K 10U_0805_25V6K GND LX 1 2
2

1
@DISEMI@ DIS@

1
4 FB_VRP PRW6 DIS@ PR9515 DIS@ DIS@ DIS@ DIS@
@DIS@ FB 4.7_1206_5% PCW6 0_0402_5% PCW7 PCW8 PCW9 PCW10
3 3

PRW7 ILMT_VRP 3 7 330P_0402_50V7K 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 6000mA

2
10K_0402_5% ILMT BYP Rup 15K_0402_1%
+3VLDO_VRP

2
+3VS 1 2 2 5 +3VLDO_VRP DIS@ PRW1

1SNB_VRP
PG LDO FB_VRP 1 2
1

DIS@
1

1
PCW11 DIS@ FB = 0.6V
@DIS@ 4.7U_0603_6.3V6K PRW2 Vout=0.6V* (1+Rup/Rdown)
2

PRW8 @DISEMI@ 10K_0402_1% @DISEMI@ PR9516


0_0402_5% PCW12 10_0402_1%
680P_0603_50V7K
1 2

2
ILMT_VRP <41> PGD_1.5V Rdown 1 2 +1.5VS <12,26,35>
@DIS@
PRW9
0_0402_5%
2

low:6A floating:8A High:12A


OCP:8A

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2013/09/09 Deciphered Date 2016/09/30 Title
+1.5VS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-B181P
LA-8551P 0.5
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 25, 2014 Sheet 52 of 62
A B C D
5 4 3 2 1

WWW.AliSaler.Com

D D

+3VDS

1
PRA2
<46> V_3.9K
100K_0402_5%

2
LBSS84LT1G_SOT23-3 SRSET <46>

PRA1 PQA1 PRA3

1
100_0402_5% 100K_0402_5% C

D
ADP_SIGNAL 1 2 3 1 1 2 2 PQA2
B MMBT3904WH_SOT323-3
E

3
1

1
G
1

2
+3VDS @ PRA7
PRA4 PRA5 PRA6 PCA1 619_0402_1%
13K_0402_1% 8.06K_0402_1% 3.9K_0402_5% 3900P_0402_50V7K

2
2

B
2

2
C C
E
3 1 VIN
OCP_A_IN <32>

C
PQA3
MMBT3906H_SOT23-3
1

1
+3VDS

3
E
@
B
PRA8 PRA9 PDA2 PRA10 2 PQA4
8.66K_0402_1% 220K_0402_5% GLZ4.7B_LL34-2 3.24K_0402_1% MMBT3906H_SOT23-3
C
2

1
ADP_A_ID <32>
1

D
2 PQA5
<32> ADP_ID_CHK
1

1
G 2N7002KW 1N SOT323-3
S
3

PRA11 PRA12
45.3K_0402_1% 130K_0402_1%
PH1 is next to CPU :
2

2
CPU thermal protection at 92 degree C
Recovery at 56 degree C
MEMO:PRA4 and PQA5 are not mount
+5VL
PRA13 +5VL
P1 470K_0402_1% +5VL
1 2

2
B +3VDS +3VL B
1

PR19

1
47K_0402_1%
1

PRA14 +5VL PH1 PC13 ENM <47>


200K_0402_1%
PRA15 PRA19 @ 0.1U_0603_25V7K PR25

1
47K_0402_5% 47K_0402_5% 100K_0402_1%_NCP15WF104F03RC 47K_0402_1%
2

PU2A 1 2

2
3 PR27
P

8
1 ADP_PRES <32> 13.7K_0402_1% PU2B
O

1
2 1 2 5 D

P
- +
G

7 2 PQ7
LM393DG_SO8 TM_REF1 6 O G 2N7002KW 1N SOT323-3
4

-
1

G
S

3
1

PRA16 PRA17 LM393DG_SO8

4
86.6K_0402_1% 100K_0402_1% PRA18 PCA2

0.22U_0805_16V7K
47K_0402_5% 0.01U_0402_16V7K
2
2

+5VL

17.4K_0402_1%
1

1
PC16

1000P_0402_50V7K
PR26
2 1
+5VL

PC15
PR28

2
100K_0402_1%

1
PR29
100K_0402_1%
A A

2
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2013/09/09 Deciphered Date 2016/09/30 Title
ADP_OCP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-B181P 0.5
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 25, 2014 Sheet 53 of 62
5 4 3 2 1
A B C D E

WWW.AliSaler.Com <34> VGA_VSSSENSE VGA_VCCSENSE <34>

VGA@

1
VGA@
PRV28 PRV29
0_0402_5% 0_0402_5%

2
10_0402_1% 1_0402_1% VGA@
1 2 1 2 +VGA_CORE
PRV30 PRV31

0.22U_0603_25V7K
VGA@

PCV86
2
@VGA@
1 1

1
1 2

10K_0402_1%
@VGA@

PRV32
PCV87
270P_0402_50V7K VGA@ +5VS
VGA@ PRV33 PRV34 VGA@

2
10K_0402_1% 84.5K_0402_1%
1 2 1 2
VGA@ PRV37 GPU_B+
+1.8VS_VGA +3VS 1 2

1
10K_0402_1%

10K_0402_1%
PCV88 VGA@ PCV89 VGA@

VGA_ISEN1P @VGA@ PRV35

@VGA@ PRV36
270P_0402_50V7K 27P_0402_50V8J 137K_0402_1%

1
VGA@ @VGA@ 1 2 1 2
PRV38 PRV39
2.2_0402_1% 2.2_0402_1%

VGA_TONSET
2

VGA_COMP
GPU_VDDIO

VGA_ISEN1N
VGA_FB

VGA_BOOT2
+5VS

VGA_ISEN2N

VGA_ISEN2P

VGA_UGATE2
+1.8VS_VGA VGA@ GPU_B+ EMIVGA@ PL1000
PRV6 0_0603_5% HCB2012KF-121T50_0805

13

12

11

10

1
VGA_UGATE1 1 2 1 2 B+

PWM3

BOOT2

UGATE2
COMP

FB

VSEN

ISEN3N

ISEN3P

ISEN1P

ISEN1N

ISEN2N

ISEN2P

TONSET
1

PCV3 VGA@

2200P_0402_50V7K
10U_0805_25V6K

10U_0805_25V6K

0.1U_0402_25V6
MDV1525URH_PDFN33-8-5
1

@EMIVGA@
PRV43 53 VGA@
GND

@EMIVGA@
4.7K_0402_1% VGA@ PRV40

1
+5VS

PQV1 VGA@

VGA@
PCV2
VGA@ 14 52 VGA_PHASE2 PRV41 10K_0402_1%
RGND PHASE2

PCV4
PCV91
VGA@ 2.2_0402_1%
2

2
VGA_IMON 15 51 VGA_LGATE2 VGA_PVCC 1 2 4

2
PUV1_PWROK PRV78 1K_0402_1% IMON LGATE2
1 2 VGA_VREF 16 50 VGA_PVCC VGA_PHASE1
VGA@ V064 PVCC VGA_VCC 1 2 VGA@ PRV10 VGA@ PLV2
PCV93 17 49 VGA_LGATE1 2.2_0603_1% 0.36UH_PDME064T-R36MS_24A_20%

3
2
1
IMONA LGATE1

VGA@
2.2U_0603_10V7K PRV42 VGA_BOOT1 1 2 1 2
VGA_BOOT1-1 1 4

2.2U_0603_10V7K

2.2U_0603_10V7K
1

1
PCV94

VGA@ PCV95
<9,33> VGA_PWRGD 1 2 GPU_VDDIO 18 PUV1 VGA@ 48 VGA_PHASE1 2.2_0603_5% +VGA_CORE
VDDIO PHASE1

@EMIVGA@
VGA@ VGA@ PCV9 2 3

4.7_1206_5%
5
VGA@ 1 2 PUV1_PWROK 19 47 VGA_UGATE1 0.22U_0603_25V7K VGA@

2
PWROK UGATE1

1
VGA@ PQV20
PD16 RB751V-40_SOD323-2 RT8880CGQW_WQFN52_6X6 PRV44

MDU1511RH_POWERDFN56-8-5

PRV9
<34> GPU_SVC 1 2 20 46 VGA_BOOT1 3.4K_0402_1%
VGA@ PRV45 0_0402_5% SVC BOOT1 VGA@ 1 2 1 2
<34> GPU_SVD 1 2 21 45 PRV46 0_0603_5% VGA@ 31000mA(TDC)
VGA@ PRV48 0_0402_5% SVD LGATEA1 VGA_LGATE1 1 2 4 PCV96

1 2
<34> GPU_SVT 1 2 22 44 VGA_SNB_APU1 .1U_0402_16V7K load line:1m ohm
SVT PHASEA1

@EMIVGA@
PCV12
VGA@ PRV50 0_0402_5% VGA@

680P_0603_50V7K
7.32K_0402_1% 23 43 PRV49 slew rate:50mV/uS
OFS UGATEA1
1

1
2 PCV99 10K_0402_1% 2

3
2
1

2
VGA@

PRV47
.1U_0402_16V7K 24 42
@VGA@ OFSA BOOTA1

2
VGA_SET1 25 41
SET1 PWMA2 VGA@ PRV52 GPU_B+
2

VGA_SET2 26 40 1 2

VGA_ISEN1N-1
SET2 TONSETA

PGOODA
ISENA2N

ISENA1N
ISENA2P

ISENA1P
12.4K_0402_1% 137K_0402_1%

PGOOD
VGA_ISEN1P

COMPA

VSENA
OCP_L
VGA@ +5VS

IBIAS
VCC
PRV51

FBA

EN
1 2 PRV53 VGA@
1.3K_0402_1%

27

VGA_VCC28

1 VGA_IBIAS 29

30

31

32

33

34

35

36

37

38

39
14K_0402_1%

1
VGA_ISEN1N 2
100K_0402_1%_TSM0B104F4251RZ

<9,33> GPU_PGD
1

EC_THERM# <34>
VGA@

@VGA@
PHV2

PRV55

PHV2 is next to PLV2 PRV62

0.1U_0402_25V6
1

1
PCV97
5.76K_0402_1%

1K_0402_1%
@VGA@
1 2 +3VS
2

2
@VGA@

PRV80
VGA_VREF

100K_0402_1%
PRV59 10K_0402_1%

2
VGA@

PRV60
VGA@ VGA@ PRV61 10K_0402_1%
1
VGA@

0.47U_0402_16V4Z
1

VGA@ PCV98

PRV64 1 2 +3VS

2
10K_0402_1%
VGA_EN <8,35> GPU_B+
@VGA@
2

1
10K_0402_1%
2

1.8V_PWRGD <9,56>

VGA@
PRV79
1 2

5
VGA@ PRV65 1K_0402_1%

10U_0805_25V6K

10U_0805_25V6K
1 2 +0.95VS_PWRGD <57>

1
VGA@PCV103

VGA@PCV100
VGA@ PRV66 1K_0402_1% VGA@

MDV1525URH_PDFN33-8-5
PRV67 0_0603_5%

1
D VGA_UGATE2 1 2 4

2
PX_EN <34>

PQV21 VGA@
+5VS PQV23 2

0.1U_0402_25V6
VGA@
PCV102
2N7002KW 1N SOT323-3 G

1
@VGA@ S VGA@

3
+5VS PRV68

3
2
1
10K_0402_1%

VGA@ VGA_PHASE2 VGA@

2
PRV27 PLV3
2.2_0603_1% 0.36UH_PDME064T-R36MS_24A_20%
VGA_BOOT21 2 1
VGA_BOOT2-1 2 1 4
+VGA_CORE
VGA@ PCV26 2 3

4.7_1206_5%
5

@VGA@

PRV70
0.22U_0603_25V7K

1
VGA@ PQV22
PRV69

MDU1511RH_POWERDFN56-8-5
3.4K_0402_1%
VGA@ 1 2 1 2
3 PRV73 0_0603_5% VGA@ 3
APU_core
2

VGA@ VGA@ VGA_LGATE2 1 2 4 VGA@ PCV106

1 2
PRV71 PRV72 TDC 31A(1H1L) *2phase VGA_SNB_APU2 .1U_0402_16V7K

1
124K_0402_1% VGA@

680P_0603_50V7K
124K_0402_1%
Vset1=0.11V Peak Current 46.5A PRV74

@VGA@
10K_0402_1%
1

3
2
1

2
FSW=300kHz

PCV107
VGA_SET1 VGA_SET2 Vset2=0.018V
DCR 1.4mohm +/-5%

2
2

VGA@
PRV75 PRV76
2.8K_0402_1% 470_0402_1%
H/S Rds(on) :11A/15mohm(FDMS7698) ,36A/3.3mohm(MDU1511RH)

VGA_ISEN1N-2
VGA@
VGA_ISEN2P
1

PRV77 VGA@
1.3K_0402_1%
1
VGA_ISEN2N 2

@VGA@

0.1U_0402_25V6
1
PCV108
2
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2013/03/19 Deciphered Date 2013/03/19 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
RT8880AGQW
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-B181P 0.5
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 25, 2014 Sheet 54 of 62

A B C D E
5 4 3 2 1

WWW.AliSaler.Com
+VGA_CORE

1 1 1
+ DIS@ + DIS@ + DIS@
PCV51 PCV52 PCV53
330U_X_2VM_R6M 330U_X_2VM_R6M 330U_X_2VM_R6M
2 2 2
D D

+VGA_CORE
1

1
DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@
PCV54 PCV55 PCV56 PCV57 PCV58 PCV59 PCV60 PCV61
2.2U_0402_6.3V6M 2.2U_0402_6.3V6M 2.2U_0402_6.3V6M 2.2U_0402_6.3V6M 2.2U_0402_6.3V6M 2.2U_0402_6.3V6M 2.2U_0402_6.3V6M 2.2U_0402_6.3V6M
2

2
+VGA_CORE
1

1
DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@
C PCV62 PCV63 PCV64 PCV65 PCV66 PCV67 PCV68 PCV69 C
2.2U_0402_6.3V6M 2.2U_0402_6.3V6M 2.2U_0402_6.3V6M 2.2U_0402_6.3V6M 2.2U_0402_6.3V6M 2.2U_0402_6.3V6M 2.2U_0402_6.3V6M 2.2U_0402_6.3V6M
2

2
+VGA_CORE
1

1
DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@
PCV70 PCV71 PCV72 PCV73 PCV74 PCV75 PCV76
10U_0603_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M
2

B +VGA_CORE B
1

1
DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@
PCV77 PCV78 PCV79 PCV80 PCV81 PCV82 PCV83 PCV84 PCV85
1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K 22U_0603_6.3V6M 22U_0603_6.3V6M
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/04/03 Deciphered Date 2016/09/30 Title
VGA CHIP DECOUPLING
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-B181P 0.5
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 25, 2014 Sheet 55 of 62
5 4 3 2 1
5 4 3 2 1

WWW.AliSaler.Com
換jump DIS@
PU1801
SY8003DFC_DFN8_2X2
DISEMI@ DIS@ +1.8VGSP @ +1.8VS_VGA
PL1801 4 5 PL1802 PJP1801
HCB1608KF-121T30_0603 PGND NC 2.2UH +-20% MMD-04BZ-2R2M-X2 3A JUMP_43X79
+3VS 1 2 B+_1.8V 3 6 LX_1.8V 1 2 1 2
IN LX 1 2
D <9,54> 1.8V_PWRGD 2 7 EN_1.8V D
PG EN

1
@DISEMI@ DIS@ DIS@

1
PC1801 PC1802 PC1803 FB_1.8V 1 8 @DISEMI@ DIS@ DIS@
FB SGND

1
2200P_0402_50V7K 22U_0603_6.3V6M 22U_0603_6.3V6M 9 PR1803 DIS@ PC1805 PC1806 331mA
2

2
PGND 4.7_1206_5% PC1804 PR9511 22U_0603_6.3V6M 22U_0603_6.3V6M

2
22P_0402_50V8J 0_0402_5% OCP:3A

2
DIS@
FB_1.8V 1 2
DIS@ PR1801

1SNB_1.8V
20K_0402_1%

1
10_0402_1%PR9509 @DIS@
DIS@
DIS@ PR1802 1 2 +1.8VS_VGA <34,35,36,54>
PR1804 @DISEMI@ 10K_0402_1%
<35,57> 0.95V_1.8V_VGA_EN 0_0402_5% PC1807

2
1 2 680P_0402_50V7K

2
1
1
@DIS@ DIS@
PC1808 PR1805
0.1U_0402_16V7K 1M_0402_5%

2
C C

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2013/09/09 Deciphered Date 2016/09/30 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+1.8VS_VGA
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B 0.5
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA‐B181P
Date: Sheet 56 of 62
5 4 3 2 1
5 4 3 2 1

WWW.AliSaler.Com

換jump DIS@
PU9501
SY8003DFC_DFN8_2X2
D DISEMI@ DIS@ +0.95VGSP @ +0.95VS_VGA D
PL9501 4 5 PL9502 PJP9501
HCB1608KF-121T30_0603 PGND NC 2.2UH +-20% MMD-04BZ-2R2M-X2 3A JUMP_43X79
+3VS 1 2 B+_0.95V 3 6 LX_0.95V 1 2 1 2
IN LX 1 2
<54> +0.95VS_PWRGD 2 7 EN_0.95V
PG EN
1

1
@DISEMI@ DIS@ DIS@

1
PC9501 PC9502 PC9503 FB_0.95V 1 8 @DISEMI@ DIS@ DIS@ 1932mA
FB SGND

1
2200P_0402_50V7K 22U_0603_6.3V6M 22U_0603_6.3V6M 9 PR9503 PC9504 PR9508 DIS@ DIS@
2

2
PGND 4.7_1206_5% 22P_0402_50V8J 0_0402_5% PC9505 PC9506

2
22U_0603_6.3V6M 22U_0603_6.3V6M

2
OCP:3A

2
FB_0.95V 1 2

1SNB_0.95V
PR9501 DIS@
36.5K_0402_1%

1
DIS@ 10_0402_1%PR9506 @DIS@
DIS@ @DISEMI@ PR9502
<35,56> 0.95V_1.8V_VGA_EN PR9504 PC9507 62K_0402_1% 1 2 +0.95VS_VGA <33,35,36>
0_0402_5% 680P_0402_50V7K

2
1 2

1
1
@DIS@ DIS@
PC9508 PR9505
C C
0.1U_0402_16V7K 1M_0402_5%
2

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2013/09/09 Deciphered Date 2016/09/30 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+0.95VS_VGA
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B 0.5
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA‐B181P
Date: Sheet 57 of 62
5 4 3 2 1
5 4 3 2 1

WWW.AliSaler.Com

D D

AC
Adapter CPU DC/DC
P.44 RT8243AZQW TPS51622ARSMR 50~51
INPUTS OUTPUTS
B+ VCC_VORE

+3VLP +3VDS/+5VDS DC/DC +3VS/+5VS


SYSTEM DC/DC
EN (+5VS/+3VS) RT8243AZQW 47
INPUTS OUTPUTS
B+ AOZ1331DI B+ 3VDS/5VDS
DC Vin SYSTEM DC/DC
Battery RT8207MZQW 48
P.45 DC/DC DC/DC INPUTS OUTPUTS
+3V_PCH
Charger (+5VDS/+3VDS) (+3V_PCH) B+
1.35V_VDDQ
0.675VS
BQ24736RGRR
AO3413L SYSTEM DC/DC
SY8206DQNC 49
P.46
INPUTS OUTPUTS
B+ 1.05VS
PGOOD P.47 SYSTEM DC/DC
3V_PG SY8003DFC 52
INPUTS OUTPUTS
+1.35V_VDDQ B+ 1.5VS

+0.675VS SYSTEM DC/DC


C Vin DDR RT8880BGQW 54~55 C

SLP_S4# RT8027MZQW DDR_PGD INPUTS OUTPUTS


EN B+ +VGA_CORE
SLP_S3# P.48
SYSTEM DC/DC
+1.05VS SY8003DFC 56
Vin SY8206DQNC INPUTS OUTPUTS
SLP_S3# +1.05V_PGD B+ +1.8VS_VGA
EN
P.49
SYSTEM DC/DC
+1.5VS SY8003DFC 57
+3VS INPUTS OUTPUTS
Vin SY8003DFC B+ +0.95VS_VGA
SLP_S3#
EN
P.52 PGD_1.5V

+VCC_CORE
Vin TPS51622ARSM
VR12.5_VR_ON
VR_ON
DC/DC VGATE
(CPU_CORE)
P.50,51
B B

+VGA_CORE
Vin RT8880BGQW
DC/DC VDDC_PWRGD
EN (VGA_CORE)
P.54,55

+1.8VS_VGA
+3VS
Vin SY8003DFC
DC/DC
EN (VGA_RAM)
SLP_S3#
P.56

+0.95VS_VGA
+3VS
Vin SY8003DFC
DC/DC
A EN (VGA_RAM) A
SLP_S3#
P.57

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2012/04/03 2014/12/31 Title
Deciphered Date
Power Block Diagram
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-B181P 0.5
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 25, 2014 Sheet 58 of 62
5 4 3 2 1
5 4 3 2 1

WWW.AliSaler.Com
11/07
Power ON Sequence

D D

C C

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2013/02/26 Deciphered Date 2015/07/08 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power ON Sequence
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C 0.5
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B181P
Date: Tuesday, March 25, 2014 Sheet 59 of 62
5 4 3 2 1
5 4 3 2 1

WWW.AliSaler.Com
Version change list (P.I.R. List)
Fixed
Item Date Reason for change Modify List Phase
Issue
Delete
1 1.PQ307 1.customer request DB0
D 2.charger air line power circuit 2.customer request D
3.customer common part
3.change AON7506 to SI7716(PQ106)
4.compal change
DB0
4.change NDS0610 to LBSS84L
5.change AON7506 to SI7716 5.customer common part
20131030 6.vender reveiw DB0
6.change 47U 6.3V to 22U 6.3V (PCH8,PCH9)
7.PR9512 mount
DB0

1.10U_0805_25V==>2200p_0402_50V not mount(PC160) 1.EMI feedback


2 20131031 2.PC107,PR111,PC121,PC305,PR314 2.EMI feedback DB0
PC313,PC308,PR315,PC312,PCH4,PCZ3,PRZ13,PCZ13 3.power vender feedback
PCZ20,PCZ26,PCW1,PCV4,PRV70,PCV107 4.power change fb sense DB0
3.change 147K_0402_1% to 237K_0402_1% (PRV34) 5.for compal module design
change 560P_0402_50V7K to 470P_0402_50V7 (PCV88) 6.current limit design DB0
change 10.7K_0402_1% to 22.6K_0402_1%(PRV47)
DB1
C C

change 9.76K_0402_1% to 5.6K_0402_1%(PRV51) DB1


change 15K_0402_1% to 19.1K_0402_1%(PRV55)
change 910K_0402_5% to 20.5K_0402_1%(PRV75) DB1
change 910k_0402_1% to 910_0402_1%(PRV53) DB1
change 3.48K_0402_1% to 3.4K_0402_1%(PRV69)
change 910k_0402_1% to 910_0402_1%(PRV77) DB1
4.remove PR9510,PR9512,PR9514,PR9513 DB1
5.remove PC318,PRH10,PRW10,PCW13
6. PRH8,PRW8 not mount SI1
7.22u/0805 6.3V to 22u/0603 6.3V PC1504,PC1501 SI1
PC1505,PC1802,PC1803,PC1805,PC1806,PC9502,PC9503,
PC9505,PC9506,PCH9,PCH10,PCH11,PCH8
B
SI1 B
8.0.22U_0402_6.3V6K to 0.22U_0603_50V7K (PC128)

3 20131101 1.remove PRW11 1.HW request

4 20131112 1.not mount PRW7 2.AMD request


2.change 0_0402_1% to 0_0402_5%(PR1502,PR1804,
PR9504,PR9508,PR9511,PR9515)

5 20131202 1.not mount PRZ36,PRV32 and PCV86 1.PWR request


2.PC128 change 0.22U_0603_25V to 0.22U_0402_6.3V6K 2.PWR request SI1
3.add PD16,PRV43 SI1
3. customer request
4.add PRV45,PRV48,PCV99 and PRV50
4.richtek request
SI2
A A
SI2
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date Title
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PIR List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.5
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B181P
Date: Tuesday, March 25, 2014 Sheet 60 of 62
5 4 3 2 1
5 4 3 2 1

WWW.AliSaler.Com
Version change list (P.I.R. List)
Fixed
Item Date Reason for change Modify List Phase
Issue
add
6 20131210 PRV78 1K_0402_1% RITCHTEK issue request DB0
D PRV62 5.76K_0402_1% D

PRV64 10K_0402_1% DB0


PRV80 1K_0402_1%
PRV79 10K_0402_1% DB0
PRV52 137K_0402_1%

PRM2 Change 4.7_1206_5% to 0_1206_5% DB0


20131221 PCM7 Change 680P_0603_50V7K to 1000P_0603_50V7K EMI request
PR314 not mount==>mount
PC313 not mount==>mount DB0
PR315 not mount==>mount
PC312 not mount==>mount DB0
PCZ13 not mount==>mount
PRZ13 not mount==>mount
PCZ20 not mount==>mount(28W) DB0
PRZ26 not mount==>mount(28W)
DB1
C C

DB1
PRV31 Change 10_0402_1% to 1_0402_1% RITCHTEK issue request
20131226 PRV34 Change 127K_0402_1% to 84.5K_0402_1% DB1
PRV47 Change 22.6K_0402_1% to 7.32K_0402_1%
PRV51 Change 5.6K_0402_1% to 12.4K_0402_1% DB1
PRV55 Change 19.1K_0402_1% to 14K_0402_1%
PRV75 Change 20.5K_0402_1% to 2.8K_0402_1% DB1
PRV77 Change 910_0402_1% to 1.3K_0402_1%
PRV53 Change 910_0402_1% to 1.3K_0402_1%
PC128 Change 0.22U_0603_6.3V to 0.22U_0402_6.3V DB1
SI1
PRM2 Change 0_1206_5% to 4.7_1206_5%
20140102 PCM7 Change 1000P_0603_50V7K to 680P_0603_50V7K EMI request SI1
PUV1 change RT8880BGQW to RT8880CGQW RITCHTEK request

B PR14,PQ2 and PR13 are not mount. SI1 B


20140103 PR11 Change 330_0402_1% to 680_0402_1% Customer request

PRV80 mount==>not mount RITCHTEK issue request


20140106 PRV79 not mount==>mount

20140213 add PC8,PC9 and PC10 EMC request


mount PR111,PC121,PC107 and PC129 EMC request
PC107 2200P_0402_50V7K==>0.022_0402 25V
PC129 0.1U_0402_50V7K==>0.022_0402_25V
20140214 SI1
add PC161 2200P_0402_50V7K not mount EMC request
SI1

SI2
A A
SI2
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date Title
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PIR List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.5
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B181P
Date: Tuesday, March 25, 2014 Sheet 61 of 62
5 4 3 2 1
5 4 3 2 1

ZPL40/50/70 from DB to DB-R LA-B181P REV:0.1 -> 0.2 Modify <2013.11.28.~ 2013.12.03>

WWW.AliSaler.Com
Rev. Item Date Impact Page Change Cause Modify Description
0.2 1 11/28 CKT, LAYOUT 6 -Design issue -Change RC222 pin 1 connection from +3VS to +5VS
0.2 2 11/28 CKT, LAYOUT 7 -Follow CHICLET -Move TPM LPC CLK from port 0 to port 1
0.2 3 11/28 CKT 8 -DGPU_PWR_EN voltage level uncorrect issue -Uninstall RC125
0.2 4 11/28 CKT, LAYOUT 9 -DGPU power on sequence -Change RC121 to 100K and add CC127 to timing delay.
0.2 5 11/28 CKT, LAYOUT 18 -Footprint uncorrect issue -Modify UT6 footprint to SC70-5
0.2 6 11/28 CKT, LAYOUT 21 -No used. -Remove CLK_PCI_DEBUG from JMINI1 pin 19
0.2 7 11/28 CKT 23 -Q35 can't turn on issue -Uninstall RL26
0.2 8 11/28 CKT 30 -Follow HP BIOS code request -Uninstall R124
0.2 9 11/28 CKT, LAYOUT 32 -Aviod leakage issue. -Swap Q88 pin 1 and pin 3
0.2 10 11/28 CKT, LAYOUT 32 -Footprint uncorrect issue -Modify C187 footprint to 0402 package
0.2 11 11/28 CKT, LAYOUT 33 -Design issue -Swap GPU PEG RX bus P/N signal and CV1~CV8 change to 0.22u
0.2 12 11/29 CKT, LAYOUT 28 -Current limit -Add R660
0.2 13 11/29 CKT, LAYOUT 30 -Vendor request -U13 pin 6 add external 4.7K PU to +3VS_TPM
D 0.2 14 11/29 CKT 32 -Follow CHICLET -Change R255, R257, and R493 to 10Kohm D

-Delete QC12 and add buffer U20 and U21.


0.2 15 12/02 CKT, LAYOUT 6 -Follow CHICLET QC8.3 net name from HDA_SDOUT_AUDIO change to HDA_SDOUT
0.2 16 12/02 CKT, LAYOUT 32 -Follow CHICLET add R101, R102, R104, R105, R106
1.swap QL2 pin 1 and pin 3
0.2 17 12/02 CKT, LAYOUT 23 -leakage issue and FAR suggest 2.Install RL40
3.Reserve 2 resistor (RL48, RL49) connection QL2.2 to +3VS and +LAN_VDD_3V3.
0.2 18 12/02 CKT, LAYOUT 34 -Follow 2013 RRR -Add D14
0.2 19 12/02 CKT 35 -DGPU power on sequence -Uninstall R5076, R5074
0.2 20 12/03 CKT, LAYOUT 40 -Follow CHICLET -change +1.05VS_MODPHY switch circuit

ZPL40/50/70 from DB-R to SI LA-B181P REV:0.2 -> 0.3 Modify <2013.12.04~ 2013.12.17>
0.3 1 12/04 CKT, LAYOUT 29 -Follow 2013 RRR -update FAN control circuit delete Q4108, R5080 and add U2, C31
0.3 2 12/05 CKT 35 -DGPU power on sequence -C4816 from 0.01u change to 0.022u
0.3 3 12/05 CKT 9 -DGPU power on sequence -Change RC121 to 0ohm and uninstall CC127 (BIOS code control timing)
0.3 4 12/05 CKT 10, 33 -For PCIe Gen2 -change CC89, CC90, CC91, CC92, CC93, CC94, CC95, CC96, CV1, CV2, CV3, CV4, CV5, CV6, CV7, CV8 from 0.22u to 0.1u
0.3 5 12/06 CKT 12 -Follow CHICLET -Change RC174 from 5.11ohm to 0ohm
0.3 6 12/06 CKT 11 -Follow INTEL schematic -Change RC156 from 110ohm to 130ohm install
0.3 7 12/06 CKT, LAYOUT 29 -Platform ID identify -add R82, R86
0.3 8 12/06 CKT, LAYOUT 32 -reserve R136, R137 co-lay with U20, U21
0.3 9 12/06 CKT, LAYOUT 40 -reserve R135 co-lay with Q185
0.3 10 12/09 CKT, LAYOUT 43 -No leakage issue -remove Q57
0.3 11 12/09 CKT 26 -Follow CHICLET -RA36 from 22ohm change to 33ohm
0.3 12 12/09 CKT, LAYOUT 17 -Follow INTEL schematic -Install CD52, CD53, CD54, RD11, RD12, RD19 and re-placement RD7, RD8, RD15
0.3 13 12/09 CKT, LAYOUT 11 -Follow INTEL schematic -Re-placement RC154
0.3 14 12/09 CKT, LAYOUT 12 -Follow INTEL schematic -Add RC183, CC47, RC189, CC75
0.3 15 12/10 CKT, LAYOUT 10 -For WWAN , Touch share USB port -Add R138, R139
0.3 16 12/10 CKT, LAYOUT 4 -Follow CHICLET -Add C32
0.3 17 12/11 CKT, LAYOUT 8 -Follow INTEL schematic -reserve RC330
0.3 18 12/11 CKT, LAYOUT 21 -solve SIM card cann't detect issue -delete R5079 , Q4107 and add C2
0.3 19 12/13 CKT, LAYOUT 9 -Follow Runt -R103 change to test point T184
0.3 20 12/13 CKT 8 -solve DGPU power issue -Install RC125
C C
0.3 21 12/13 CKT, LAYOUT 21 -Follow Runt -Q90 , Q4113 from two single MOS change to daul MOS (Q90)
0.3 22 12/13 CKT, LAYOUT 22 -ODD power issue -Add Q63
0.3 23 12/13 CKT, LAYOUT 23 -LAN power issue -delete JHW1 , RL26
0.3 24 12/13 CKT, LAYOUT 21 -no need -delete R205 , C292
0.3 25 12/13 CKT 25 -For V drop test -C1572 from 100u change to 150u
0.3 26 12/13 CKT, LAYOUT 9 -Hp request -ODD_DA# form GPIO14 change to GPIO3
0.3 27 12/13 CKT, LAYOUT 21 -For GPIO initial status -add R91
0.3 28 12/14 CKT, LAYOUT 12 -solve power ripple -add CC77 , CC78 , CC79
0.3 29 12/16 CKT, LAYOUT 9 -reserve for MPHY sequence -add RC377

ZPL40/50/70 from DB-R to SI LA-B181P REV:0.3 -> 0.4 Modify <2013.12.18~ 2013.12.25>
0.4 1 12/20 CKT 9 -Follow HP request -Install RC272, RC273
0.4 2 12/20 CKT, LAYOUT 15 -Follow Intel PDG -Remove RD26, Install RD21
0.4 3 12/20 CKT, LAYOUT 16 -Follow Intel PDG -Unnstall CD52, CD53, CD54, RD11, RD12, RD19 and re-placement RD7, RD8, RD15
0.4 4 12/20 CKT, LAYOUT 19 -Follow Vendor request -Reserve RG5
0.4 5 12/20 CKT 19 -Follow HP request -Change R82, R86 to 0 ohm
0.4 6 12/20 CKT 20 -Follow Intel PDG -Change RP3 and RP4 to 470 ohm
0.4 7 12/20 CKT 21 -Compal Request -Install R91
0.4 8 12/20 CKT, LAYOUT 22 -Customer modify GPIO table. -Remove Q84, R954. Change JODD1 pin 11 netname to ODD_DA#
0.4 9 12/20 CKT 23 -Prepare leakage issue when S3, S5 -Uninstall RL40, QL2, RL49, RL48 install RL34
0.4 10 12/20 CKT 24 -Vendor Request -Reserve RA40, U4101 pin 37 add RT57 10K PU to +5VS
0.4 11 12/20 CKT 31 -Vendor Request -Remove R1363, R1365, R1367, C421, C423, C414, L31, L32, L34, R1364, R1366, and R1368. Modify CRT pi filter
0.4 12 12/20 CKT, LAYOUT 40 -Follow Compal common design -Modify MPHY Power circuit
-Install C80, C556, C81, C558
0.4 13 12/23 CKT, LAYOUT 30 -Follow RF team request -Reserve C90, C564, C91, C565, C92, C566, C93, C567, C95, C569, C110, C578, C111, C579, C108, C576, C82, C559, C83, C560, C84, C561, C86, C562, C89, C563, C94, C568, C96, C571,
C112, C580, C109, C577, C106, C574, C97, C572, C105, C573, C130, C581, C131, C582, C132, C583, C133, C584, C134, C585, C135, C586, C136, C587, C137, C588, C138, C589
-Install C113, C127
0.4 14 12/24 CKT, LAYOUT -Follow ESD team request -Reserve C114, C115, C116, C121, C123, C124, C128, C129

ZPL40/50/70 from SI to PV-1 LA-B181P REV:0.3 -> 0.4 Modify <2014.02.05~2014.>


0.5 1 02/05 CKT 21 -Double pull hugh -RN3 change to @
0.5 2 02/05 CKT 18, 19 -For LVDS SKU -R163, RG3 change to LVDS@
B B
0.5 3 02/05 CKT 19 -For eDP SKU -R172 change to eDP@
0.5 4 02/05 CKT 19 -For Lid Switch issue -R166, R175 change to 3.3K
0.5 5 02/05 CKT, LAYOUT 22 -For ODD issue -add R448, reserve C151
-1. QA2, QA3 combine to dual mos QA2A, QA2B
2. Q91, Q182 combine to dual mos Q91A, Q91B
0.5 6 02/05 CKT, LAYOUT 3. Q86, Q87 combine to dual mos Q86A, Q86B
4. Q63 change to Q63A, Q63B
5. Q4112, Q4114 combine to dual mos Q4112A, Q4112B
0.5 7 02/10 CKT, LAYOUT 35 -For GPU Power Sequence -add D15 and move R5075, C4819
0.5 8 02/10 CKT, LAYOUT 28 -Follow ESD team request -add C594, C595, C596
0.5 9 02/10 LAYOUT 31 -Move U4101 circuit close to JCRT
0.5 10 02/11 CKT, LAYOUT 40 -SLG59M1470VTR is single source issue -modify U44 circuit
0.5 11 02/12 CKT 33 -Improve VGA_PWRGD signal quality -R5094 from 8.25K change to 0ohm
0.5 12 02/13 CKT, LAYOUT 11, 19 -Follow RF team request -add C139, C140, C421
-1. FPR_OFF from GPIO11 change to GPIO65
2. change JAUDIO1.16 from +3V_PCH to +3VS
3. disconnect EC pin125 and CPU pinAJ5
rename EC pin125 "PCH_PCIE_WAKE#" to "EC_GPIO25" and add R249 pull up to +3VDS
4. RN13 un-install
0.5 13 02/14 CKT, LAYOUT -Follow HP request 5. connector EC pin103 to JMINI1 pin1 (WLAN_WAKE#), JMINI2 pin15 change to NC
6. connector EC pin105 to CPU pinAJ5 (PCH_PCIE_WAKE#)
7. change RN3 pull up power rail from +3VS_WLAN to +3VDS and install RN3
8. add JP4102 between +3VDS and +3V_WWAN

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2011/11/5 Deciphered Date 2010/12/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HW_PIR1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.5
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B181P
Date: Tuesday, March 25, 2014 Sheet 62 of 62
5 4 3 2 1

You might also like