Sequential Circuits

Latches and Flip-Flops

Dr. Sonali Vyas

Introduction
 Output depends on current as well as
past inputs
 Depends on the history
 Have “memory” property
 Sequential circuit consists of
» Combinational circuit
» Feedback circuit
 Past input is encoded into a set of state
variables
» Uses feedback (to feed the state
variables)
– Simple feedback
– Uses flip flops
 Types of Sequential Circuits
In Asynchronous sequential circuits the output of the logic circuit can
change state at any time, as soon as any input changes its state
whereas in the case of synchronous systems a signal namely clock
signal is used to determine/control the exact time at which any output
can change its state. These are also called as clocked sequential
circuits.
 Flip Flop
 A flip flop is a binary storage device. It
can store binary bit either 0 or 1. It has two sta
ble states HIGH and LOW i.e. 1 and 0. It has t
he
property to remain in one state indefinitely until
it is directed by an input signal to switch over t
o the other state.
 It is also called bistable multivibrator.
 The basic formation of flip flop is to store data.
Flip Flop Types:

 SR ("set-reset")
 D ("data" or "delay")
 T ("toggle")
 JK

Flip-flops can be either simple (transparent or

asynchronous) or clocked (synchronous); the
transparent ones are commonly called latches.
The word latch is mainly used for storage
elements, while clocked devices are described
as flip-flops
SR Flip-flop

 The SR (Set-Reset) flip-flop is one of the

simplest sequential circuits and consists of
two gates connected .
 The output of each gate is connected to
one of the inputs of the other gate.
 The circuit has two active low inputs
marked S’ and R’, as well as two outputs,
Q and Q’.
 RS Latch
 RS latch have two inputs, S and R. S is called
set and R is called reset.
 The S input is used to produce HIGH on Q ( i.e.
store binary 1 in flip-flop).
 The R input is used to produce LOW on Q (i.e.
store binary 0 in flip-flop). Q' is Q
complementary output, so it always holds the
opposite value of Q.
 The output of the S-R latch depends on current
as well as previous inputs or state, and its state
(value stored) can change as soon as its inputs
change.
•When S = 0 and R = 0: If we assume Q = 1 and Q' = 0 as initial condition, then
output Q after input is applied would be Q = (R + Q')' = 1 and Q' = (S + Q)' = 0.
Assuming Q = 0 and Q' = 1 as initial condition, then output Q after the input applied
would be Q = (R + Q')' = 0 and Q' = (S + Q)' = 1. So it is clear that when both S and
R inputs are LOW, the output is retained as before the application of inputs. (i.e.
there is no state change).
•When S = 1 and R = 0: If we assume Q = 1 and Q' = 0 as initial condition, then
output Q after input is applied would be Q = (R + Q')' = 1 and Q' = (S + Q)' = 0.
Assuming Q = 0 and Q' = 1 as initial condition, then output Q after the input applied
would be Q = (R + Q')' = 1 and Q' = (S + Q)' = 0. So in simple words when S is
HIGH and R is LOW, output Q is HIGH.
•When S = 0 and R = 1: If we assume Q = 1 and Q' = 0 as initial condition, then
output Q after input is applied would be Q = (R + Q')' = 0 and Q' = (S + Q)' = 1.
Assuming Q = 0 and Q' = 1 as initial condition, then output Q after the input applied
would be Q = (R + Q')' = 0 and Q' = (S + Q)' = 1. So in simple words when S is
LOW and R is HIGH, output Q is LOW.
•When S = 1 and R =1 : No matter what state Q and Q' are in, application of 1 at
input of NOR gate always results in 0 at output of NOR gate, which results in both Q
and Q' set to LOW (i.e. Q = Q'). LOW in both the outputs basically is wrong, so this
case is invalid
Clocked RS Flip Flop
 The RS latch flip flop required the direct input but no clock. It is
very use full to add clock to control precisely the time at which the
flip flop changes the state of its output.
 In the clocked RS flip flop the appropriate levels applied to their
inputs are blocked till the receipt of a pulse from an other source
called clock. The flip flop changes state only when clock pulse is
applied depending upon the inputs.
 This circuit is formed by adding two AND gates at inputs to the RS
flip flop. In addition to control inputs Set (S) and Reset (R), there is
a clock input (C) also.
The first five lines in the truth table give the static input and output
states.
The last four lines show the state of the outputs after a complete
clock pulse p.
JK Flip Flop
 One of the most useful and versatile flip flop is
the JK flip flop the unique features of a JK flip
flop are:
◦ If the J and K input are both at 1 and the clock pulse is
applied, then the output will change state, regardless
of its previous condition.
◦ If both J and K inputs are at 0 and the clock pulse is
applied there will be no change in the output.
◦ There is no indeterminate condition, in the operation
of JK flip flop i.e. it has no ambiguous state.
 When J = 0 and K = 0,
These J and K inputs disable the NAND gates, therefore
clock pulse have no effect on the flip flop. In other
words, Q returns it last value.
 When J = 0 and K = 1,
The upper NAND gate is disabled the lower NAND gate
is enabled if Q is 1 therefore, flip flop will be reset (Q =
0 , Q’ =1)if not already in that state.
 When J = 1 and K = 0
The lower NAND gate is disabled and the upper NAND
gate is enabled if is at 1, As a result we will be able to
set the flip flop ( Q = 1, Q’ = 0) if not already set.
 When J and K are both high, the clock pulses cause
the JK flip flop to toggle.
Master Slave JK Flip Flop
 A master slave flip flop contains two clocked
flip flops. The first is called master and the
second slave.
 When the clock is high the master is active.
The output of the master is set or reset
according to the state of the input.
 When clock becomes low the output of the
slave flip flop changes because it become
active during low clock period.
 The final output of master slave flip flop is
the output of the slave flip flop. So the
output of master slave flip flop is available at
the end of a clock pulse.
Delay Flip Flop or D-Flip Flop
 The D type flip-flop has one data input 'D' and a clock
input. The circuit edge triggers on the clock input. The
flip-flop also has two outputs Q and Q' (where Q' is the
reverse of Q).
 Such type of flip flop is a modification of clocked RS
flip flop gates from a basic Latch flip flop and NOR
gates modify it in to a clock RS flip flop.
 The D input goes directly to S input and its complement
through NOT gate, is applied to the R input.
 When the clock is low, both AND gates
are disabled, therefore D can change
values without affecting the value of Q.
 When the clock is high, both AND gates
are enabled. In this case, Q is forced equal
to D
 When the clock again goes low, Q retains
or stores the last value of D
Toggle Flip Flop or T-Flip Flop
 The operation of the T type flip-flop is as
follows:
 A '0' input to 'T' will make the next state
the same as the present state (i.e. T = 0
present state = 0 therefore next state = 0).
 However a '1' input to 'T' will change the
next state to the inverse of the present
state (i.e. T = 1 present state = 0 therefore
next state = 1).
Counters
 A counter is a register that goes through a
predetermined sequence of states upon the application
of clock pulses
Asynchronous counters
Synchronous counters
 Asynchronous Counters (or Ripple counters)
 the clock signal (CLK) is only used to clock the first FF.
Each FF (except the first FF) is clocked by the preceding
FF.
 Synchronous Counters
the clock signal (CLK) is applied to all FF, which means
that all FF shares the same clock signal
thus the output will change at the same time
Asynchronous Counters
 The Asynchronous Counter that counts 4 number
starts from 00 01 10 11 and back to 00 is called
MOD-4 Ripple (Asynchronous) Up-Counter.
 The external clock is connected to the clock input of
the first flip-flop (FF0) only. So, FF0 changes state at
the falling edge of each clock pulse, but FF1 changes
only when triggered by the falling edge of the Q
output of FF0.
 Because of the inherent propagation delay through a
flip-flop, the transition of the input clock pulse and a
transition of the Q output of FF0 can never occur at
exactly the same time.
 Therefore, the flip-flops cannot be triggered
simultaneously, producing an asynchronous operation.
The transitions of Q0, Q1 and CLK in the timing diagram below are shown as
simultaneous even though this is an asynchronous counter. Actually, there is
some small delay between the CLK, Q0 and Q1 transitions.

Usually, all the CLEAR inputs are connected together, so that a single pulse can
clear all the flip-flops before counting starts.

The clock pulse fed into FF0 is rippled through the other counters after
propagation delays, like a ripple on water, hence the name Ripple Counter.
 A counter with n flip-flops can have 2 to the power
n states. The number of states in a counter is known as
its mod (modulo) number. Thus a 2-bit counter is
a mod-4 counter.
 For a 4-bit counter, the range of the count is 0000 to
1111 (24-1). A counter may count up or count down or
count up and down depending on the input control. The
count sequence usually repeats itself.
 When counting up, the count sequence goes from 0000,
0001, 0010, ... 1110 , 1111 , 0000, 0001, ... etc.
 When counting down the count sequence goes in the
opposite manner: 1111, 1110, ... 0010, 0001, 0000, 1111,
1110, ... etc.
Synchronous counters
 A synchronous counter, is one whose output bits
change state simultaneously, with no ripple.
 The external clock signal is connected to the
clock input of every individual flip-flop within
the counter so that all of the flip-flops are clocked
together simultaneously (in parallel) at the same
time giving a fixed time relationship.
 The result of this synchronization is that all the
individual output bits changing state at exactly the
same time in response to the common clock signal
with no ripple effect.
 The external clock pulses are fed directly to each of the J-K flip-
flops in the counter chain and that both the J and K inputs are all
tied together in toggle mode.
 In flip-flop FFA(LSB) they are connected HIGH, logic “1”
allowing the flip-flop to toggle on every clock pulse. Then the
synchronous counter follows a predetermined sequence of states
in response to the common clock signal, advancing one state for
each pulse.
 The J and K inputs of flip-flop FFB are connected directly to the
output QA of flip-flop FFA, but the J and K inputs of flip-
flops FFC and FFD are driven from separate AND gates which are
also supplied with signals from the input and output of the
previous stage.
 These additional AND gates generate the required logic for the JK
inputs of the next stage.
 When all the counter stages are triggered in parallel at the same
time, the maximum operating frequency of this type of frequency
counter is much higher than that for a similar asynchronous
counter circuit.