VLSI LAB

SUBMITTED BY:
M.SALMAN SHAHID
REGISTRATION #:170401026

Submitted to: Mr. MEER HAMZA

EE-16
 Transient response of cmos NAND gate

and NOR gate

Objective

In this, our objective is to:

• Get familiar with the Cadence Virtuoso environment.

• Draw a schematic of a simple NAND gate and simulate it.
• Compare the schematic and extracted simulations.

Apparatus

Virtuoso cadence

In Lab Task

NAND gate

Procedure:

• Firstly, I constructed the circuit as per instructed by using PMOS and Nmos
• Then I placed some inputs and outputs nodes.
• Then I activated these nodes some of them were input and som eof them were outputs.
• I made the settimgs of inputs.
• I decided the time period, pulse width and time period of the input signals which are basically the
pulses
• Then I selcted the transiant analysis and made settings.
• Then, I selected the outputs to be plotted and observed the outout graph
Circuit Diagram

Settings
Output
Load Circuit

Output
10pf
Home Task

NOR GATE

Procedure:

• Firstly, I constructed the circuit by using PMOS and Nmos

• Then I placed some inputs and outputs nodes.
• Then I activated these nodes some of them were input and som eof them were outputs.
• I made the settimgs of inputs.
• I decided the time period, pulse width and time period of the input signals which are basically the
pulses
• I created symbol of Nor gate
• Then I selcted the transiant analysis and made settings.
• Then, I selected the outputs to be plotted and observed the outout graph

Circuit Diagram
Symbol:

Settings( CMOS NOR GATE)

Output

AVG Power
Rise Time
FALL Time
DELAY Time
With Load

100f F
Rise , Fall and Delay time

Average power

50F
Average Power
1P
Capacitance Delay Time Rise Time Fall Time Average Power

100f 2.3ns 3.1ns 579.4ps 66.03x10^-3W

10f 317.3ps 570.6ps 75.8ps 363.08 x 10^-3W

50f 1.5ns 2.7ns 335.3ps 254 x 10^-3 W

1p 2.1ns 3.1ns 4.2ns 95.09 x 10 ^-3

Invertor
Output

Delay, Rise and Fall Time

Average Power

Conclusion:

From the experiment, we concluded that

• Capacitive load has a great impact on the output of the gates.

• As the load increases. Output starts to become more irregular because capacitor does not charge
completely and next input comes and vice versa.