VLSI LAB 5

M.SALMAN SHAHID
170401026

Submiited to
 Properly sized Pmos and Nmos inverotr and Nand gate analysis

Objective:
 To understand the dc analysis of nand gate using proper sizing
 To understand the paralell working of invertors.
 To calculate delay time using calculator

Apparatus
 Cadence Vietuoso

Procdeure:
Fisrt I made the circuit diagram as per instructed.
Then, I did the proper sizing of pmos and nmos for getting proper results.

The following graphs were obtained

TASK 2

BOLEAN EXPRESSION
Task 3
In this task we have to make three invertors in parallel

Difference was this time pmos and nmos were properly sized

Circuit Diagram
Settings
Output

Delay
2
Output
Delay
Output
Delay

Conclusion:
From the experiment, we concluded that

 proper sizing effects the output performances

 Delay time changes with change in sizing
 The less the delay, the better it is.