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SUBMITTED BY:
M.SALMAN SHAHID
REGISTRATION #:170401026
Apparatus
Virtuoso cadence
In Lab Task
NAND gate
Procedure:
• Firstly, I constructed the circuit as per instructed by using PMOS and Nmos
• Then I placed some inputs and outputs nodes.
• Then I activated these nodes some of them were input and som eof them were outputs.
• I made the settimgs of inputs.
• I decided the time period, pulse width and time period of the input signals which are basically the
pulses
• Then I selcted the transiant analysis and made settings.
• Then, I selected the outputs to be plotted and observed the outout graph
Circuit Diagram
Settings
Output
Load Circuit
Output
10pf
Home Task
NOR GATE
Procedure:
Circuit Diagram
Symbol:
AVG Power
Rise Time
FALL Time
DELAY Time
With Load
100f F
Rise , Fall and Delay time
Average power
50F
Average Power
1P
Capacitance Delay Time Rise Time Fall Time Average Power
Invertor
Output
Conclusion: