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  • M.Salman Shahid: Vlsi Lab#07

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    Muhammad Salman Shahid
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    This document summarizes 7 tasks completed by a student to understand Verilog functionality and gate level and data flow modeling design. The tasks include creating a 2:1 multiplexer at the gate level and data flow, modeling a NOR gate, an inverter, an adder, and a 4:1 multiplexer at the gate level and data flow. Verilog code was written and test benches were created for each task and viewed in Modelsim to observe the results.

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    170401026_lab07.docx

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    This document summarizes 7 tasks completed by a student to understand Verilog functionality and gate level and data flow modeling design. The tasks include creating a 2:1 multiplexer at the gate level and data flow, modeling a NOR gate, an inverter, an adder, and a 4:1 multiplexer at the gate level and data flow. Verilog code was written and test benches were created for each task and viewed in Modelsim to observe the results.

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    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    13 views13 pages

    M.Salman Shahid: Vlsi Lab#07

    Uploaded by

    Muhammad Salman Shahid
    This document summarizes 7 tasks completed by a student to understand Verilog functionality and gate level and data flow modeling design. The tasks include creating a 2:1 multiplexer at the gate level and data flow, modeling a NOR gate, an inverter, an adder, and a 4:1 multiplexer at the gate level and data flow. Verilog code was written and test benches were created for each task and viewed in Modelsim to observe the results.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    of 13

    VLSI LAB#07

    M.SALMAN SHAHID
    170401026

    SUBMITTED TO:
    Objective:

     To understand the functionality of Verilog.


     To understand gate level and data flow modeeling design.

    Apparatus

     Modelsim

    Procedure

     I wrote verilog code and created test benches and then added it to wave to see the results

    TASK 1

    2:1 MUX

    GATE LEVEL and Data Flow


    NOR GATE
    TASK 3

    Invertor
    Test Bench

    Wave Diagram
    TASK 4
    TASK 5
    TASK 7

    Adder
    TASK 8

    4 to 1 mux

    Gate level and Data FLow


    Data flow

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