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I I i I 0 i D.mt+a.
i i i iir i i i
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Pi I I I I I
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F=::;"'-�' : :
(1)
. .
. ... . . - . _ . . . ,- - _ . . , - - - - - ,- -
--·-
, - -- ------, ----,--- ',--
· . .
. . (2)
-Vi ..... .t.-,;...-____....... . ... .
7r
where (31 and (32 are the conduction angles, /6 <
Figure 2: Firing signals and AC voltage with bipolar (31, (32 :s; 7r/2, and can be expressed as
modulation ( i=1,2 )
(3)
(4)
tank, as well as maintaining capacitor voltage at a desired
value. To achieve these goals, switched AC voltages where Mal and Ma2 are control signal magnitudes
must be controllable on both sides. An effective topology and 0 :s; Mal , Ma2 :s; 2/3. It can be seen that the AC
includes two voltage source converters (V SCs) based on voltages magnitude and phase are directly controlled by
insulated-gate bipolar transistors (IGBTs) as shown in using control signals (Mal and Ma2 ) and phase shifts
Figure L V SCs are able to control AC side voltages (0;1 and 0;2), respectively.
which do not exceed DC side voltages. This implies that By considering AC sine waves at the fundamental
lower voltage bridge does not see a high voltage stress frequency, the KCL and KVL result in:
[14].
We introduce three resonant frequencies for the LCL C. Phase shift between VIae and V2ae
converter
J
1 L1 + L2
frLCL = 27r (14)
L1L2C
1
frl = (15)
27rVLIC
1
fr2 = (16)
27rVL2C
where frLcL is the main LCL resonant frequency, and Figure 4: Phasor Diagram for LCL resonant tank
frl and fr2 are the local resonant frequencies.
Figure 4 shows the phasor digram for the LCL circuit
B. Zero reactive power condition under zero reactive power condition. The phase shift
between two AC voltages is:
We apply zero reactive power condition to the both
sides of the LCL circuit. This forces the circuit to 1 V1 q
a = tan - (23)
operate with minimum current magnitudes, this redicing V1 d
the switching losses [14]. Zero reactive power at terminal
By substituting R2 from (21), we derive the phase shift
2 results in zero q-component for its current (because of
expression.
V2 q = 0). Therefore, the terminal 2 side behaves as a
resistive load with effective resistance R2 given by
(24)
V2 d
R2 = _ (17) The above equation implies that the phase shift be
12d
tween VIae and V2ae is fixed for given constant L1, L2,
Using (17), we will rewrite equations (12) and (13) as C and w, and also forces the following condition
(25)
(18)
D. Power balance
(19)
We derive active power expressions for both side under
zero-reactive power circumstance:
The reactive power expression can be now derived by
using (18) and (19) ,
1, , IV12ae
PI = VI . h = -VIae · ha c = - (26)
2 2 R1
,
1, , IV22ae
P2 = V2 · 12 = -V2ae · 12ae = - (27)
2 2 R2
where Rl and R2 are the equivalent resistance seen by
R2 can be obtained by applying zero reactive condition each side, respectively. We will obtain Rl by applying
also at terminal 1 (Ql = 0): power balance condition ( PI = P2 ) and using equations
(1) and (2):
(21) (28)
(22)
E. Voltage step ratio
At given frequency w determined by switching pattern, The voltage step ratio is defined as:
and once L1, L2 and C are chosen, then effective V1acj (2 /31 -1)
sin
resistance at the LV side of the converter is constant. (29)
V2acj (2 /32 -1)
sin
Voltage V2ae changes in proportion to current 12ae like
for a DC load. After rearranging (19) and using (21)
k2
(30) 1 - w2 L1 C
0.1
I 1 - w2
0.00025
L2C I w2 L2C
0.99975
0.5 0.00125 0.99875
Using (30) in (29) the voltage ratio is expressed as
0.8 0.002 0.998
k1 (2sin,8 2 _ 1) 2
(31)
k2 (2sin,81 - 1) 2 If we use some realistic values for implementa-
This voltage step ratio will be calculated for maximum tion such as k2 0.lorO.05(min) and kl
power transferring which is in full conduction (,81 = 0.9or 0.95(max) then we achieve not very high voltage
,8 2 =90°). step ratio 3 and 4.2, respectively. The step ratio can be
improved by another factor of 2 by limiting the range
on ,81, i.e. that at maximum load 2sin,82 - 1 = 1 and
(32)
2sin,81 - 1 = 0.5. Using these values in equation (31)
gives 6 and 8 for the voltage ratio, which is still not very
Above equation indicates that both k1 and k2 are of
high.
the same sign and Ik11 > Ik21 (V2 < VI). From (21), k3
2) Post-resonant case: Both kl and k2 are negative,
must be positive, which means switching frequency must
and the switching frequency w is greater than both local
be less than the LCL resonance frequency. 2
resonance frequencies (i.e. w L1C > 1 and w L1C >
2
According to the above conditions, we introduce two
1). Therefore, it can be simply realized from (18) and
operation cases for converter: a) pre-resonant case and
(19) that the real parts of both VIae and [la c (V1d and
b) post-resonant case. The aim is to find the realistic
maximum voltage ratio for each case.
hd) are negative. Figure 6 shows the phasor diagram for
2 different relationship between VIae and V2ae.
1) P re-resonant case: Both (1 - w L1C) and (1 -
2
w L2C) are greater than zero, and the switching fre
quency w is less than both local resonance frequencies
2 2
(i.e. 0 < w Ll C < 1 and 0 < w Ll C < 1). Therefore,
both real and imaginary parts of VIae and i1ae are
positive. Figure 5 shows the phasor diagram for different
relationship between V Iae and V2ae.
Vl'�" �'V"i",' I' Figure 6: Phasor diagram for LCL resonant tank in post
iWL,I, , "
resonant case
U V2.� Vl••
Jw�Th<
( 12000 ) 2 =400
-- (33)
for k1 is -20, which gives a maximum voltage ratio
of 20 (compared to 4.2 in pre-resonant case). Therefor,
600 higher voltage step ratio can be realistically implemented
in post-resonant case, which is clearly a preferred option
It is noted that both terms kl and k2 are positive and
for the converter design.
less than one, and then, k1 < 1jk2. Table I presents some
calculated values for these terms to give a clear picture.
It can be seen that L2C must be tuned very close but F. Capacitor voltage
not equal to w. If L2C varies slightly then L2C > �2 The voltage across the capacitor can reach several
and k2 becomes negative, and this causes instability. times the high voltage level, which would cause a high
current passing from the capacitor. Using equations (22) current for side 2 and 1 determined from (17) and (18),
nad (32), we obtain kl and k2 as respectively:
VI � 1
kl = --y1 -r (36) 12aese2.n = - (46)
V2 ,
2
V2 V2 � �
k2 = kl . -2 = --y1 -r- (37) haeSe2.n = -'----'- (47)
VI VI ,
where, = wCR2 �� and must be less than one. Thus, where subscript "n" denotes the normalized value.
the maximum value for C is Therefore, , can be presented as a single design
parameter for converter. Figure 7 shows k2, Vc and
V2 1 normalized fault currents versus " for a 100-MW 300-
Cm ax = . . (38)
VI wR2 kV120 kV 1500 Hz test system. It is observed that
As a result, the capacitance C is expressed as increasing, causes decreasing Vc and short circuit cur
rents, which is desired. However, this results in reducing
C = " Cm ax. (39) the absolute value of k2, which may lead to the system
instability. For the ease of estimating " the resonant
From (6) and (17), we calculate the capacitor voltage
frequencies for the converter has been plotted in Figure
8. The converter resonant frequency is approaching the
- . V2d . 2 1 switching frequency as , is decreasing. As a result, ,
Ve = V2 d+ JwL2 = V2d(1+ JW L2C ). (40)
R2 R
w 2C
:A-
must be carefully selected to avoid any instability caused
It is noted that V2d = and deriving (36) and (37) by working close to the resonant frequency.
into (40), the capacitor voltage magnitude is calculated:
(41)
',L____�--------�
G. DC fault analysis
gam:! gama
Prior to applying the fault analysis to the LCL con
verter, we assume that the converter is operating atn
full power and that the switches remain at maximum
conduction ((31 = (32 = 7r /2) for high-power application.
This results in having a constant magnitude for VIae
equal to 4V1/7rV2. A DC fault is applied at terminal 2
(V2 = 0), which implies V2ae = O. Using this condition " L__________���
with (5), (6) and (7), we can calculate the short circuit gama gama
- j - 1
12aese2 = � VIae' (42)
L2 + k2Ll
Il aeSe2 = -k2 . 12aeSe (43)
4
A
•
Step 1: FInd V2ac = -; V2. all voltages in simulation are measured as pole-neutral
Step 2: Calculate R2 using (27). values.
-V2
Step 3: Plot graphs as in Figure 7 and choose "( for
an acceptable range of Vc and k2.
Step 4: For selected "(, calculate k1, k2 and Cm ax
using (36), (37) and (38), respectively.
Step 5: The capacitance C and inductance L1 and L2 1.6 2
Time(s)
can be determined as
�
IOOO
500
0
wmmm
-Vc
· · · · · · ·
..... .. -j········· 1 · ........ ( .. .....:........ ·t········· ; " ........ ( .. ... .
'" ...... : ...... .. j ... ..... : ...... ...'.... ......; ....... .. : ... ...... : ...... ..
(48)
(49) .::=
0.9995 1 1.0005 1.001 1.0015 1.002 1.0025 1.003 1.1)035
Time (!I)
-Hac
(50)
-I2ac
t 1.0005 1.001 1.0015 1.002
Timc(s)
1.0025 1.003 1.0035
'J�
procedure, we compare the results to the work by lovcic
and Zhang [14] for a lOOMW 300-kV120 kV LCL
converter. Using illustrated design steps and Figure 7
0.9995 I 1.0005 1.001 l.0015 1.002 1.0025 1.003 1.0035
and 8, we have selected "( = 0.65 as the optimal value, Timc(s)
with each other for the bridge 1, which results in zero A 200-W laboratory prototype converter was built to
switching and minimizing stress on switches. Note that validate the design procedure and simulation model. The
0' 4
0.2 ...
�
-Hac
... .
•
......... .
•
.. . .
•
.
•
.. .. ....•.... .. . .
•
........ .
•
.. . .
•
; .. .. ...
<:jEr: mm '
-P2
0.2 ·
mml Figure 11: Experiment Setup
o ------�------�----�----��----�
o � u U U 2
Tim.(,)
(b 1 Transferred Power