co I

Basics VLSI Design and Technology

of

1 Fabrication slips of
Pros transistor
NMOS transistor
n well CMOS process
P well CMOS process
twin tub process

iton
Important fabrication steps in NMOS Coro CMOS

process are

1 oxidation
2 diffusion
3 Ion implantation
4 Lithography and etching
5 Metallization

1 Single crystal silicon is used for fabricating

the IC's
2 oxidation
Oxidation is the used in growing of
process
gate oxide oxide beneath the gate in the
transistor This is very thin oxide
 cry
Field onide or thick oxide is the silicon
dioxide that is thick oxide used to separate
the layers in the IC and denies in it
There are 2 types of oxidation
i3 dryonid ation
used to grow gate oxide
takes more time to grow but defect free
Sit 02 Sioz
ii
wetoxidation
used to grow field onide or thick oxides
growth rate is speedy compared to dry
oxidation
si 1211 Si 02 211 29
20

3 Diffusion
Diffusion is the process through which controlled
amount of dopants are introduced into
the semiconductor
The basic principle underlying in this
process is that dopants atoms migrate
from a concentration to the
region of high
region of low concentration
Source and drain regions are formed
using diffusion
4 Lithography and etching
To form the wafer
patterns or shapes on

Lithography is used
Etching is the process of removing
unwanted areas on the IC during
the fabrication
UV
light is exposed to photoresist coated wafer

during lithography

5 Metallization
To form the metal contacts and interconnect
wires on the IC metallization is used
Metal is evapourated on the wafer and
removed in the unwanted areas
Aluminium is the regular metal used in
fabrication
 NMOS transistor Fabrication

polysilicon gate self aligning nMos Fabrication

processing is carried out on

a thin wager cut from a

single crystal og silicon

of high purity into which regrind p impurities are
introduced as crystal is
grown
wafers are typically 75 to 150mm in diameter
and 0.4mm thick and are doped with say
boron to impurity concentrations of co m3
to 10 land
giving resistivity in app range of
25ohm cm to 2 ohm cm

A layer of silicon
dioxide bio typically
1µm thick grown all over
is the surface of the

wafer to protect the surface This sioz acts as a

barrier to dopants during processing and provide
a generally insulating substrate onto which other
layers may be deposited or patterned
 The surface is now

covered with pho st

which is deposited
on the wafer and spun to achieve an even
distribution of the required thickness

The photoresist Lager is

then exposed to a
r Yr unayoutaida
UV light through a mask
Kardened
are which defines those
regions into which diffusion should take place
The areas exposed to UV light are hardened and
areas required for diffusion are shielded by mask
and remain unaffected
As the Uv hardened
light
the photoresist in the

exposed areas the Sioz

and photoresist in this area is
ethedaway
subsequently photoresist in the unexposed areas
is also etched off
polysilicon gate A thin layerof Sio
p
gate oxide is grown
over the entire chip

surface Than polysilicon is deposited on the surface

and patterned to form the gate structure
 impurities
is removed
If 11h Thin oxide
in the source and
drain areas

Through diffusion n type of impurities are doped

into exposed areas source and drain
of
contactholes thick oxide
p
f Thick oxide is again
grown all over

Using photolithography

and etching contact holes are opened in this

thick oxide

A metal ex Aluminium
is deposited all over
the chip and using
photolithography and etching metal contacts are

formed Typically the metal thickness is 1µm

Note
I p Mostransistiniction
on the above question in the place
of
P replace it with n
Rest of the answer remains the same

o
 CMo t
P well process
A typical CMOS invester consists of a naos and
a pros transistor on the substrate
The substrate is n type in which pros transistors
are fabricated
P well is formed in the substrate through doping
in which n Mos transistors are
fabricated
Formation of P well regions

on the n
p well is formed To form
substrate
this a
masking Lithography and etching ship
is needed in the Sioz
grown on the substrate
Mask l
actine arees
Define NMOS and pros
Quin
oxide
thin

Zeemoted

Thin oxide is grown over the substrate and

should be removed in the source and drain
regions of both NMOS and prows devices Mask 2
Polysilicon is deposited and patterned to form
gate structures for NMOS and PMOS Mask 3
 for
Find gate xide isoh.com Pfdiffusion

A pt mask is used to form P diffusion for

transistors
source and drain regions of P mos
Mask 4 The p well region is protected through
Pt
masking step
nt diffusion

the
complementary negative Pt mask
using
n diffusion takes place to form source and
drain regions of the NMOS transistors Masks

Contact cuts
Mask 6 contact cuts are formed
thick field
11774791,17174 oxide
 Metallizatras
Mask 7 Metal layer is patterned

TpFqMBE Taffy
TgqaBBq

overglers
Mask 8 An overall passivation Leyer over glass

layer is
applied and mask 8 is needed to
open the contact holes fer
glans

f f
Over
TH f
THfest 17 f's poredion
1 117117111
7

Note
If the question is asked for n well
process

just write P instead of n

and n instead of P in the above
question
have to practise on your own
you
 Imp points in n well proeers

I Formation of n wall regions

Define PROS and NMOS active areas
2
3 Field and
gate oxidations thinox
4 Form and Pattern polysilicon
5 PT diffusion
6 Mt diffusion
7 contact cuts
8 Deposit and pattern metallizelnnas
9 over glass with cuts for bonding pads

All these slips are

explained to P well process

above just interchange bP
and PEM
for n well
 Twinpan

fiddoxide

In Dual well process or twin tub process bolts

f well and n well for NMOS and PMOS transistors

respectively are formed

on same substrate
The main advantage of this process is that
threshold voltage body effect parameter and
trans conductance separately
The starting materiel for this process is
nt substrate with epitaxial n
byes grown
step 1 A thin layer of Sio deposited which
is
will serve as pad oxide
Step 21 A thicker sacrificial silicon nitride layer
is chemicel
deposited by Vapour deposition
steps A plasma etching process is used to
create trenches used for insulating the
devices
sleepy The trenches are filled with Sioz which
is called field oxide
 Steps The p well mask is used to expose
this Emplent
P well areas Cpwellformed after
to
and annealing sequence applied
is

adjust well doping This is followed by

second implant slip to adjust the
threshold voltage of NMOS transistor
slip 6 The n well mask is used to expose

only n well areas Cn well formed after this

implant andannealing sequence is
applied to adjust well doping This is
followed by second implant step to
adjust the threshold voltage of PMos transistor
step 7 A thin layer of gate oxide and
polysilicon is chemically deposited and
patterned
steps ht implantation is done in p well
to form source and drain regions of
nmos transistor and covering n well region
step 9 Pt implantation is done in n well
form source and drain regions of
pros transistor and covering p well region
step co Metal is deposited and patterned to
form contacts
step 11 A glass layer is deposed and contact holes
are opened through Patternin
 MOSFET operation Ias derivation Ias Wds relations
xt
MOSFET is metal oxide Semiconductor field effect
transistors
Two modes transistor operation
of
1 Enhancement mode operation
2 Depletion mode operation

NMOS
onide gale
Polysilicon
metal
Ptdiffusion
y y
depletionregion
n substrate

PMI

what the MOSFETs BLTs

are advantages of over

1905 BIT
1 Low static power dissipation 1 High powerdissipation
2 High packaging density 2 Low packaging dens b
3 Low output driving current 3 High output driving
current
4 Low gm 4 High gm
 gm c gh
ENHANCEMENT MODE TRANSISTOR ACTION

All Voltages in a MOSFET are applied w r t Source

1 OFF state or NON conducting state

when was _O and VDS _0 there are no

charge carriers
in the channel hence the transistor is
said to be in OFF r NON conducting State
ohmic or Non saturated state
2
AIDS

1
I VDS
when the gate voltage
of an naos transistor is
slightly increased due positive charge that is
placed on the gate a vertical electric field exists
between the gate and the substrate across the
oxide
The holes which majority carriers in p substrate
are

near the surface feel this electric field and

repel away from the surface Hence depletion
region is in
formed the transistor
of gate voltage of the nmos transistor
the
is further increased the vertical electric

field is strong enough to attract electrons

which are minority carriers in p substrate
These electrons accumalete near the surface
and form a channel
Threshold Voltage
At a certain gate voltage the number of
charge carriers electrons in the channel
is
equal to
number
of holes in the Substrat
This voltage is called thr Q.ge
on NMOS transistor the surface is inverted
to n type and in pros transistor the surface
is invested to p type
Since the drain and the source are at

same
voltage channel carrier distribution
is
uniform along the device
IDs
N

µ
ggy
VD
 when the Uas is applied a horizontal electric
field attracts the electrons in the channel
and current Ids flows from drain to
source The current increases in the channel This
is called ohmic Cor Non saturated state
region
Saturation Region

Due to this current a corresponding IR Vds

drop exists along the channel This voltage
drop varies from source to drain

The effective gate voltage is Vg Ugs Vt

when U cut no current flows

gs
As
long as Ugs Ve Yes is there this voltage
is
sufficient to invert the surface at
the drain end
when Ugs Ve Vds the condition is called
condition
limiting

of Vds is increased further Vds Uop Vt There

is no
sufficient electric field to invert the
the drain end The channel
surface near

is called as pinched off

 IDS Ve
Vds Ugs
get
Has

VDS

when the Vds is further increased the

towards
pinch off point moves source

and current becomes constant

The constant electric field in the depletion
constant
region is responsible for
the
current in the saturation region

Transistor circuit symbols

Depletion Mode transistor

Depletion mode mosfet is a

normally 0N
device
It has a narrow n channel buried between
Source and drain near the surface i e
n type dopants are implanted near the
surface
Free electrons are available in the channel
Ups o and negative gate voltage
a
of
is applied the holes are attracted from
the body of the transistor to the surface
and recombine with electrons in the
channel and channel is depleted
Vps positive voltage current floors
of
from drain to source as electrons move
from Source to drain even when Vas _ou
 Drain to Source Current Ids Versus Voltage Was
Rdationshops

The whole concept

of Mos transistor evolves from the
use
of voltage on the gate Vgs to induce a
a

charge in the channel between source and

drain which to move from
may then be caused
source to drain under the influence
of an
electric field created by voltage Vds applied between
drain and Source
Ids is dependent on Vgs and Vds
d ced
in the channel
Ids Q c Qc charge in a

Z E Electron transit time

Zsa L Length the channel

If U Velocity
of
of the carriers

U Electron hole mobility

µ Eds µ
Eds Electric field
 Eds _Vds
IL
in
Substituting
D µ Vds
c
in
substituting

7
The non saturated region ohmic region
to
charge induced in the channel is due
between
Vgs is due to voltage difference
gate and channel
voltage along the channel varies linearly
with distance X from source due to IR

drop in the channel

Device is not saturated and average
voltage in the channel is Vds z
Effective gate voltage Vg Vgs Vt
Ut is threshold voltage
 charge unit area Eg Eines Eo
W L
Qc Eg Eins Eo
6
Total Induced charge
Eg average field gate to channel
electric
Cins _relative permittivity of Sioz 8 85 10 Hcm
Eo pennitivity of free space
average
gatevoltage drop in the
f channel
Eg Ngs Ve Vash
D
D thickness of oxide
in
substituting

QEWLC Ngs Ve
jns.co VDI

and in
4,8
Ids Ci oI wz Cgs Vt
Qq Hz Vds
2
pg
I Ids K wzfCVgs VHVds
Vdsz2JK EinsggEo.t
MVDS.G gate capacitance per
unit once
 thcow fcvgs hJVds V.dz
IId5
VdsCVgs VE

Saturated region
In saturation region Vds Ugs Veh substitute
Vds Vgs Vch in non ohmic region current

equation

2
Ids Co
_An hfflugs ve Ugs Ve Vgs

2
Ids fin YzG Ugs Ve

Yds_Vgs VE

conditions of operation in MOSFET

f OFF condition Vds _O

Vgs O
2 Channel formation Vgs Ve Vds 0
3 ohmic region cos
non Saturation region Ugs Ve Vds
4 Saturation region Vds Vgs Ve
Mostoansistorch aretn.es

nm

modedmce.Enmodedcrice

ORF stale

o
 Thr Ye
The threshold Ut is defined minimum
Voltage as

gate voltage was that is needed to create

to source
a
conducting path channel between source and
drain terminals

if 2VNAC.si
20
f r VsB
Cox

Off fermi potential of Silicon

y f Esi
Vsz substrate bias voltage Con
Con oxide thickeners
gate
per unit area

Veco Threshold voltage for

substrate bias
Zero
P substrate
Na doping concentration of
67 threshold Voltage when Usz O

GiF
Velo
F riff
Dvt Vt Uto

DV t
rf tVzl If
 alternatively
Vt V'to 1 DUE
Uto 18 tTI

D
transistor is
The threshold Voltage a
of
on
dependent
1 Substrate doping
2 thickness the gate oxide
of
3 channel length

1 ng
Threshold voltage increases with the
doping
concentration the substrate
of
As the doping increases a higher gate voltage
is
required to move the majority carriers
away from the Channel region
Solution is to
adjust the doping concentration
different than the substrate

2 Gateo mide
From the equation the threshold voltage ne
of
Ut is directly proportional to the thickness
of
the oxide
 The thinner oxide reduces the threshold Voltage
while thicker oxide increases the threshold

voltage

3 channell ength
The threshold voltage is less tes Smaller
Channel lengths short channel effects are

observed within the transistor

o

Body effect
USB is the voltage applied between body and
source to keep the source substrate and
drain substrate
junctions reverse biased
From the threshold Voltage egi

Ut Vtotrfflofts tot
increasing Us Causes channel to be depleted
of the charge carriers and threshold voltage
is increased
DV t
rf tVzl If
DUEL FSB r is a constant which depends
on substrate doping so that more lightly
duped the substrate smaller will be body effect
o
MoS Transistor Trans conductance gm

Trans conductance expresses the relationship

between output current Ids and input
and is defined
Voltage Yp as

gm of Ids
Fp Vds constant
To calculate the value
of gm
The charge in channel Q is such that

I z is transit time

change in current
o
smuederiration
from oIas remit
s

qz
Cds
gas Eds Vdsz

in re
substituting Eds pieds
L
8 4d t
dIds I as
L2
But change in charge
dQc G Jugs
 d Ids Cg digs Vds fl
L2

gm dids cg.tvgs Vd
Jugs exgs L2
Cg M Vds
T
In saturation
Vds Ugs Ve

gm E
Z
wL
Cg Esio
gm µEsiozEo wz Vgs Vel D

lgm pcxgs.ve p MGijI.E

d is possible to increase gm of Cte

MoS device by increasing its width
This increases the input capacitance delay are

o
 out
Y gas

Gds didst
Stds
d X Ids
F channel length
L 1 1 modulation
L L
parameter
21 XXL
LZ L

Idsa L
L

observations
I Reduction in channel length L increases
Wo and higher gm
2 But mos device decreases with
gain of
degradation of output
resistance f gta
 Mos Transistor merit
figure of
word

Wo _Gm But gm G M Vgs 42

Cg z

f
M cvgs.hr
fwoi

The indication of frequency response can

be obtained
from Wo
Switching speed depends on
gate voltage above threshold voltage
Mobility m2
inversly to channel length
square g

A faster circuit
requires gm as high
as
possible
M 15 Electron mobility on L too oriented
silicon surface pm is larger
than 1117 Surface

An 3Mp
µ is also dependent on Ugs Ve
 Bivonvind
list out extrasteps involved it
There are advantages observed in
several
Biomes of properties of Cios and bi poler
technologies are combined
T A few
processing slips increase compared
to CMOS febnicdn.cn

density reduces compared

packaging
Coctos
cost increases compared to Chaos

The
high impedance Cmos transistors can
be used for input circuitary while
remaining stages and output drivers
are reelized using bi polar transistors

The additional processing steps are due

to formation
of npn transistor along
with Cmos devices

The additional process steps in a N well

Bicraos fabrication ere
given below
 single poly single Additional steps for
metal crios Bi Polar devices
I Form n well
2 Form buried ntlayerCBCCD
3 Delineate active areas
4 Channel ship implantation
5 Form deep H collector
6 Threshold Vt implantation
7 Delineate
polyfgate armes
8 Form Nt active areas
9 Form Pt active axes
10 Form Pt base for BLT
11 Define contacts
12 Delineate metal axes

Steps 2,5 10 are additional steps in a

Bialas fabrication Refer diagram in neat

pages
Bi7os
CMOS Bice905
processing steps less more

packaging density more less

cost less more
low high
power dissipation
 Input impedance low high more drive
current
Noise High lens
margin
Delay sensitivity high low more
jam art
Output drive current low high
transcenduetanucgn low high