Semiconductor Technology

Shafy Eltoukhy , Ph.D.

Agenda
• Integrated Circuits (IC’s) functions
• Memory , Digital , Analog
• IC’s Manufacturing flow
• CMOS wafer processing
• Packaging technologies
• Moore’s Law
• Scaling up
• Scaling down
• Scaling out
• System Integration
• Semiconductor Evolution Comparison

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Smart Phones Block Diagram and IC’s

Multiple IC’s performing different functions

Design Abstraction Levels From Transistor to System
SYSTEM

MODULE
+

GATE

CIRCUIT

DEVICE
G
S D
n+ n+

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Types of Semiconductor Chips
• Memories
• Store digital data
• Microprocessor
• Central processing chip programmed at the SW level with instructions to execute
important tasks such as connecting to a cellular network
• Field Programmable Gate Array (FPGA)
• Contains digital circuits blocks and memories that can be configured and updated by the
user to perform certain task
• Application specific integrated circuit (ASIC)
• Contains digital instructions that are specifically customized to a certain purpose
• Analog & RF Chips
• Interface with the real world to perform sensing or measuring physical parameters ,
power management , transmitting radio signals etc.
• Analog Mixed Signals (AMS)
• Integrate analog and digital blocks to perform more complex functions
• System on Chip (SoC)
• Integrate processors such as ARM , digital and limited number of analog functions
• System in Package (SiP)
• Integrate all of the above in a single package

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Memory Types
• Volatile Memory : Loses its stored data when the power turned
off. However, it can be faster than non-volatile memory. This
type is used for the main memory in most computers
• DRAM (Dynamic RAM) Memory cells consisting of one capacitor and one transistor to store
each bit. It is the cheapest and highest in density, so it is used for the main memory in
computers. However, the charge that stores the data slowly leaks off, memory cells must be
periodically refreshed (rewritten)
• SRAM (Static RAM) Several transistors to store each bit. Less dense and more expensive
than DRAM, but faster and does not require refresh. Used for cache memory in computers

• Non-Volatile Memory : Preserves the data stored in it during

periods when the power to the chip is turned off
• ROM (Read Only Memory) is designed to hold permanent data, and in normal operation is
only read from, not written to
• NVRAM (Flash Memory) it can be written to, but not fast enough to serve as main memory.
It is often used as a semiconductor version of hard disk, to store files

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Integrated Circuits Manufacturing flow

• Dedicated , expensive and very clean facilities (Fab)

Wafer Process • Masking steps , layers etching & deposition , implants etc.
• In line measurements , QA inspection, Elect. testing

• Visual inspection , probing hardware , electrical testing

Wafer Test • Separate good and bad chips (dies) , Yield analysis

• Die dicing , die attachment to the package

Packaging • Wire bonding , package encapsulation , marking codes

• Testing hardware , testing at speed and high temperature

Final Test • Speed binning , burn-in , out going quality inspection
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Four Basic Wafer Processing Steps
• Deposition
• Any process that grows, coats, or otherwise transfers a
material onto the wafer
• Removal
• Any process that removes material from the wafer
• Patterning
• The shaping or altering of deposited materials, and is
generally referred to as Lithography
• Modification of electrical properties
• Historically entailed doping transistor sources and drains
originally by diffusion furnaces and later by ion implantation

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 Simple Example of Oxide Patterning
Chemical or plasma
etch
Si-substrate
Hardened resist
SiO
2
(a) Silicon base material
Si-substrate
Photoresist
SiO
2 (d) After development and etching of resist,
chemical or plasma etch of SiO
Si-substrate 2

(b) After oxidation and deposition Hardened resist

of negative photoresist SiO
2
Si-substrate
UV-light
Patterned (e) After etching
optical mask

Exposed resist
SiO
2

Si-substrate Si-substrate

(f) Final result after removal of resist

(c) Stepper exposure

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Basic Wafer Processing Steps
• Front-end-of-line (FEOL) processing : Transistors
• Processing refers to the formation of the transistors directly in
the silicon wafers. The raw wafer is engineered by the growth of
an ultrapure, virtually defect-free silicon layer through.
• In the most advanced logic devices, tricks are performed to
improve the performance of the transistors to be built such as
Gate Oxide and Source Drain

• Back-end-of-line (BEOL) processing : Metal layers

• Once the various semiconductor devices have been created,
they must be interconnected to form the desired electrical
circuits. This occurs in a series of wafer processing steps
• Processing involves creating metal interconnecting wires that are
isolated by dielectric layers. The insulating material has
traditionally been a form of SiO2 but recently new materials are
being used to reduce capacitance

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CMOS Process Engineering Innovation Examples

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IC’s Packaging
Semiconductor Devices Vs. Nature Dimensions
Nature Made Semiconductor Lithography

Line width starting point (~1960) ( < 0.5x Human hair)

Scaling down by > 3 order of magnitude (Moore’s Law)

Flu Virus

Line width state of the art dimensions (5x the DNA size)

2014 Semiconductor IC’s Market ~ $330 Billions

Pakistan Growth Domestic Product ~ $250 Billions
Moore’s Law : Scaling Up Period
• It is more of a discipline and self-fulfilling prophecy than a law
• 1965 : Transistor counts had doubled every year since 1958
• 1975 : Moore altered it to “doubling every two years”
• 1970’s-1980’s : Scaling Up Phase
• New technology generation introduced every 3 years
• Transistor density increased by 2x every 3 years
• And we were also increasing chip size
• Hence doubling transistors count every 18 months
• Industry stuck at 5v power supply due to legacy systems
• Pushed transistor reliability and hence, lifetime to uncomfortable zone
• Dr. Dennard to the rescue

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Moore’s Law : Scaling UP Period

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Dennard Scaling Down

• Gives the industry the roadmap to continue Moore’s law

• Scale Transistor dimensions by 0.7x (k=1.4) every generation
• Scale down voltage by 0.7x to keep electric field constant
• Transistors will switch faster and use less power
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1990’s : Golden Age of Scaling
• Scaling down phase
• Voltage drop from 5v to 1v in ~ 10 years
• Transistor delay decrease (Higher frequency)
• Switching energy decrease
• Transistor turn-on voltage decrease
• When dimensions got too small
• Significant transistor leakage around 90nm
• Gate Oxide too thin and start leaking
• Hard to control transistor leakage when turn-on voltage is
too low
• Voltage scaling has to slow down
• Higher power due to leakage

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Moore’s Law : Scaling Down Period

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Transistor Cost Trend

• Cost crossover not quite on 2 year cadence

• 20nm & 14nm transistor cost will be higher

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Moore’s Law : Scaling Out Period (Power Supply Wall)

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Moore’s Law : Scaling Out Period (Leakage)

• Lower Gate Leakage due to High K Metal Gate (HKMG)

• Lower Ioff leakage using FinFET Transistor
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More than Moore
System Integration

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3D System in Package

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Evolutionary Comparison

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