8 – PSK Bandwidth and Receiver

By: Engr. Wendell L. Gonzales

 Bandwidth considerations of 8-PSK
• With 8-PSK, because the data are
divided into three channels, the bit rate
in the I, Q, or C channel is equal to one-
third of the binary input data rate
(fb/3).
• The bit splitter stretches the I, Q, and C
bits to three times their input bit
length.
• Because the I, Q, and C bits are
outputted simultaneously and in
parallel, the 2-to-4-level converters also
see a change in their inputs (and
consequently their outputs) at a rate
equal to fb/3
 Bandwidth considerations of 8-PSK
• Figure shows the bit timing
relationship between the binary input
data; the I, Q, and C channel data, the
I and Q PAM signals.
• It can be seen that the highest
fundamental frequency in the I, Q, or
C channel is equal to one-sixth the bit
rate of the binary input (one cycle in
the I, Q, or C channel takes the same
amount of time as six input bits).
• Also, the highest fundamental
frequency in either PAM signal is equal
to one-sixth of the binary input bit
rate.
 Bandwidth considerations of 8-PSK
• With an 8-PSK modulator, there
is one change in phase at the
output for every three
data input bits.
• Consequently, the baud for 8
PSK equals fb/3, the same as
the minimum bandwidth.
• Again, the balanced modulators
are product modulators; their
outputs are the product of
the carrier and the PAM signal.
Example:
For an 8-PSK modulator with an input data rate (fb)
equal to 10 Mbps and a carrier frequency of 70 MHz,
determine the minimum double-sided Nyquist
bandwidth (fN) and the baud.

Ans. BW = 3.33 MHz; Baud = 3.33 Mbaud

 8 – PSK Receiver
• The figure shows a block diagram of
an 8-PSK receiver.
• The power splitter directs the input 8-
PSK signal to the I and Q product
detectors and the carrier recovery
circuit.
• The carrier recovery circuit reproduces
the original reference oscillator signal.
• The incoming 8-PSK signal is mixed
with the recovered carrier in the I
product detector and with a
quadrature carrier in the Q product
detector.
 8 – PSK Receiver
• The outputs of the product
detectors are 4-level PAM signals
that are fed to the 4-to-2-level
analog-to-digital converters (ADCs).
• The outputs from the I channel 4-
to-2-level converter are the I and C
bits, whereas the outputs from the
Q channel 4-to-2-level converter
are the Q and and bits.
• The parallel-to-serial logic circuit
converts the I/C and Q/ bit pairs
to serial I, Q, and C output data
streams.
 16 - PSK
• 16-PSK is an M-ary encoding technique where M 16;
there are 16 different output phases possible.
• With 16-PSK, four bits (called quadbits) are combined,
producing 16 different output phases.
• With 16-PSK, n = 4 and M = 16; therefore, the minimum
bandwidth and baud equal one-fourth the bit rate (
fb/4).

Prepared by: Engr. Wendell L. Gonzales, ECE

 16 - PSK
• With 16- PSK, the angular
separation between adjacent
output phases is only 22.5°.
• Therefore, 16-PSK can undergo
only a 11.25° phase shift during
transmission and still retain its
integrity
• For an M-ary PSK system with
64 output phases (n = 6), the
angular separation between
adjacent phases is only 5.6°.
END