ENUGU STATE UNIVERSITY OF SCIENCE AND

TECHNOLOGY
FACULTY OF APPLIED NATURAL SCIENCES
DEPARTMENT OF COMPUTER SCIENCE

ASSIGNMENT BY GROUP B
COURSE TITTLE: ASSEMBLY LANGUAGE
COURSE CODE: CSC 353
LECTURER: MR. BABATUNDE OLOFIN
DATE: 15TH MARCH 2017
 NAMES OF STUDENTS IN GROUP B
GROUP LEADER: FRANCIS OGBONNA

S/N Names Reg. No

1 Francis Ogbonna Esut/2014/155200
2 Ifemena Samuel Esut/2014/155192
3 Owoh Chinonso Juhoiakin Esut/2014/
4 Emmanuel Ikechukwu Ugwuanyi Esut/2014/
5 Chukwu Amos Onyedika Esut/2014/155195
6 Ozor Chiedozie Christian Esut/2014/
7 Confidence C . Chibuoke Esut/2014/155197
8 Daniel Obinna Nebo Esut/2014/155198
9 Obinna Michael Eneh Esut/2014/155199
10 Ngwu Chinonso Emmanuel Esut/2014/
11 Victor Chukwu Nnakwe Esut/2014/155203
12 Obinna Dialoke Esut/2014/
13 Ude Collins Esut/2014/155205
14 Onuh Stanley Chizoba Esut/2014/155206
15 Cynthia Ozioma Ani Esut/2014/
16 Ernest Arinze Ikeh Esut/2014/
17 Innocent Chisom Amadi Esut/2014/
18 Nelson Tochukwu Udeh Esut/2014/155209
19 Emeka Emmanuel Ozoaka Esut/2014/155210
20 Emmanuel chinedu Onah Esut/2014/
21 Ogenyi Marthins Chukwuebuka Esut/2014/
22 Simeon Ifeanyichukwu Agbo Esut/2014/155213
23 Leonard Obinna Offor Esut/2014/155214
24 Lovenah Ifunanya Okafor Esut/2014/
25 Ogolo Ernest Idah Esut/2014/155217
26 Cyprian Michael Otum Esut/2014/155218
27 Murphy Ugochukwu Ozor Esut/2014/155219
28 Onyinyechukwu Benita Okoye Esut/2014/
29 Onyedikachi Michael Eze Esut/2014/155221
30 Ugochkwu Chinagorom Orji Esut/2014/155223
31 Chisom Emmanuel Eze Esut/2014/
32 Kenneth Chekwube Odo Esut/2014/155225
33 Emmanuel Chibuike Nchuma Esut/2014/155226
34 Okorie Charles Okwudiri Esut/2014/155228
35 Chisom Loveth Nwagu Esut/2014/155229
36 Onyia Ogonna Andrew Esut/2014/155230
37 Chinaza Modesta Onuorah Esut/2014/155231
38 Martins Amobi Ugwu Esut/2014/155232
39 Roseline Ukamaka Nwankwo Esut/2014/155233
40 Ngene Kingsley Esut/2014/
41 Emeka Innocent Odoti Esut/2014/155235
42 Chikwe John Chika Esut/2014/155236
43 Ogbuzuru Amarachi Benjamin Esut/2014/
44 Gabriel Ifeanyichukwu Ani Esut/2014/
QUESTIONS ON PAGE 143 NO. 15 – 33

15. What is a clock cycle?

Answer:
Clock cycle is one full period.

16. What is the relationship between clock frequency and the clock period?
Answer:
Clock frequency is the number of clock cycle per second while clock period is the tine taken to
switch from zero to one and back to zero. Frequency (f) = 1 / period (T)

17. How many clock cycles are required for each of the following to read a byte from memory?
a) 8088 b) 8086 c) 80486
Answer:
Processor Clock cycles required
8088 4 clock cycles
8086 4 clock cycles
80486 A clock cycle

18. What does the term “memory access time” mean?

Answer:
Memory access time is the amount of time between a memory request operation (read / write)
and the time the memory operation completes.

19. What is a wait state?

Answer:
A wait state is the extra clock cycle given to some device to complete their operation.

20. If you are running an 80486 at the following clock speeds, how many wait states are
required if you are using 80ns RAM (assuming no other delays)?
a) 20 MHz b) 25 MHz c) 33 MHz d) 50 MHz e) 100 MHz
Answer:
Clock speeds No of wait states
20 MHz 2 wait states
25 MHz 3 wait states
33 MHz 3 wait states
50 MHz 4 wait states
100 MHz 4 or 5 wait states

21. If your CPU runs at 50 MHz, 20ns RAM probably won’t be fast enough to operate at zero
wait states. Explain why.
Answer:
The CPU has only but 20 ns clock period , during memory access time 10 ns will be used by
decoding and buffering circuitry this cause delay in the system leaving 10 ns or less for the CPU to
access data which is not enough.

22. Since sub-10ns RAM is available, why aren’t all system zero wait state systems?
Answer:
Though a sub-10 ns RAM is available it is very expensive, consumes a lot of power and generates
heat. All this are bad attributes that discourage users.
23. Explain how the cache operates to save some wait states.
Answer:
The catch memory saves some frequently accessed memory locations in its memory.
A catch hit occurs when the CPU accesses memory and finds the data in the catch in such situation
the CPU experiences a zero wait state.

24. What is the difference between spatial and temporal locality of reference?
Answer:
Spatial locality of reference occurs when a program accesses neighbouring memory locations
within a short interval of time. While Temporal locality of reference is when the program accesses
the same memory location in a short time period.

25. Explain where temporal and spatial locality of reference occur in the following Pascal code:
while i < 10 do begin
x := x * i;
i := i + 1;
end;
Answer:
Temporal locality of reference during the loop check I < 10 and during the increment of I the same
memory location is accessed within a short time.
Spatial locality of reference occur at X := X + I the memory location of are accessed (two
neighbouring memory locations)in a short period of time.

26. How does cache memory improve the performance of a section of code exhibiting spatial
locality of reference?
Answer:
The catch memory stores the memory locations of the two adjacent variable making it easy for
the program to access with zero wait state.

27. Under what circumstances is a cache not going to save you any wait states?
Answer:
A catch miss. This happens when the CPU access memory and the data is not on the catch
memory.

28. What is the effective (average) number of wait states the following systems will operate
under?
a) 80% cache hit ratio, 10 wait states (WS) for memory, 0 WS for cache.
b) 90% cache hit ratio; 7 WS for memory; 0 WS for cache.
c) 95% cache hit ratio; 10 WS memory; 1 WS cache.
d) 50% cache hit ratio; 2 WS memory; 0 WS cache.

29. What is the purpose of a two level caching system? What does it save?
Answer:
The purpose of a two level catching system is to improve performance. It saves cost.

30. What is the effective number of wait states for the following systems?
a) 80% primary cache hit ratio (HR) zero WS; 95% secondary cache HR with 2 WS; 10 WS
for main memory access.
b) 50% primary cache HR, zero WS; 98% secondary cache HR, one WS; five WS for main
memory access.
c) 95% primary cache HR, one WS; 98% secondary cache HR, 4 WS; 10 WS for main memory
access.

31. Explain the purpose of the bus interface unit, the execution unit, and the control unit.
Answer:
Bus interface unit: The bus interface unit (BIU) is responsible for controlling the address and data
busses when accessing main memory. If a cache is present on the CPU chip then the BIU is also
responsible for accessing data in the cache.

Control unit: the control unit (CU), fetches instruction codes (also known as operation codes or
opcodes) from memory and moves them to the instruction decoding register. The control unit
contains a special registers, the instruction pointer that contains the address of an executable
instruction.
The control unit fetches this instruction’s code from memory and places it in the decoding register
for execution. After executing the instruction, the control unit increments the instruction pointer
and fetches the next instruction from memory for execution.

Execution unit: The execution unit tells the bus interface unit where to fetch data. It decodes and
executes instructions fetched by BIU.

32. Why does it take more than one clock cycle to execute an instruction. Give some x86
examples.
33. How does a prefetch queue save you time? Give some examples.

Answer:

The prefetch queue saves time by acting as a buffer between the instruction stream in the
memory and the opcode fetching circuitry. For example, if you execute two one-byte instructions
in a row, the BIU can fetch both opcodes in one memory cycle, freeing up the bus for other
operations. The CPU can use these available bus cycles to fetch additional opcodes or to deal with
other memory accesses.
QUESTIONS ON PAGE 190: NO. 9 – 17
9) Given the bit pattern for the generic MOV instruction (see “The 80x86 MOV Instruction”
on page 166) explain why the 80x86 does not support a memory to memory move operation.
Answer:
The move instruction opcode form does not support it.

10) Which of the following MOV instructions are not handled by the generic MOV instruction
opcode? Explain.
a) mov ax, bx b) mov ax, 1234 c) mov ax, I
d) mov ax, [bx] e) mov ax, ds f) mov [bx], 2
Answer:
C) mov ax,I a constant being moved must be a numeric constant in hexadecimal notation.

11) Assume the variable “I” is at offset 20h in the data segment. Provide the binary encodings
for the above instructions.
Answer:
The binary encoding will be mov ax, [200h]

12) What determines if the R/M field specifies a register or a memory operand?
Answer:
The MOD.

13) What field in the REG-MOD-R/M byte determines the size of the displacement following
an instruction? What displacement sizes does the 8086 support?
Answer:
The MOD field determines the size of the displacement.
8086 supports zero, one, two, and four byte displacement size.

14) Why doesn’t the displacement only addressing mode support multiple displacement
sizes?
Answer:
This is because it’s a 32 bit constant (displacement), an offset from the beginning o memory.

15) Why would you not want to interchange the two instructions “mov ax, [bx]” and
“mov ax,[ebx]”?
Answer:
This will amount to moving a 32-bit register into a 16-bit register. Intel processors does not
support such operation.

16) Certain 80x86 instructions take several forms. For example, there are two different versions
of the MOV instruction that load a register with an immediate value. Explain why
the designers incorporated this redundancy into the instruction set.
Answer:
Its to achieve greater efficiency between this two instruction set one is two byte long and the
other one byte which executes faster.

17) Why isn’t there a true [bp] addressing mode?

Answer: This is because all addressing modes involving [bp] uses the stack segment by default.