Analog and Digital Electronics ESC301

Sequential Circuits – Triggering of

Flip-flops

S.C.Puri
Department of ECE
Asansol Engineering College

1 S.C.Puri
Asansol Engineering College Department of ECE
 TRIGGERING OF FLIP-FLOPS

➢The momentary change in clock input of flip-flop to

switch it from one state to the other is called trigger and the
transition it causes is said to trigger the flip-flop.

➢The process of applying the clock signal to change the

state of a flip-flop is called triggering.

➢There are two types of triggering the flip-flops:

✓level triggering and

✓edge triggering
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 LEVEL TRIGGERING OF FLIP-FLOPS

➢In level triggering, the input signals affect the flip-flop only when
the clock is at logic 1 level. Such type of flip-flop knows as level
triggered flip-flops.

➢In a level-triggered flip-flop, the output responds to the data present

at the inputs during the time the clock pulse level is HIGH. That is,
any changes at the input during the time the clock is active (HIGH)
are reflected at the output as per its truth table.

➢Since the flip-flop changes its state only when clock pulse is
HIGH, this is also referred to as positive level triggered flip-flop.

➢Flip-flop changes its state when clock pulse is LOW and it is called
negative level triggered flip-flop.

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 LEVEL TRIGGERING OF FLIP-FLOPS

positive level

Negative level

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 EDGE TRIGGERING OF FLIP-FLOPS
➢The clock changes state from 0 to 1 or 1 to 0, as shown in the
Figure.

➢ The change of state from 0 to 1 is known as positive edge and the

change of state from 1 to 0 is known as negative edge.

➢ In edge triggering, the input signals affect the flip-flop only if they
are present at the positive going or negative going edge of the clock
pulse.

➢The flip-flop that responds for the positive edge is known as

positive edge-triggered flip-flop.

➢The flip-flop that responds to the negative edge is known as

negative edge-triggered flip-flop.

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 EDGE TRIGGERING OF FLIP-FLOPS

positive level

Negative level

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 LOGIC SYMBOL OF EDGE TRIGGERED FLIP-FLOPS

Logic symbols of Logic symbols of

positive edge-triggered negative edge-triggered
FF FF

➢The race-around condition is a major problem in J -K flip-flop.

➢ To overcome this problem, edge-triggered circuits can be used

whose output is determined by the edge, instead of the level, of the
clock signal.
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 LEVEL TRIGGERED FLIP-FLOPS

✓The master is set according to J and K while the clock is high; the
contents of the master are then shifted into the slave (Q changes state)
when the clock goes low.

✓This particular flip-flop might be referred to as pulse-triggered, to

distinguish it from the edge-triggered flip-flops previously discussed.

✓The master is clocked in the normal way but the inverted clock is
applied to slave i.e, the master is positive-level-triggered and the slave
is negative level-triggered.
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 Thank you

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