3338 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 63, NO.

8, AUGUST 2016

Study of Work-Function Variation in High-κ/

Metal-Gate Gate-All-Around
Nanowire MOSFET
Hyohyun Nam, Student Member, IEEE, Youngtaek Lee, Student Member, IEEE,
Jung-Dong Park, Member, IEEE, and Changhwan Shin, Member, IEEE

Abstract— In this paper, threshold-voltage (VTH ) variation
caused by work-function variation (WFV) in a high-κ/metal-
gate gate-all-around (GAA) nanowire MOSFET is quantitatively
estimated through 3-D technology computer-aided design simula-
tions. It is determined that the ratio of average grain size to gate
area (RGG) [i.e., RGG = G size,eff /(gate area)0.5 ] for the GAA
nanowire MOSFET should use the effective grain size (G size,eff ),
instead of using the nominal grain size (G size ). G size,eff is
regarded as the effective grain size around the channel region,
and it is smaller than the original grain size. In order to compare
the WFV-induced VTH variation in GAA nanowire MOSFET
against FinFET, the amount of WFV-induced VTH variation is
plotted using the RGG concept with G size,eff . As a result, it was
concluded that the cylinder-shaped GAA nanowire MOSFET has
better immunity to the WFV-induced VTH variation by 12.5%,
compared with FinFET.
Index Terms— Characterization, gate-all-around (GAA)
MOSFET, nanowire MOSFET, ratio of average grain size to
gate area, variability, work-function variation (WFV).
I. I NTRODUCTION
I N CUTTING-EDGE MOSFETs, a high-κ (HK) dielectric
material (e.g., HfO2 ) is adopted not only to suppress
severe gate leakage current but also to improve gate-to-channel
capacitive coupling. However, the HK material is not perfectly
compatible with the gate-stack composed of a heavily doped
polysilicon material, such that serious technical issues arise
such as threshold-voltage (VTH ) shift caused by the Fermi-
level pinning effect and phonon scattering leading to lower
mobility [1]. In order to overcome these problems, the polysil-
icon material is replaced with a metal material [2]. Although
the aforementioned issues were fairly addressed with a metal
gate (MG), the work-function (WF) values of the grains in the
MG significantly varied depending on the grain orientation.
Manuscript received March 23, 2016; revised May 18, 2016; accepted
May 26, 2016. Date of publication June 10, 2016; date of current version
July 21, 2016. This work was supported by the National Research Foundation
of Korea within the Ministry of Science, ICT and Future Planning through
the Korean Government under Grant 2014R1A2A1A11050637. The review
of this brief was arranged by Editor G. L. Snider.
H. Nam and J.-D. Park are with the Division of Electronics and Elec-
trical Engineering, Dongguk University, Seoul 04620, South Korea (e-mail:
jdpark@dongguk.edu).
Y. Lee and C. Shin are with the School of Electrical and Computer Engineer-
ing, University of Seoul, Seoul 02504, South Korea (e-mail: cshin@uos.ac.kr).
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TED.2016.2574328
0018-9383 © 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
As a result, the WF variation (WFV) triggered a significant
amount of VTH variation (σ VTH ) in the HK/MG technol-
ogy [3]. Furthermore, the WFV-induced σ VTH is greater than
that induced by either line-edge roughness or random-dopant
fluctuation in advanced device structures (e.g., fully depleted
silicon-on-insulator MOSFET and FinFET) [4], [5].
As one of the emerging advanced device structures, HK/MG
gate-all-around (GAA) nanowire MOSFETs have received
significant attention, because they can provide both improved
gate-to-channel capacitive coupling and better scalability than
other types of device structures [6]. Recently, the impact of the
WFV-induced σ VTH in the HK/MG GAA nanowire MOSFET
has been investigated; however, Nayak et al. [7] did not explain
the physical reason that the WFV-induced VTH variation for
the GAA nanowire MOSFET is better suppressed than that
for FinFET. In addition, the amount of the suppression of the
WFV-induced σ VTH in the HK/MG GAA nanowire MOSFET
was overestimated, because they did not consider the average
grain size (G size ) when comparing the WFV-induced σ VTH
between the GAA nanowire MOSFET and the FinFET in
Pelgrom plot. In order to accurately compare the variability
of devices, both gate area and G size should be considered,
because the number of grains, which is highly associated
with the amount of WFV, is affected by gate area and G size .
In this context, the ratio of average grain size to gate area
(RGG) (i.e., RGG = G size /(gate area)0.5 ) plot suggested in [8]
is better to estimate the WFV-induced VTH variation, because
both gate area and G size are considered together. For a given
RGG value, devices have the comparable number of grains
in MG, so that the variability of devices can be accurately
estimated.
In this paper, conventional RGG calculation is modi-
fied to be suitable for the GAA nanowire MOSFET. And
then, by comparing the 3-D technology computer-aided
design (TCAD) simulation results for four different Gsize with
the previously validated RGG plots for FinFETs [9], [12],
the WFV-induced σ VTH in HK/MG GAA nanowire MOSFETs
is quantitatively investigated. Moreover, the physical reason
of the suppressed WFV-induced VTH variation is carefully
illustrated for the first time.
II. S IMULATION OF WFV IN GAA NANOWIRE MOSFET
Fig. 1(a) shows a bird’s eye view of an HK/MG GAA
nanowire MOSFET. Based on the specifications of the

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NAM et al.: STUDY OF WFV IN HK/MG GAA NANOWIRE MOSFET
Fig. 1. (a) 3-D bird’s eye view of GAA nanowire MOSFET. (b) WF values
of the randomly sized grains in the TiN gate material.
Fig. 2. IDS –VGS plots for the nominal device and 200 samples
with G size of 10 nm and three different values of dNW . (a) dNW = 20 nm.
(b) dNW = 10 nm. (c) dNW = 5 nm. Note that the simulated IDS was
normalized by dNW , and the VTH was defined by the constant-current method
at 10 μA/μm × dNW /L G .
International Technology Roadmap for Semiconductors for the
16/14-nm technology node [10], a nominal GAA nanowire
MOSFET was designed using the following parameters:
a physical gate length (L G ) of 20 nm, a physical gate
dielectric (i.e., HfO2 ) thickness (TOX ) of 3.6 nm, a nanowire
diameter (dNW ) of 10 nm, a source/drain doping concen-
tration (NS/D ) of 1020 cm−3 , a channel doping concentra-
tion (Nchannel ) of 1015 cm−3 , an MG material of TiN, and
a power supply voltage (VDD) of 1.0 V. In order to estimate
the nominal device performance, 3-D TCAD device simu-
lations [11] were carried out with various models: a drift-
diffusion model with doping-dependent mobility for carrier
transport, a density gradient quantization model for quantum
confinement effect, the Oldslotboom model for bandgap nar-
rowing, and the Shockley–Read–Hall model for recombination
and generation.
TiN consists of randomly sized grains, each of which has
a different WF value depending on the grain orientation (e.g.,
a WF of 4.6 eV for (100) and 4.4 eV for (111) [3]), as shown
in Fig. 1(b). A total of 200 different GAA nanowire MOSFETs
with uniquely randomized metal grains based on Rayleigh
distribution [8] were generated. In order to alter RGG values
without changing the device parameters, four different G size
(i.e., 5, 10, 15, and 20 nm) were used. It was experimentally
proved that the value of WF for bulk TiN is valid for nanosized
regime [13].
III. R ESULTS AND D ISCUSSION
The input characteristic curves for the nominal device and
200 different samples with three different values of dNW (i.e.,
20, 10, and 5 nm) and G size of 10 nm are shown in Fig. 2.
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3339
Fig. 3. Contour plot for total current density with three different values
of dNW . (a) dNW = 20 nm. (b) dNW = 10 nm. (c) dNW = 5 nm. Note that
the channel in the GAA nanowire MOSFET allows the flow of bulk current
but not surface current when dNW is shorter than 20 nm.
The WFV-induced σ VTH in the GAA nanowire MOSFET
with a longer dNW is smaller than that with a shorter dNW
[e.g., when dNW is 20 and 10 nm, σ VTH is 23.27 and
32.45 mV, respectively; see Fig. 2(a) and (b)]. In other
words, the device with the smaller value of the RGG (which
is defined for the GAA nanowire MOSFET as RGG =
(G size /L G )0.5 × [G size /(dNW × π)]0.5 ) is more immune to the
WFV-induced σ VTH . This is due to the larger number of
grains in the MG material suppressing the WFV-induced σ VTH
because of a higher averaging effect [3], [8].
The current flow shape of multigate devices (e.g., FinFET
and GAA nanowire MOSFET) is altered depending on device
sizes (see Fig. 3). If a device has an independent/separate
channel, VTH variation of the device can be suppressed
by ∼30% in comparison with a device with a single/bulky
channel [12]. The physical origin of the suppressed VTH
variation lies in the fact that face-to-face gates in the multigate
device (e.g., front and back gates in FinFET) mutually interact
with each other when a channel is generated, and then, newly
generated grains can increase the device’s effective gate area;
this phenomenon is known as the extended gate area (EGA)
effect [9]. Another important fact is that, if a double-gate
device has an independent channel [see Fig. 3(a) as opposed
to a single and bulky channel in Fig. 3(b) and (c)], the EGA
effect should be included in calculating the total gate area in
order to compare variability regardless of the EGA effect [12].
Otherwise [i.e., if a double-gate device has a single and bulky
channel (as shown in Fig. 3(b) and (c)], the EGA effect should
not be included in computing the total gate area. Based on
the aforementioned facts, it is expected that the RGG for
the GAA nanowire MOSFET with a dNW of 20 nm (with
a dNW of 5 and 10 nm) should (should not) include the
EGA effect. However, irrespective of the EGA effect, all
the simulation results deviated from the FinFET RGG plot
and the magnitude of σ VTH is also smaller than that of the
FinFET (see Fig. 4). In other words, for the same RGG value,
the WFV-induced σ VTH in the GAA nanowire MOSFET
is lower than that in the FinFET. Moreover, the deviation
of simulation results from the FinFET RGG plot becomes
larger as dNW is decreased. This is because the effective
average grain size (G size,eff ) around the channel region is
smaller than the original G size in the MG [see Fig. 5(a)]
[i.e., G size,eff = G size ×{(dNW /2)/(dNW /2+ TOX )}]. That is to
3340
Fig. 4. σ VTH versus RGG for three different GAA nanowire MOSFETs
with four different Gsize . It is noteworthy that all the simulation results are
deviated from the FinFET RGG plot, regardless of the consideration of the
EGA effect.
Fig. 5. Cross-sectional view along (a) A– A and (b) B–B  lines of a GAA
nanowire MOSFET with randomly sized metal grains.
say, because conventional RGG calculation uses G size (which
is larger than G size,eff ), the RGG value is overestimated,
and therefore, it leads to underestimate the WFV-induced
σ VTH . As dNW is decreased, G size,eff becomes much smaller,
resulting in more deviation. On the other hand, G size along the
channel length is equal to the original G size [see Fig. 5(b)].
Therefore, in order to accurately estimate the WFV-induced
σ VTH , the RGG calculation around the channel region in the
GAA nanowire MOSFET should consider G size,eff as follows:
RGG|GAA = (G size /L G )0.5 × [G size,eff /(dNW × π)]0.5
= G size /[L G × 2(dNW/2 + TOX ) × π]0.5 .
Without considering G size,eff , the RGG would become
(G size /L G )0.5 × [G size /(dNW × π)]0.5 , which is incorrect.
As shown in (1), the use of G size,eff indicates use of inside
area (instead of gate area) of MG when calculating the
RGG. This is because, on the contrary to the planar device,
the effective gate area for the GAA nanowire MOSFET is
quite different from the real metal area.
As shown in Fig. 6, the simulation results with G size,eff are
shifted left and exactly matched to a certain slope, because
the RGG|GAA values in the GAA nanowire MOSFET are
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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 63, NO. 8, AUGUST 2016
Fig. 6. σ VTH versus RGG with and without G size,eff for three different
GAA nanowire MOSFETs (a) dNW = 20 nm, (b) dNW = 10 nm, and
(c) dNW = 5 nm with four different Gsize for each dNW . It is noteworthy that
although G size,eff is included in RGG calculation, the WFV-induced σ VTH of
GAA nanowire MOSFET is still smaller than that in the previously validated
multigate RGG plot (i.e., FinFET RGG plot [8], [12]).
Fig. 7. Cross-sectional view of (a) cuboid-shaped and (b) cylinder-shaped
GAA nanowire MOSFETs. Both the devices have identical an RGG|GAA
value of 0.36, but the electric field for (c) cuboid-shaped and (d) cylinder-
shaped GAA nanowire MOSFETs is different. Electrostatic potential along
(e) A– A and (f) B–B  lines for 50 samples each. Red lines: electrostatic
potential of devices with metal WF profile shown in (a) and (b). In spite
of a similar WF profile, cylinder-shaped GAA nanowire MOSFET show less
electrostatic potential variation.
(1)
decreased by [1 – (G size,eff /G size )0.5 ]%. However, it should
be noted that the slope of the GAA nanowire MOSFET is
smaller than that of the FinFET. In other words, the GAA
nanowire MOSFET shows better immunity to WFV than the
FinFET. The physical reason of the suppressed WFV-induced
VTH variation would be originated from the round structure
of the GAA nanowire MOSFET. In order to elucidate the
reason, we compare the WFV-induced potential variation in
the cuboid-shaped [see Fig. 7(a)] and cylinder-shaped GAA
nanowire MOSFETs [see Fig. 7(b)], which have an identical
RGG|GAA value of 0.36. As shown in Fig. 7(c) and (d),
NAM et al.: STUDY OF WFV IN HK/MG GAA NANOWIRE MOSFET
Fig. 8. σ VTH versus RGG|GAA for (a) cuboid-shaped and (b) cylinder-
shaped GAA nanowire MOSFETs with three different values of dNW (i.e.,
dNW = 20, 10, and 5 nm) and four different Gsize for each dNW . σ VTH is
obtained from 200 samples for each case. Note that the slope of RGG plot
for the cylinder-shaped MOSFET is decreased by 12.5% compared with the
FinFET RGG plot.
electric field becomes stronger and its distribution is relatively
uniform in the cylinder-shaped GAA nanowire MOSFET
(versus cuboid-shaped GAA nanowire MOSFET), resulting in
more average effect. Therefore, even though both the devices
have identical RGG|GAA value, the magnitude of electrosta-
tic potential variation in the cylinder-shaped GAA nanowire
MOSFET is smaller than that in the cuboid-shaped case [see
Fig. 7(e) and (f)]. Moreover, the electrostatic potential in
the cylinder-shaped GAA nanowire MOSFET is gradually
varied along the B–B  direction. σ VTH values for both the
devices are plotted against RGG|GAA in Fig. 8. Whereas σ VTH
for the cuboid-shaped GAA nanowire MOSFET is exactly
matched to the previously validated FinFET RGG plot (i.e.,
slope = 120 mV), σ VTH for the cylinder-shaped GAA
nanowire MOSFET is matched to the slope of 105 mV because
of more average effect. Therefore, the WFV-induced σ VTH in
the cylinder-shaped HK/MG GAA nanowire MOSFET can be
more suppressed to 12.5%, as compared against that in the
FinFETs.
IV. C ONCLUSION
We investigated the WFV-induced σ VTH for the GAA
nanowire MOSFET by performing 3-D TCAD simulations.
It is verified that since the effective grain size (G size,eff )
around the channel region in the GAA nanowire MOSFET
is smaller than the original grain size (G size ), the RGG calcu-
lation should include G size,eff instead of G size . Finally, the
WFV-induced σ VTH in the cylinder-shaped HK/MG GAA
nanowire MOSFET is lower than that in FinFETs by 12.5%.
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Hyohyun Nam (S’12) received the B.S. and
M.S. degrees in electrical and computer engineering
from the University of Seoul, Seoul, South Korea,
in 2013 and in 2015, respectively. He is currently
pursuing the Ph.D. degree in electronics and elec-
trical engineering at Dongguk University, Seoul,
South Korea.
His current research interests include advanced
CMOS device designs and RF integrated circuits.
Youngtaek Lee (S’14) received the B.S. degree in
electrical and computer engineering from the Uni-
versity of Seoul, Seoul, South Korea, in 2015, where
he is currently pursuing the M.S. degree in electrical
engineering with the Department of Electrical and
Computer Engineering.
His current research interests include advanced
CMOS device designs and steep-switching device
designs.
Jung-Dong Park (M’15) received the B.S. degree
from Dongguk University, Seoul, South Korea,
in 1998, the M.S. degree from the Gwangju Institute
of Science and Technology, Gwangju, South Korea,
in 2000, and the Ph.D. degree in electrical engineer-
ing and computer sciences from the University of
California at Berkeley, Berkeley, CA, USA, in 2012.
Changhwan Shin (S’04–M’11) received the
B.S. degree (Hons.) in electrical engineering from
Korea University, Seoul, South Korea, in 2006, and
the Ph.D. degree in electrical engineering and com-
puter sciences from the University of California at
Berkeley, in 2011.
His current research interests include advanced
CMOS device designs and their applications to
variation-robust system on chip memory and post-
silicon technology.