Analog Integrated Circuits and Signal Processing, 6, 209-217 (1994)

© 1994 Kluwer Academic Publishers, Boston. Manufactured in The Netherlands.

Design and Applications of a CMOS Analog Multiplier Cell

Using the Differential Difference Amplifier*

SHU-CHUAN HUANG1 AND MOHAMMED ISMAIL

Department of Electrical Engineering, The Ohio State University, Columbus, Ohio 43210-1272
1 Now is an Associate Professor at the Dept. of Electrical Eng., Tatung Institute of Technology, Taipei, Taiwan, ROC

Abstract. This paper presents design techniques for a wide input range CMOS differential difference amplifier
(DDA) and discusses its application as a basic block in the implementation of a simple four-quadrant multiplier cell.
The cell can be configured as an amplitude modulator or a one-over circuit, which axe widely used in many analog
signal processing applications. The DDA can also be reconfigured as an opamp, and hence can be used to design
many of the opamp-based multiplier circuits. The DDA amplitude modulator (AM) uses a transistor and a resistor
as the only components external to the DDA. A DDA one-over circuit, which provides an output proportional to the
inverse of the input, is also achieved with the same level of simplicity. High-frequency effects due to the DDA's
finite gain-bandwidth (GB) and MOS parasitic capacitances are investigated. Experimental results obtained from a
2 #m CMOS MOSIS chip are given.

1. Introduction
The Differential Difference Amplifier (DDA) is a novel
analog building block, whose symbol is shown in fig-
ure l(a). The concept of operation is similar to that of Vpp Vo
an opamp with the output given as Vnn
Vnp
Vo :: Ao[(V,, - V , n ) - (Vn,~ - Vn~)] A o --*
(1) (a)

where Ao is the DC gain of the DDA and (Vpp - Vpn)

and (Vnp - Vnn) are the two differential voltage inputs.
Vpn; i - T ~ . ~_ • Vo
Therefore, if a negative feedback is introduced through
Vpp :
nodes Vp~ and/or V,~,, the following design equation
is obtained. Vnn : ], ] ~ " " " -Vo
Vnp -
Vpp - Vpn = Vnp - Vnn (2)
(b)
A fully-differential DDA (FDDA), shown in fig-
ure l(b), can be designed in a manner similar to a Fig. 1. Symbols of (a) DDA and (b) FDDA.
fully-differential opamp [1]. Furthermore, A DDA can
As a result, the DDA can be used to develop opamp-
be reconfigured as an opamp as shown in figure 2 [2],
based building blocks. Figure 3 shows examples of
so that
opamp-based multipliers [3, 4]. The output of circuit
Vo = 2 A o ( V , - Vn) (3) (a) is given by

* Pats of this work have been presented at the 10th Norchip Sem- (Xl - x 2 ) y
inar, Helsinki, Finland, November 3--4, 1992 and included in the Vo = z2) (4)
Seminar's proceedings, pp. 9-14. This work was supported in part
by the NSF grant MIP-8896244 and by the Semiconductor Research
Corporation contracts 90-DJ-066 and 91-DJ-066, and in part by the where (L--)l
w w
and (-L-)2 represent the sizes of tran-
Norwegian NTNF, SINTEF and Nordic VLSI. sistors in the input and feedback sides of the opamp

33
210 Huangand Ismail

Z2
,T
Vp Vo x2 i I

l Z1T l

(a)
- Vo

: -Vo
vpVn~ ~ - ~ - - - - ~ ~Ao • Vo
L r-]
--7
• -Vo -1- iz 1
X2 I
(b) I
Z2
(a)
Fig. 2. (a) Single-ended and (b) fully-differential opamps.

respectively. The output of circuit (b) is Z2

1
w) a (X1 - X2)(Y1 - Y2)
(-L-
Vo: (~)2 (~;~S (5>

In addition, the DDA can be used to develop its own set

of basic analog cells, such as an adder/subtractor, dif-
ferential integrators and multipliers/dividers [5, 6]. In Vo
this paper, we will focus on the design of DDA-based
multipliers, which are widely used in analog signal
and information processing applications such as mod-
ulation, demodulation, mixing and neural computation
[7]. In the next section, we will discuss the design of x2 I I
DDA-based circuits such as an amplitude modulator, a --F-
four-quadrant multiplier and a one-over circuit. Sim- Z1
(b)
ulation results will be provided to verify the operation
of the proposed circuits. The design of a DDA with Fig. 3. Opamp-based multiplier/divider using (a) fully-differential
a wide input range will be presented in Section 3. In and (b) single-ended opamp.
Section 4, high-frequency nonideal effects in the AM
circuit are investigated. Experimental results of the VG
DDA modulator will be given in Section 5.
T
2. Design of DDA-Based Multipliers/Modulators Vin ~ [ I • -Vin
ID
Before discussing the design of a DDA-based multi- Fig. 4. MOS transistor with its drain and source biased out of phase.
plier, we first consider a MOS transistor operating in
the linear region with its drain and source nodes biased where K = pCoxW/L and VT is the threshold volt-
out of phase as shown in figure 4. As a result, the drain age of the transistor. This configuration results in the
current is given by cancellation of the second-order term (Vi2n) such that
the input voltage (Vm) and the drain current has lin-
ID = 2~:(vc - VT)V~,~ (6) ear relationship. The transistor is therefore equiva-
lent to a grounded resistor with a resistance equal to

34
 Design and Applications of a CMOS Analog Multiplier Cell Using the Differential Difference Amplifier 211

VM+vm 5
I R
4 ~ VM=5V-
_I_ VM=4V .......
3 :......... ~ VM=3V ......

Vc ~ ~ Vo

g
-2
(a) -3 ............. d
-4
VM+vm -5 " ' ' ' ' , , , , i
I R -1 -0.8 -0.6 -0.4 -0.2 0.2 0.4 0.6 0.8

] Tll
Vc : ~ I Fig. 6.
Vc(v)
O u t p u t t r a n s f e r c u r v e s o f the m u l t i p l i e r w i t h v a r i o u s VM.
.vo
where A is a DC signal and fro(t) and coscoct are the
• -Vo modulating and carrier signals respectively, m is the
modulation index, where m < i is required for demod-
(b) ulation using an envelope detector [8]. According to
(7) and (8), one can see that vm operates as the modu-
Fig. 5. D D A - b a s e d m u l t i p l i c a t i o n / m o d u l a t i o n cell (a) s i n g l e - e n d e d
lating signal and Vc as the carrier signal. The DC signal
a n d (b) fully-differential.
A is

1/2K(Va-IIT). The inverting bias of drain and source A = - [1 + 2KR(VM - liT)] (9)
nodes can be achieved by a DDA with Vnp = Vin,
and the modulating index m is
Vpp = V~,~ = 0 and a negative feedback through node
Vp~, 'which can be verified easily using design equation 2KR
m = (lO)
(2). The output voltage of a multiplier is obtained by I + 2KR(VM - VT)
converting the resulting current into a voltage through
To satisfy the condition m < 1, we must have
a resistor as shown in figure 5. The output is obtained
as 1
/~ >
2~(y. - vr - 1)
E :: -Vc - 2KR(VM 4- Vm - VT)Vc
for VM-- VT > 1 (11)
:: - [I + 2KR(V -
(7)
1
R<
1 + 1 + 2Kt~(VM - VT) vm V~ -- 2K(VM - V T -- I)
for VM - liT < 1 (12)
where', VM + vm >_ IVc[ + VT for an NMOS transistor. On the other hand, the amplitude of 117ois limited by
Note that the above expression results in a multiplica- the output swing of the DDA used. If the maximum
tion of vm and V~. SPICE DC simulation results of output amplitude is assumed to be VDD(= --Vss),
Vo versus Vc with various VM (v,~ = 0) are shown in V~ : Vcp cos act and v~ has amplitude V M P , w e
figure 6. To be more specific, the multiplier functions have
as an amplitude modulator. Recall that an amplitude
modu!tated (AM) waveform with a sinusoidal carrier is
given by
×[1+ 1+ 2 ~ -
2KRVMp
VT)
]
VC~<_VDD
CAM(t) = A(1 + mf.~(t)) coswct (8) (13)

35
212 Huang and lsmail

Therefore, Vml I1 R
V D D / V C p -- 1
R< (14)
-- 2 I ~ ( V M -- V T -[- V M p )

Combining (11), (12) and (14), we have

gc • [ Vm2 I2 R
V D D / W c p -- 1 _2_ Vo
2 K ( V M -- l i t + VMp)
for VM-- VT > I

[ 1
R < min 2 K ( V M - VT -- 1)'
Fig. 8. T h r e s h o l d - v o l t a g e - i n d e p e n d e n t D D A - b a s e d multiplier.
VDD/Vcp-- I 1
Since R is inversely proportional to K , a small value of
J R can be used by choosing a large K value (large W)
for V M - - VT < I for the transistor. Figures 7(a) and (b) show the SPICE
(15) simulation outputs of the modulator with R = 500 ~2
and 800 f~ respectively, where W / L = 5 0 # m / 3 # m
and liT ----0.975 V for the NMOS transistor and VM =
R=500 - -
4 V. v,~ is given as a sinusoidal wave (amplitude 1V)
with frequency 1 KHz and Vc is a square wave (ampli-
2
tude 1V) with frequency 20 KHz.
A straightforward way to implement a threshold-
o
voltage-independent multiplier is to use two modula-
tion cells as shown in figure 8. The output is given
-2
as

-4
i i i
Vo = 2KR(Vr - V 2)V (16)
0 0.0005 0.001 0,0015 0.002
t (sec)
where transistors M1 and M2 are assumed matched.
One of the inputs, Vm = Vml - Vm2, and the output
are differential. If a single-ended output is desired, a
differential-to-single-ended converter is easily realized
by a DDA difference amplifier [5]. However, a sim-
4 pler implementation can be obtained using the opamp
architecture shown in figure 3(a).
2
Using the same concept, a one-over circuit, which
provides an output proportional to the inverse of the
0
input, can be achieved by the circuit shown in figure 9,
-2
where Vc and VB are bias voltages and V~n is the input
of the circuit. This circuit finds many applications, e.g.,
-4 a tracking system where the target velocity is inversely
i i i proportional to an integrated pulse width [9]. Note
0.0005 0.001 0.0015 0.002 that the FDDA is connected as a differential unity gain
t (see)
buffer [10]. As a result, the outputs are directly con-
nected to the inputs of the FDDA (high input impedance
(b) nodes), and therefore the buffer stage in the FDDA can
Fig. 7. S i m u l a t i o n results o f t h e D D A m o d u l a t o r w i t h (a) R = 5 0 0 ~ be eliminated. From (2) we have 171- 1Io = 112- (-17o)
a n d (b) R = 8 0 0 f t . which gives V1 - 172 = 21/'o. Since V1 = VB - I R and

36
 Design and Applications of a CMOS Analog Multiplier Cell Using the Differential Difference Amplifier 213

3. Design of a Wide Input Range DDA

VB :
: Vo The simplest way to implement a DDA is to make use
of an opamp design concept with an additional two-
"- - V o
- V B * transistor differential pair as the added input port [ 11 ].
However, the input operating range is limited by the
nonlinear I-V property of the differential pair. To cir-
Fig. 9. Simple one-over circuit.
cumvent this problem, one can replace the differential
pairs with wide-range linear V-I converters. The lin-
V2 = - l i b + I R , thenV1 = - ~ a n d hence V1 = Vo
ear V-I converter used in this paper is shown in fig-
and V2 = -Vo. According to (6),
ure 11 [5]. The overall DDA circuit is shown in fig-
ure 12, where M1-M10 form a cascode gain stage, and
z = 2 K ( v c + v ~ - vT)vo (17)
V DD

And since 17o = VB -- I R , the resulting output function

is proportional to the inverse of vi,~ and is given by

v~
~ sF__
F-
Vzl Vz2

Vo = (18)
[1 + 2 K R ( V G - VT)] + 2 K R v i n Vx2
Vxl Ixl
M10
IM; Ixl IM3
This circuit could also perform voltage division. I v2
SPICE simulation results are given in figure 10 with the
same NMOS transistors used in the modulator, Vc =
2'
4 V and R = 800 fL One can observe that one-over Vyl I M
the output is linearly proportional to the input.
The useful voltage range of the circuits discussed Vb3 iI
is limited by the input range of the DDA. This is due
to the fact that there is no virtual short between the
single-ended voltages Vpp and Vpn (V.p and V,~) [5]. VSS

In the following section, the design of a wide input

Fig. 11. A linear C M O S V - I converter.
range DDA will be discussed.
~ 1 and Vb2 are the bias voltages. The input operating
! , ! ! ! ! ! ! range of the DDA is therefore widened by the linear V-
I converter. A fully-differential DDA is implemented
by a DDA with a common-mode feedback circuit [1].
2.{ . . . . . :. . . . . . . :. . . . . . . : - ~ : The opamp reconfigured from a wide input range DDA
should exhibit a good performance at high frequencies,
due to its linear transconductances at the input stages.
~2
4. High-Frequency Nonideal Effects
:: i ~ v B : 2 . ~
1.6 .............. .......... •. . . . . . . . . . . . . . . . . .-
In this section, high-frequency nonideal effects such
1.4 as the finite gain-bandwidth (GB) of the DDA and the
1.2 MOS parasitic capacitances will be investigated for the
, ~ i i i _
AM circuit. To reduce the complexity of calculation,
0.1 0'.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Vin (V) these two effects will be dealt with separately in a man-
ner similar to that discussed in [12] for opamp MOS
Fig. 10. Simulation results o f the simple one-over circuit. circuits.

37
214 Huang and IsmaiI

Vdd
I
31 I~_q 711
!~ Vbl MB5 ~ [-" ~ ~ MB6
MA5 MA6 ..~1M3 I M41[('- Vo Vc
_ w

-'-]MA9, [ - ~ M5 [ M6[ =B1

MAl
-~''~
l E ~ ~--'t ~ ~i ~MA2 .~--"]l M9 MI0 ; ~ -"4
I"~.MB3 ~}~MB4
MB2
1 MA,0~ " ] / MBI0[

All MA12 1 MBII MB12

vss
Fig. 12. ACMOSwideinputrangeDDAcircuit.
Finite GB Effect
I1o = Vp,~ - I R
If the finite GB effect of the DDA is taken into ac-
count in the AM circuit, nonlinearities are introduced
in the transistor current I, since the DDA inverter is now (
frequency-dependent. Assume the open-loop gain of
the DDA is modeled by A ( s ) = G B / s . According to
(2), we have
]
~) 2 G~--L-Vo
+ (Va - l i t + B ] (22)

which gives
17o = G B ( - v p n - Vc) (19)
8
Vo = -[1 + 2 K R ( V a - VT)]V¢ x CaB(S) (23)
i.e.,
where eGB(s) is an error function resulting from the
S GB effect and is given by
G,~ = - y c - ~-dVo (20)
1
Note that Vpn is no longer equal to - V c . The current CUB(S) = 1 + ~B[1 + K R ( V G - VT + Vc)] (24)
I is therefore given by
It results in a phase lag, 0, written as

I = K
[
(VG - gT)(Yc
1
- Y p n ) -- - ~ ( Y ) - yp2n)
] tO
0 = tan -1 ~-~ [1 + K R ( V a - VT + Vc)] (25)

[ ,q which may degrade the high-frequency performance.

A I.d-IJI~
Magnitude errors leaB(jto)[ ( ~ 1 - [1 + K R ( V G -
I
V T q- V,C/J
~122 G~2B 2 a] are of second-order and can be ne-
glected.
s2 K 2] (21)
+ 4GB 2 o j

whereVa = VM + v ~ . T h e s a n d s 2 terms in the M O S Parasitic Effects

above equation result from the GB effect. Moreover,
Vo2 in s 2 term would introduce second-order harmonic At high frequencies, a MOS transistor operating in the
component in I. Fortunately, since the frequency range triode region can be modeled as shown in figure 13,
of interest is much smaller than G B , the s 2 term can where R c is the small signal MOS resistance given by
be neglected in the calculation. The output voltage is 1
written as R a -- K ( V a - I77) (26)

38
 Design and Applications of a CMOS Analog Multiplier Cell Using the Differential Difference Amplifier 215

RG Therefore, the equivalent resistance R~q is

I1 12
VI: /- ~ :V2
=
1
t[
1
-
Rc
2 x eT(S) (30)

Tca TCp where the error function er(s) is given by

~s+l
Fig. 13. Small-signal high-frequency model of a MOS transistor eT(S) = RaC.r~2 (ncC~ (31)
operating in the triode region. 12 ~ +~ 2 +~)s+l
Again, the s 2 term in the denominator is practically
1/Y Req small and is negligible, and eT(s) is approximated by

I1 RG i2 I I = vw ~s + 1 (32)
w .--~--.-v~ .~ J, r T(8) = + + i
-- Vo
whose magnitude and phase are obtained as

Fig. 14. AM circuit with a MOS small-signal high-frequency model.

leT(jco)l i 1+ i + + i)2032

Ca and G% are extrinsic capacitances and Cp represents 037 - t a n - 1 w ( _ ~

/eT(jW) = tan -1 ---6- + 4)
the distributed capacitances in the channel, which are
modeled as a uniform RC transmission line. The first (33)
order y parameters of the transmission line are given The distributed effect reduces the equivalent resistance
by [12] of the transistor slightly, and introduces small phase
8T
lag. The output voltage is written as
-E+I
Yll : Y22 ~
R c ( ~ + 1) Vo = -lie - I R
(27)
-1 = -V~[1 + 2 K R ( V a - VT)/eT(S)] (34)
Y12 : Y21 ~
Ro(-~- + 1)
5. Experimental Results
where 7- = RCCp and Cp = Co~WL. Using the
model, the AM circuit is redrawn in figure 14. Note The DDA proposed in Section 3 was fabricated in a
that the extrinsic capacitance Ca is eliminated in the 2 #m P-well MOSIS CMOS process. A common cen-
figure, since it is driven by a voltage source Vc. Using troid layout technique was used to improve the match-
the admittance parameters, we may write the following ing of the devices incorporated in the input stages; Fig-
equation. ure 15 shows the measurement of Vo with Vm (100 Hz
and amplitude 1 V), V~ (not shown with 1 KHz and
amplitude 1 V) and R = 220 fL The transistor in the
circuit is built by a series combination of 2 SK9160 de-
pletion transistors (which have their sources connected
The equivalent admittance, Y, is therefore given by to the bulks) with their gates and sources connected
respectively and their drains being the new drain and
y --
fi I2 source of the composite transistor. This implementa-
E -V~ tion reduces the body effect of the transistors. The
depletion mode transistors were chosen to simplify the
= Yll -- Y I 2 = Y22 -- Y 2 1 experiments since they are normally on (no DC com-
ponent, VM, is required). It can be seen from figure 15
~-sr4_ 2
2
(29) that the envelope of the output is proportional to the
R G ( • 4- I) modulating signal Yr,.

39
216 Huang and Ismail

~£, running

iI ii °...... .....................
. . . . . . .'.....................
. . . . . . . .........i.....................
.I........... .......................................
i! ..... .................. 0fss00
1,o00 vJv35o0v
.........................
ii : : ~

.......
11 I . . . .

4" 500 IrN/d i v

i of f s e t ' , - 3 5 , 0 0 mV
! ................................
i.............. i } ,,ooo , 1 ac
i .............. : ................... a ................... : ................... iii~...................................................................................................
i i

-10.0000 ms 0,30000 s 10.0000 ms

2,00 ms/dlv
Fig. 15. Experimental results of the DDA modulation cell.

6. Conclusions 4. Khachab, N. I. and Ismail, M., "A nonlinear CMOS analog cell
for VLSI signal and information processing," IEEE J. Solid-
The design of a wide input range DDA and a simple State Circuits, Vol. 26, pp. 1689-1699, Nov. 1991.
5. Huang, S.-C., Ismail, M. and Zarabadi, S. R., "A wide range dif-
DDA-based multiplier cell have been discussed, and ferential difference amplifier: A basic block for analog signal
experimental results are given. A DDA can be recon- procerssing in MOS technology," IEEE Trans. Circuits Syst. -
figured as an opamp to make use of opamp-based build- II, Vol. 40, pp. 289-301, May 1993.
6. Ismall, M., Huang, S.-C. and Sakurai, S., "Continuous-time
ing cells. In addition, simple AM and one-over circuits
signal processing," in Analog VLSI: Signal and Information
are developed by reconfiguring the basic multiplier cell Processing, edited by M. Ismail and T. Fiez, ch. 3, McGraw-
and taking advantage of the differential input prop- Hill, 1994.
erty of the DDA. This demonstrates that the DDA is 7. Mead, C. and Ismail, M.,Analog VLSllmplementation of Neu-
ral Systems. Kluwer, 1989.
a competitive building block to opamps in many signal 8. Stremler, E G., Introduction to Communication Systems.
processing applications. All-MOS implementations of Addison-Wesley, 1982.
the circuits discussed in this paper are easily achieved 9. Etienne-Cummings, R., Hathaway, R. and Van der Spiegel,
by replacing resistors with all-MOS voltage-controlled J., "Accurate and simple CMOS 'one-over' circuit," Electron.
Lett., Vol. 29, pp. 1618-1620, Sept. 1993.
floating resistors, e.g. see [13]. The voltage-controlled 10. de la Plaza, A. and Morlon, P., "Power-supply rejection in dif-
resistors wilt provide electronic programmability of the ferential switched-capacitor filters" IEEE J. Solid-State Cir-
output voltage. cuits, Vol. SC-19, pp. 912-918, Dec. 1984.
11. Sackinger, E. and Guggenbuhl, W., "A versatile building block:
the CMOS differential difference amplifier," IEEE J. Solid-
State Circuits, Vol. SC-22, pp. 287-294, April 1987.
References 12. Khachab, N. I. and Ismall, M., "Linearization techniques for
nth-order sensor models in MOS VLSI technology," IEEE
1. Huang, S.-C. and Ismail, M., "A CMOS differential differ- Trans. Circuits Syst., Vol. 38, pp. 1439-1450, Dec. 1991.
ence amplifier with rail-to-rail fully-differential outputs" (to 13. Sakurai, S. and Ismail, M., "A CMOS square-law pro-
be published). grammable floating resistor independent of the threshold volt-
2. Zarabadi, S. R., Larsen, E and Ismail, M., "A configurable age," IEEE Trans. Circuits Syst., Vol. 39, pp. 565-574, Aug.
op-amp/DDA CMOS amplifier architecture," IEEE Trans. Cir- 1992.
cuits Syst., Vol. 39, pp. 484-487, June 1992.
3. Khachab, N. I. and Ismail, M., "MOS multiplier/divider cell
for analogue VLSI," Electron. Lett., Vol. 25, pp. 1550-1551,
Nov. 1989.

40
 Design and Applications of a C M O S Analog Multiplier Cell Using the Differential Difference Amplifier
Shu-Chuan Huang was born in Taipei, Taiwan, in 1965.
She received the B.S. degree from National Central Univer-
sity, Taiwan, in 1987 and the M.S. degree from the Ohio State
University, Columbus, in 1990, both in electrical engineer-
ing. She is currently a Ph.D. student of electrical engineer-
ing and a Research Assistant at the Ohio State University,
Columbus. Her research interests are in the area of analog
integrated circuit analysis and design. She was employed by
Tatung Institute of Technology, Taiwan, as a teaching assis-
tant,. 1987-1988, and received a scholarship from the institute
whi~e at the Ohio State University.
Mohammed Ismail is a professor in the Department of Elec-
trical engineering at The Ohio State University (OSU). Previ-
217
ously, he held several positions in both industry and academia
and has served as a corporate consultant to nearly 20 compa-
nies in the U.S. and abroad. In 1985, Dr. Ismail received the
NSF Presidential Young Investigator Award, and in 1993, the
OSU Lumley Research Award in recognition of outstanding
research accomplishments. In 1984, he received the IEEE
Outstanding Teacher Award at the University of Nebraska.
Dr. Ismail is the founder of the Int. J. Analog Integrated Cir-
cuits and Signal Processing and currently serves as the Jour-
nal's Editor-in-Chief (N. America). He has been the Circuits
and Systems Society Editor of the 1EEE Circuits and De-
vices Magazine since 1991 and was the Chairman of the So-
ciety's Tech. Committee on Analog Signal Processing from
1987-1990. He also served as Associate Editor of the IEEE
Transactions on Circuits and Systems ( 1989-199 l) and of the
IEEE Transactions on Neural Networks (1992-1994). He is
the author of about 100 publications on VLSI circuit design
and signal processing and was awarded several patents in the
area of analog VLSI. He co-edited and co-authored Analog
VLSI Implementation of Neural Systems (1989), Introduc-
tion to Analog VLSI Design Automation (1990), Statistical
Modeling for Computer-Aided Design of MOS VLSI Circuits
(1993) and Analog VLSI: Signal and Information Processing
(1994). He received his Ph.D. in electrical engineering from
the University of Manitoba in 1983.
41