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15 September 2022 1444 ‫ صفر‬19

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Analog IC Design

Lecture 21
Slew Rate (SR) and Power Supply Rejection (PSR)

Dr. Hesham A. Omran

Integrated Circuits Laboratory (ICL)
Electronics and Communications Eng. Dept.
Faculty of Engineering
Ain Shams University
 Outline
❑ Linear and non-linear settling
❑ SR examples
❑ Power supply rejection
❑ PSRR examples

21: SR and PSR 2

 Outline
❑ Linear and non-linear settling
❑ SR examples
❑ Power supply rejection
❑ PSRR examples

21: SR and PSR 3

 Linear System
❑ One important property of linear systems: doubling the input doubles the output
▪ More generally: scaling the input scales the output

R
Vin Vout

Vin t t
Vout
CL

21: SR and PSR 4

 Linear Settling
❑ The system time constant 𝜏 do not depend on the input level
▪ Need to settle to a higher voltage in the same time
▪ Need larger slope
▪ Need higher current!
❑ For linear systems: doubling the input doubles the output
▪ The slope is also doubled!
❑ Linear settling: Scaling the input scales the output slope

Vin
Vout
CL
t t
21: SR and PSR 5
 Linear Settling
❑ Linear settling: Output slope and charging current ∝ input
𝑡
−𝜏
𝑉𝑜𝑢𝑡 = 𝑉𝑠𝑡𝑒𝑝 1 −𝑒
𝑑𝑉𝑜𝑢𝑡 1 −𝑡 𝑑𝑉𝑜𝑢𝑡
= 𝑉𝑠𝑡𝑒𝑝 𝑒 𝜏 → ∝ 𝑉𝑠𝑡𝑒𝑝
𝑑𝑡 𝜏 𝑑𝑡
𝑑𝑉𝑜𝑢𝑡
𝐼𝑜𝑢𝑡 = 𝐶𝐿 → 𝐼𝑜𝑢𝑡 ∝ 𝑉𝑠𝑡𝑒𝑝
𝑑𝑡

Vin
Vout
CL
t t
21: SR and PSR 6
 Non-linear Settling: Slewing
❑ Non-linear settling: Output slope and current NOT ∝ input
▪ Output is linear ramp → finite constant slope
❑ Slew Rate (SR): the maximum possible slope of the op-amp output
❑ Linear ramp → constant current charging a capacitor
𝑑𝑉𝑜𝑢𝑡 𝑑𝑉𝑜𝑢𝑡 𝐼𝑜𝑢𝑡,𝑚𝑎𝑥
𝐼𝑜𝑢𝑡 = 𝐶𝐿 → 𝑆𝑅 = = = 𝑐𝑜𝑛𝑠𝑡.
𝑑𝑡 𝑑𝑡 𝑚𝑎𝑥
𝐶𝐿
❑ Slope independent of the input level → non-linear behavior

Vin
Vout
CL
t

21: SR and PSR 7

 Small Input Step: Linear Settling
❑ Linear settling: Output slope and charging current ∝ input
❑ Output voltage has exponential settling behavior
❑ When the output settles → Δ𝑉𝑖𝑑 = 𝑉𝑖𝑛 − 𝑉𝑜𝑢𝑡 ≈ 0

M3 M4
Iout = gmΔVid
Vout
CL
Vin M1 M2

t
ISS

21: SR and PSR 8

 Large Input Step: Slewing
❑ M2 OFF, 𝐼𝑆𝑆 is fully steered to M1 → M3 → M4 then to 𝐶𝐿
❑ Nonlinear settling: output slope and charging current NOT ∝ input
▪ Linear ramp → constant current 𝐼𝑆𝑆 charging a capacitor
❑ As 𝑉𝑜𝑢𝑡 approaches 𝑉𝑖𝑛 the circuit resumes linear settling (exp)
𝐼𝑆𝑆
❑ 𝑆𝑅 =
𝐶𝐿

❑ Efficiency ~ 100%
M3 M4
ISS Iout = ISS
ISS Vout
CL
Vin M1 M2

t
ISS

21: SR and PSR 9

 Outline
❑ Linear and non-linear settling
❑ SR examples
❑ Power supply rejection
❑ PSRR examples

21: SR and PSR 10

 SR of FD OTA
𝐼𝑆𝑆
❑ 𝑉𝑜𝑢𝑡− : 𝑆𝑅 = /𝐶𝐿
2
𝐼𝑆𝑆
❑ 𝑉𝑜𝑢𝑡+ : 𝑆𝑅 = /𝐶𝐿
2
❑ 𝑉𝑜𝑢𝑡𝑑 = 𝑉𝑜𝑢𝑡+ − 𝑉𝑜𝑢𝑡− : 𝑆𝑅 = 𝐼𝑆𝑆 /𝐶𝐿
❑ Symmetrical slewing → Necessary to maintain constant CM level

VB M3
M4
Iout = ISS/2 ISS/2 ISS/2 Iout = ISS/2
Vout- Vout+
ISS
CL CL
Vin+ M1 M2 Vin-

ISS

21: SR and PSR 11

 SR of Telescopic Cascode
𝐼𝑆𝑆
❑ 𝑆𝑅 =
𝐶𝐿

❑ Efficiency ~ 100%

M7 M8
M5
VB2 M6
ISS Iout = ISS
VM Vout
ISS
M3 CL
VB1 M4

Vin M1 M2
t
ISS

21: SR and PSR 12

 SR of Folded Cascode
❑ At equilibrium: Usually set 𝐼𝐷𝑄,𝐶𝑆 = 𝐼𝐷𝑄,𝐶𝐺 → 𝐼𝐵1 = 𝐼𝐵2
❑ At slewing: 𝐼𝐵2 → 𝐼𝐵2 − 𝐼𝐵1 ≈ 0
❑ 𝑆𝑅 = 𝐼𝑆𝑆 /𝐶𝐿
❑ Efficiency ≈ 50%
IB2 IB2
M5a M5b

ISS =
Vcascp M4a M4b Vcascp
2IB1
IB2 – IB1 Iout = ISS
IB2 – IB1 Vout
Vin M1a,b CL
Vcascn M3a M3b Vcascn
ISS
t
Vbiasn M2a M2b Vbiasn
IB1 + IB2 IB1 + IB2

21: SR and PSR 13

 SR of Two-Stage Miller OTA
❑ 𝐼𝐵2 is usually much larger than 𝐼𝐵1
M3 M4 ID6
▪ SR usually limited by 𝐼𝐵1
M6
❑ Internal slewing limits output slewing IB1 IB1
ID6 - IB1 - IB2
M1 M2 Vin C Vout
❑ Positive slewing C
CL
𝐼𝐷6 − 𝐼𝐵1 − 𝐼𝐵2 𝐼𝐵1 IB1 IB2
> M5
𝐶𝐿 𝐶1 + 𝐶𝐶 VB M7

𝐼𝐵1
𝑆𝑅+ ≈
𝐶1 + 𝐶𝐶
❑ Negative slewing M3 M4 ID6
IB1
𝐼𝐵2 − 𝐼𝐵1 𝐼𝐵1 IB1 IB1
M6
> IB2 - IB1 - ID6
𝐶𝐿 𝐶1 + 𝐶𝐶 M1 M2 Vin C Vout
C
𝐼𝐵1 CL
𝑆𝑅− ≈ IB1 IB2
𝐶1 + 𝐶𝐶 M5
VB M7
21: SR and PSR 14
 SR of Fully-Differential Miller OTA
❑ Must design the circuit such that 𝑆𝑅+ = 𝑆𝑅−
▪ Both should be limited by 𝐼𝐵1
❑ Otherwise the slewing is asymmetric
▪ Causes a shift in CM output
▪ Slow transients if the CMFB network is slow

21: SR and PSR 15

 Outline
❑ Linear and non-linear settling
❑ SR examples
❑ Power supply rejection
❑ PSRR examples

21: SR and PSR 16

 Power Supply Rejection (PSR)
❑ Supply lines carry noise from regulators, digital loads, etc.
❑ We don’t want 𝑉𝑜𝑢𝑡 to be affected by 𝑉𝐷𝐷 noise
1
𝑃𝑆𝑅 =
𝑣𝑜𝑢𝑡 /𝑣𝐷𝐷
𝑣𝑜𝑢𝑡 /𝑣𝑖𝑛
𝑃𝑆𝑅𝑅 = = 𝐴𝑣𝑑 ⋅ 𝑃𝑆𝑅
𝑣𝑜𝑢𝑡 /𝑣𝐷𝐷
❑ Both PSR and PSRR usually reported in dB

VDD

Vin Vout

21: SR and PSR 17

 Power Supply Rejection Ratio (PSRR)
❑ The diode-connected device “clamps” 𝑉𝑀 to VDD
❑ 𝑉𝑀 and 𝑉𝑜𝑢𝑡 experience approximately the same change as VDD
1
𝑃𝑆𝑅 = ≈1
𝑣𝑜𝑢𝑡 /𝑣𝑑𝑑
𝑣𝑜𝑢𝑡 /𝑣𝑖𝑛 𝑔𝑚1,2 𝑟𝑜2 ||𝑟𝑜4
𝑃𝑆𝑅𝑅 = = 𝐴𝑣𝑑 ⋅ 𝑃𝑆𝑅 ≈
𝑣𝑜𝑢𝑡 /𝑣𝑑𝑑 1

M3 M4
VM Vout
Vin+ M1 M2 Vin-

VB M5
21: SR and PSR 18
 Outline
❑ Linear and non-linear settling
❑ SR examples
❑ Power supply rejection
❑ PSRR examples

21: SR and PSR 19

 Quiz: PSRR of 5T OTA
❑ Derive the PSRR for a 5T OTA with PMOS input pair
▪ Assume the tail current source is generated by a simple current mirror
❑ What is the relation between the PSRR you derived and the CMRR?

21: SR and PSR 20

 Quiz: PSRR of Complementary CS
❑ Find the PSRR of the complementary CS amplifier (inverter-based amplifier)
𝑣𝑜𝑢𝑡 /𝑣𝑖𝑛
𝑃𝑆𝑅𝑅 =
𝑣𝑜𝑢𝑡 /𝑣𝑑𝑑
❑ Very poor PSRR!

M2
Vin Vout
M1

21: SR and PSR 21

 Quiz: PSRR of CS with Active Load
❑ Assume all transistors have the same 𝑔𝑚 and 𝑟𝑜
❑ Note: The gate of the active load is NOT ac ground

M2
Vout
Vin M1

21: SR and PSR 22

 PSRR: SE Output vs Fully Differential
❑ In both cases Δ𝑉𝐷𝐷 gets transferred to the output
▪ But for the fully diff amp, the differential output is not affected

M3 M4 VB
VM Vout Vout- Vout+
Vin+ M1 M2 Vin- Vin+ Vin-

ISS ISS

21: SR and PSR 23

 Thank you!

21: SR and PSR 24

 Folded Cascode Slewing (IB1 < IB2)
❑ The slewing is always symmetrical independent of the speed of the CMFB network.
▪ This is an advantage for driving slightly more current in the output branch.
IB1 < IB2
IB2 IB2
Vbiasp M5a M5b Vbiasp
Vcmfb M6
Vcascp M4a M4b Vcascp
2IB1
IB1 IB1
Voutp Voutn
IB2-IB1 Vinn M1a,b Vinp IB1+IB2
CL CL
M3a M3b
Vcascn 2IB1 Vcascn

Vbiasn M2a M2b Vbiasn

IB1+IB2 IB1+IB2

21: SR and PSR 25

 Folded Cascode Slewing (IB1 > IB2)
❑ Assume a fast CMFB network that forces a constant CM (symmetrical slewing).

IB1 > IB2

IB2 IB2
Vbiasp M5a M5b Vbiasp
Vcmfb M6
Vcascp M4a M4b Vcascp
IB1+IB2
IB2 IB2
Voutp Voutn
0 Vinn Vinp 2IB2
CL M1a,b CL
M3a M3b
Vcascn IB1+IB2 Vcascn

Vbiasn M2a M2b Vbiasn

IB1+IB2 2IB2

21: SR and PSR 26

 Folded Cascode Slewing (IB1 > IB2)
❑ Assume a slow CMFB network (non-symmetrical slewing).

IB1 > IB2

IB2 IB2
Vbiasp M5a M5b Vbiasp
Vcmfb M6
Vcascp M4a M4b Vcascp
IB1+IB2
IB2 IB1
Voutp Voutn
0 Vinn M1a,b Vinp IB1+IB2
CL CL
M3a M3b
Vcascn IB1+IB2 Vcascn

Vbiasn M2a M2b Vbiasn

IB1+IB2 IB1+IB2

21: SR and PSR 27