Session - 5 - Routing and Stack Up

Session 5
Routing and Stack up
Session Speaker:
Dr. Ugra Mohan Roy
mohanroy.ec.et@msruas.ac.in
1
Faculty of Engineering & Technology © Ramaiah University of Applied Sciences
Session Objectives
• At the end of this session, student will be able to

– Explain PCB stack ups, its advantages and disadvantages
– Discuss main issues in high speed board routing
– Analyze development of best topologies and better termination
techniques to overcome issues on high speed boards
2
Session Topics:
• Main issues for routing

– Routing topologies
– Rise and fall time degradation
– Signal Skew
– Line Termination
• Power distribution and de-coupling
• PCB Stackup
• Return Path Discontinuities
3
Main Issues for Routing:
• Routing topologies and loading

• Impedance
• Rise and fall time degradation
• Signal Skew (Signal delay difference)
• Crosstalk
• Termination
• Signal return path
4
Point to Point Topology:
• This is the ideal topology but not very efficient in that it

requires a lot of extra buffers.
• Always use this topology for critical clock trees.
• Use low skew clock buffers
• Skew can be compensated with delay lines
5
Fan / Star Topology
• This topology is routing efficient but put heavy load on the

driver, especially where several lines fan out.
• Use drivers with low output impedance.
• Terminate properly at each receiver or reflections will
propagate back and forth in the net.
• Be careful with the high power consumption of many
terminated lines
6
T - Topology
• This split will cause a 33% negative reflection if all lines are of
same impedance.
• All ends (also driver) should be terminated properly for larger nets
• The driver will have to drive twice the amount of DC into the
termination resistors.
7
Daisy Chain
• The preferred topology for high speed digital.

• Terminate in both ends.
• Allow no stubs
• Keep tap load low.
• Keep distance between loads so high that the signal can recover.
8
Rise And Fall Time Degradation
• Any lossy transmission line acts as a filter which filters the high
frequency components first.
• Since the high frequency components is damped more the signal will
show slower rise times at the end of the line.
9
Signal skew
• Signal skew is the delay difference at inputs.
• Keeping low signal skew in a clock system is a challenge and
there are several consideration.
– Keep every signal trace equally long
– Use low skew drivers
– Rise time degradation may pose a problem in calculated delay
daisy chains.
– Signals travel faster at outer layers, so trace lengths must be
compensated. Or - use only inner layers.
– Poor decoupling influence rise time.
– Use only first incident clocking or better, reduce reflections to
zero.
10
Signal Return Path
• The high frequency signals follow a mirror image of the trace on
the ground plane.
• Do not degrade this return by:
– Changing to layers which have another ground-plane without

placing a ground-ground via close to the signal via. If the new
reference plane is a power plane a low inductance decoupling
is placed close to the signal via
– Using split reference planes.
– Using one small via for several returns, this may cause
common mode problems.
11
How To Design Delay Lines
• Remember loss
• Use meander structure, be careful to avoid inductor effects.
• Keep meander lines at least 4 times the distance to ground plane
apart to avoid distortion.
• Preferably use inner layers, this reduce distortion and keep
inductance low.
12
Line Termination
13
Driven Line And Its Reflection Coefficients
Z  90
0
Z S  30 Z L  1500
30  90 1550  90
s   0.8 l   0 .9
30  90 1550  90
14
Different Types Of Termination
• Series Termination – Resistor on driver side. Resistor value
depends on driver output impedance and line wave impedance.
• Thevenin termination – Uses two resistors at the end of the line.

Very much like a parallel termination but much better at
terminating lines at 50 Ohm and below.
• Parallel termination – single resistor at end of line. Resistor value

depend on line impedance and acts as in parallel with input
impedance of receiver.
15
Why Terminate The Signals
• Termination is a method to match the driver line and receiver in
such way that no reflections are generated.
• Generally the ideal would be to do a parallel termination in the
line impedance
• Terminate critical lines that are longer than 1/3 of the rise time.
On FR-4 this mean that a 1ns rise signal, the longest
unterminated line is 5cm.
• Reflections can cause double triggering, if using non- terminated
nets do not use data before the reflections have settled.
16
Series Termination
• Used to match driver impedance

• Slow rise and fall times (Some times good, for instance to
achieve low crosstalk)
• Absorb reflections if matched to line
17
Series Termination
• Series Termination:
– A termination is placed near the source.
– The value of the termination
Rt = Xline.impedance(Zo)-Source output Impedance(Ro)
– The advantage of using this termination is that it occupies only small

space of the board real estate.
– It could be also added within the chip.
– The disadvantage is that it loads the signal .
18
What Happens To Reflections When You Put
A Series Termination
• Series termination is always a compromise for CMOS drivers as the

output impedance is not the same when the driver is pulling up or
down. This is because the NMOS and PMOS in output buffer are not
balanced.
19
Parallel Termination
• The termination of choice for high speed digital, especially for

ECL, PECL and other technologies intended for termination.
• High power consumption.
• 100% clean signals possible
20
Parallel Termination
• Parallel Termination:
– It is placing a termination with value of the transmission
impedance at the far end of the line.
– A Thevenin equivalent could be used yet it can take more

space and loads the signal further.
– The disadvantage of this termination is its power dissipation .
21
Thevenin Termination
• Ideal for bus termination or lines with 3-State drivers.

• 330 Ohm & 220 Ohm is often used.
• Faster switching from 3-state
• Does NOT correctly terminate the line, reflections will occur
22
DC Thevenin Termination- Design Example
Vdd
R1 || R 2  Z 0 Gnd
Vcc Vcc
R1  Z 0 R2  Z 0
VT Vcc  VT
R2
VT  VCC
R1  R 2
• R1 , R2 provides a DC path at the termination hence there is an

additional Dc power consumption.
• The second criteria is the Maximum current sunk by driver must be
able to drive the receiver when the output voltage is a 1( high).
23
Current Driving Requirements For Thevenin
Termination
(VCC  VOH ) (VOH )

  I OH ,max
R1 R2
(VCC  VOL ) (VoL )
  I OL ,max
R1 R2
R1 150 165 160 Zl=74.25
R2 150 135 130
Iohl -0.1 -26mA
Ioll 16.67 19mA
24
AC Termination
• AC or RC termination, better for technologies not intended for

termination.
• Low power consumption (No DC consumption)
• Be careful with inductive capacitors, select capacitors with care.
25
AC Termination – Thevenin without DC current
The two series capacitors allow the effectiveness of the Thevenin Termination without the
DC current flow. The two capacitors act as DC blocks.
This is also called a AC Thevenin termination. The capacitor value can be computed using
the criteria that it should act as a DC cutoff.
Xc > 3Tr/Z0 .
Larger capacitor values can lead to higher power consumption at higher operating
frequencies
26
Capacitance Calculation for AC Termination
• Inputs – Rise time, Line Impedance.
• Outputs – Capacitance
12
Tr 400 *10 1200 12
Xc  3 3  10
Z0 75 75
12 1
X c  16 *10  16 *10 12
2fC
C  16 *10 12 * 2 * 400 *10 6  40212 *10 6
C  0.04 F
27
AC Termination
• AC Termination:
– It is placing a termination at the far end in series with a
capacitor.
– Certainly the advantage of the termination would be having
more output power which would could unfortunately lead to
poorer signal integrity
• Advantages
– Active Termination consume less power.
– Diodes could be used to limit Overshoot and Undershoot.
– It takes less space and could be incorporated within the chip.
28
Diode Termination
• Kills large over and undershoot

• Not generally useful in high-speed systems. (A design needing
this type of termination have probably greater problems
elsewhere)
29
Active Termination Via ICs
Active
termination
IC
• Typically implemented as on–board SMTs. One terminator will terminate a minimum

number of lines – say 16.
• More expensive that resistors but with volume production terminator costs are less
than 1 cent.
• The impedance and sunk current is programmable hence we have better control of
power dissipation.
30
Examples Of Termination Waveforms – Thevenin Vs
Series Vs AC.
SERIES THEVENIN AC PARALLEL

TERMINATION TERMINATION TERMINATION
31
Differential Trace Termination
• Differential lines also require a termination resistor if the line

length exceeds the data rate
• The termination is placed at the destination
• To reduce the current consumption AC termination may be used
• The termination resistor [R] is selected to match the trace
impedance [Zo]
• while the capacitor is selected by: Xc = [3 * Tr] / Zo.
32
PCB Stack Up
34
General Aspects On Stack-up
• PCB stack-up is an important factor in determining the EMC

performance of a product.
• A good stack-up can be very effective in reducing radiation from
the loops on the PCB (differential-mode emission), as well as the
cables attached to the board (common-mode emission).
• A poor stack-up can increase the radiation from both of these
mechanisms considerably.
35
Board Stack-up
• Four factors are important with respect to board stack-up considerations:
– The number of layers,
– The number and types of planes (power and/or ground) used,
– The ordering or sequence of the layers, and
– The spacing between the layers.
• In deciding on the number of layers, the following should be considered:
– The number of signals to be routed and cost
– Frequency
– Will the product have to meet Class A or Class B emission requirements
– Will the PCB be in a shielded or unshielded enclosure
– The EMC engineering expertise of the design team.
36
Board Stack-up (Cont…)
• Multi-layer boards using ground and/or power planes provide significant reduction in radiated
emission over two layer PCBs.
– They allow signals to be routed in a microstrip (or stripline) configuration.
– These configurations are controlled impedance transmission lines with much less
radiation than the random traces used on a two-layer board.
– The ground plane decreases the ground impedance (and therefore the ground noise)
significantly.
• Five objectives on Multi-layer Board
1. A signal layer should always be adjacent to a plane
2. Signal layers should be tightly coupled (close) to their adjacent planes.
3. Power and Ground planes should be closely coupled together.
4. High-speed signals should be routed on buried layers located between planes.
 In this way the planes can act as shields and contain the radiation from the high-
speed traces.
5. Multiple ground planes are very advantageous, since they will lower the ground (reference
plane) impedance of the board and reduce the common-mode radiation.
37
Four-Layer Boards
 The most common four-layer board configuration is as below
_____________ Sig.
_____________ Ground
_____________ Power
_____________ Sig.
 The advantages of tight coupling between the signal (trace) layers and the
current return planes will more than outweigh the disadvantage caused by the
slight loss in interplane capacitance
 Layers are equally spaced
 Large separation between the signal layer and the current return plane
 Large separation between the power and ground planes
 Not sufficient inter-plane capacitance between the adjacent power and ground
planes
 Decoupling will have to be taken care
 Opt for tight coupling between the signal and the current return plane
38
Four-Layer Boards (cont..)
• To improve the EMC performance of a four-layer board is to space the signal
layers as close to the planes as possible (<0.010"), and use a large core (>0.040")
between the power and ground planes
_____________ Sig.
_____________ Ground
_____________ Power
_____________ Sig.
• Advantages
– The signal loop areas are smaller and therefore produce less differential mode
radiation
– the tight coupling between the signal trace and the ground plane reduces the
plane impedance (inductance)
– the close trace to plane coupling will decrease the crosstalk between traces
• Disadvantage
– For a fixed trace to trace spacing the crosstalk is proportional to the square of
the trace height.
39
_____________ Ground.
_____________ Sig.
_____________ Sig.
_____________ Power
• Advantage
 The planes on the outer layers provide shielding to the signal traces on the inner layers
• Disadvantage
 The ground plane may be cut-up considerably with component mounting pads on a high
density PCB
 an exposed power plane
 the buried signal layers make board rework difficult if not impossible
40
_____________ Ground.
_____________ Sig./Pwr.
_____________ Sig./Pwr.
_____________ Ground
• Two outer planes are ground planes and power is routed as a trace on the
signal planes. The power should be routed as a grid, using wide traces, on the
signal layers
• Advantages
 The two ground planes produce a much lower ground impedance and
hence less common-mode cable radiation
 The two ground planes can be stitched together around the periphery of
the board to enclose all the signal traces in a faraday cage
41
_____________ Sig./Pwr.
_____________ Ground
_____________ Ground
_____________ Sig./Pwr.
• Advantages
 Still provides for the low ground impedance as a result of two ground
planes
• Disadvantage
 The planes however do not provide any shielding
This configuration satisfies objectives (1), (2), and (5) but not objectives (3) or (4).
42
Possible Combination of 4 Layer Stack-up
43
Six-Layer Boards
• Most six-layer boards consist of four signal routing layers and two
planes.
________________Signal
________________Signal
________________Ground
________________Power
________________Signal
________________Signal
• One stack-up NOT to use on a six-layer board is the one shown in

the above figure. Why? Cont…
44
Why?
• The planes provide no shielding for the signal layers,
• and two of the signal layers (1 and 6) are not adjacent to a
plane.
• The only time this arrangement works even moderately well is if
all the high frequency signals are routed on layers 2 and 5 and
only very low frequency signals, or better yet no signals at all
(just mounting pads), are routed on layers 1 and 6.
• If used, any unused area on layers 1 and 6 should be provided
with "ground fill" and tied into the primary ground plane, with
vias, at as many locations as possible.
45
Six-Layer Boards (cont…)
• With six layers available the principle of providing two buried layers for high-
speed signals is easily implemented as shown
________________Mounting Pads/Low Freq. Signals
________________Ground
________________High Freq. Signals
________________High Freq. Signals
________________Power
________________Low Freq. Signals
• This configuration also provides two surface layers for routing low speed
signals.
• Satisfies objectives 1, 2, & 4 but not objectives 3 & 5
• Disadvantages
– main drawback is the separation of the power and ground planes
– Due to this separation there is no significant interplane capacitance
between power and ground Therefore, the decoupling must be
designed very carefully to account for this fact
46
Not nearly as common, but a good performing stack-up for a six-layer board is shown
________________Signal(H1)
________________Ground  H1 indicates the horizontal
________________Signal (V1) routing layer for signal 1
________________Signal (H2)  V1 indicates the vertical
________________Power routing layer for signal 1.
________________Signal (V2)  H2 and V2 represent the same
for signal 2
Advantages
Orthogonal routed signals always reference the same plane
Disadvantage
The signals on layer one and six are not shielded, therefore the signal layers should be
placed very close to their adjacent planes, & the desired board thickness made up by
the use of a thicker center core
This configuration satisfies objectives 1 and 2, but not 3, 4, or 5.
47
• Another excellent performing six-layer board is shown
________________Ground/ Mounting Pads
________________Signal
________________Ground
________________Power
________________Signal
________________Ground
• Advantage
 It provides two buried signal layers and adjacent power and ground planes
and satisfies all five objectives
• Disadvantage
 It only has two routing layers -- so it is not often used
48
Possible Combination of 6 Layer Stack-up
49
Ten-Layer Boards
• A ten-layer board should be used when six routing layers are required.
• Ten-layer boards, therefore, usually have six signal layers and four planes.
• Having more than six signal layers on a ten-layer board is not recommended.
• Ten-layers is also the largest number of layers that can usually be conveniently
fabricated in a 0.062" thick board.
• There are twelve-layer board fabricated as a 0.062" thick board, but the
number of fabricators capable of producing it are limited..
• High layer count boards (ten +) require thin dielectrics (typically 0.006" or less
on a 0.062" thick board) and therefore they automatically have tight coupling
between layers.
• When properly stacked and routed they can meet all five objectives and will
have excellent EMC performance and signal integrity.
50
Ten-Layer Boards (cont…)
• Ideal stack-up for a ten-layer board is shown

________________Signal (low-speed signals)
________________Gnd.
________________Signal (high-speed signals & clocks)
________________Pwr. _
________________Gnd.
________________Gnd. or Pwr.
________________Signal (low-speed signals)
51
• The reason that this stack-up has such good performance is
– The tight coupling of the signal and return planes,
– The shielding of the high-speed signal layers,
– The existence of multiple ground planes, as well as
– A tightly coupled power/ground plane pair in the center of the board.
• High-speed signals normally would be routed on the signal layers buried between
planes (layers 3-4 and 7-8 in this case).
• The common way to pair orthogonally routed signals in this configuration would be to
pair layers 1 & 10 (carrying only low-frequency signals), as well as pairing layers 3 & 4,
and layers 7 & 8 (both carrying high-speed signals).
• By paring signals in this manner, the planes on layers 2 and 9 provide shielding to the
high-frequency signal traces on the inner layers.
• In addition the signals on layers 3 & 4 are isolated from the signals on layers 7 & 8 by
the center power/ground plane pair.
• Example
– High-speed clocks might be routed on one of the pairs, and high-speed address
and data buses routed on the other pair.
– In this way the bus lines are protected, against being contaminated with clock
noise, by the intervening planes
52
• Another possibility for routing orthogonal signals on the ten-
layer board is to pair layers 1 & 3, layers 4 & 7, and layers 8 &
10.
• In the case of layer pairs 1 & 3 as well as 8 & 10, this has the
advantage of routing orthogonal signals with reference to the
same plane.
• The disadvantage, of course, is that if layers 1 and/or 10 have
high frequency signals on them there is no inherent shielding
provided by the PCB planes.
• Therefore, these signal layers should be placed very close to
their adjacent plane.
53

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Session 5

Routing and Stack up

• At the end of this session, student will be able to

• Main issues for routing

• Routing topologies and loading

• This is the ideal topology but not very efficient in that it

• This topology is routing efficient but put heavy load on the

• The preferred topology for high speed digital.

– Changing to layers which have another ground-plane without

• Thevenin termination – Uses two resistors at the end of the line.

• Parallel termination – single resistor at end of line. Resistor value

• Used to match driver impedance

Rt = Xline.impedance(Zo)-Source output Impedance(Ro)

– The advantage of using this termination is that it occupies only small

• Series termination is always a compromise for CMOS drivers as the

• The termination of choice for high speed digital, especially for

– A Thevenin equivalent could be used yet it can take more

– The disadvantage of this termination is its power dissipation .

• Ideal for bus termination or lines with 3-State drivers.

• R1 , R2 provides a DC path at the termination hence there is an

(VCC  VOH ) (VOH )

R1 150 165 160 Zl=74.25

R2 150 135 130

Iohl -0.1 -26mA

Ioll 16.67 19mA

• AC or RC termination, better for technologies not intended for

• Kills large over and undershoot

• Typically implemented as on–board SMTs. One terminator will terminate a minimum

SERIES THEVENIN AC PARALLEL

• Differential lines also require a termination resistor if the line

• PCB stack-up is an important factor in determining the EMC

• One stack-up NOT to use on a six-layer board is the one shown in

• Ideal stack-up for a ten-layer board is shown

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