National Institute of Technology, Jamshedpur

Department of Physics
Final (End) Semester Examination Dated: 7th January 2021

M.Sc. (Second year): 1st semester Course Code: PH3104

(Physics) Course Name: Electronics
Date of Examination: 07/01/2021
Time: 03 Hours M. Marks = 50 Name of the Faculty: Uday Kumar
All questions are compulsory.

Question:1 [3.0+2.0=5.0].
For a given NPN transistor, the collector emitter voltage is 0.4V. Explain the amplification
of an input ac signal of 0.1V in terms of amplification factor. Draw diagram essentially
required to explain the fact.
Question: 2 [3.0+2.0=5.0].
A load resistance of 6KΩ is connected to the circuit of a NPN transistor with VCC = 18V.
Calculate the maximum magnitude of the input signal if the amplification factor β=100, knee
voltage=1V & a change of 0.1V in base emitter voltage causes a change of 2.5mA in
collector current. Further if the load resistance in above problem is comprised of the two
resistances of 2KΩ & 4KΩ in series then calculate the voltage drop in each resistance.
Question: 3 [1.5+1.5+2.0=5.0].
Draw the circuit diagram for a PNP transistor by taking VCC = 18V& RC=6 KΩ. Further draw
the dc load line & determine the position of Q-point if zero signal base current is 40μA &
β=100.
Question: 4 [3.0+2.0 =5.0].
In a source self-bias arrangement, the Q-point of a FET is located as VGS=-1.0V & ID
(saturated drain current) =2.5mA. Calculate the value of resistance RS. Draw the circuit also.
Question: 5 [2.5+2.5 =5.0].
A FET is being operated under the influence of a proper gate voltage of 18Volt as a result of
which the gate current is 2×10-3μA. Calculate the resistance between source & gate.
Comment on the result compared to a bipolar transistor.
Question: 6 [2.5+2.5=5.0].
The drain current of a FET drops from 10mA to 5mA due to change in gate source voltage
from -1.0V to -1.5V at constant drain source voltage. Calculate the trans-conductance value
of the FET if the ac drain resistance is 300KΩ.
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Question: 7 [2.5+2.5=5.0].
Draw the circuit diagram of an OP-AMP based amplifier suitable for the voltage gain of 50of
a suitable input voltage signal if input resistance is 1KΩ & supply voltage is ±12V. Further
calculate the output voltage for the input voltage equal to 0.7sin100πt volt.
Question: 8 [3.0+2.0=5.0].
Draw the circuit diagram of a three inputs adder for which input voltages are -10.0V, +6.0V,
+8.0V corresponding to 1KΩ, 200Ω, 400Ω input resistances respectively. Also calculate the
output voltage if feedback resistance is 500Ω.
Question: 9 [4.0+1.0=5.0].
Draw the circuit diagram of voltage amplifier using two resistances 1KΩ & 3KΩ & an OP-
AMP with supply voltage ±12V suitable for maximum voltage gain. Also calculate the
maximum voltage gain which could be obtained from the above drawn circuit.
Question: 10 [5.0=5.0].
For the two given input voltages v1 & v2 (with respect to ground), draw an OP-AMP circuit
suitable for getting output voltage v0 = 2v1-v2 under suitable conditions using input resistance
R1 & feedback resistance Rf.
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