Engineering Reports - 2023 - Attar - Four Stage CMOS Operational Amplifier Frequency Compensated Via Active Miller Network

Received: 27 July 2023 Revised: 16 October 2023 Accepted: 18 October 2023
DOI: 10.1002/eng2.12810
RESEARCH ARTICLE
Four stage CMOS operational amplifier, frequency

compensated via active miller network
Mahdis Attar1 Hadi Dehbovid2 Alireza Ghorbani1 Habib Adarang2
1
Department of Electrical Engineering,
Sari Branch, Islamic Azad University, Sari, Abstract
Iran A four-stage CMOS operational amplifier is proposed in this work. The designed
2
Department of Electrical Engineering, amplifier is frequency compensated via two differential blocks and two Miller
Nour Branch, Islamic Azad University,
capacitors. Unlike well-known frequency compensation methods, the proposed
Nour, Iran
compensation leaves the output node while exploiting extremely smaller capac-
Correspondence itors compared to conventional approaches. The presented approach is modeled
Hadi Dehbovid, Department of Electrical
Engineering, Nour Branch, Islamic Azad
symbolically and realized at the circuit level via the Hspice circuit simulator
University, Nour, Iran. and 0.18 μm CMOS technology. Good agreements between two separate simu-
Email: hadi.dehbovid@gmail.com lation paths verify the validity and accuracy of the proposed approach. Ample
simulation results are reported to investigate the proposed amplifier regard-
ing parameter mismatches. According to the simulation results, the proposed
four-stage amplifier is an excellent candidate to be used in larger systems such
as data converters, modulators, and sensors while it shows more than 169 dB
as DC-gain, 10 MHz as unity gain frequency with power consumption less than
500 μW.
KEYWORDS
CMOS, frequency compensation, miller capacitor, multi-stage amplifier, OTA
1 I N T RO DU CT ION
Nowadays, high-gain amplifier is in demand for realizing electronic systems such as data converters, modulators, and sen-
sors. This becomes a challenging task for circuit designers since supply voltages are reduced continuously by advancing
technology.1,2 Smaller supply voltages limit exploiting cascode structures since evolved MOSFETs (Metal Oxide Semicon-
ductor Field Effect Transistors) need considerable Drain-Source voltage to operate in the saturation region.3,4 This is the
main cause of using multi-stage amplifiers while cascode structures are more efficient, stable, simple, and low-power.
Nevertheless, multi-stage or cascade amplifiers turn to reliable choices, providing a very large DC gain, more than
100 dB.5,6
The major problem with multi-stage amplifiers is stability issues since the number of nodes is increased compared
to cascode versions.7,8 As a result, using a frequency compensation network along with the main amplifier becomes an
inevitable task. In this way, the main part of the design allocates to designing a compensation network. Considering the
whole amplifier as an on-chip device, it is important concerning the compensation capacitors’ value. Usually, passive ele-
ments occupy a large part of the die area, so less value for compensation capacitors leads to less die occupation. This issue
This is an open access article under the terms of the Creative Commons Attribution License, which permits use, distribution and reproduction in any medium, provided the
original work is properly cited.
© 2023 The Authors. Engineering Reports published by John Wiley & Sons Ltd.
Engineering Reports. 2023;e12810. wileyonlinelibrary.com/journal/eng2 1 of 16

https://doi.org/10.1002/eng2.12810
25778196, 0, Downloaded from https://onlinelibrary.wiley.com/doi/10.1002/eng2.12810, Wiley Online Library on [12/11/2023]. See the Terms and Conditions (https://onlinelibrary.wiley.com/terms-and-conditions) on Wiley Online Library for rules of use; OA articles are governed by the applicable Creative Commons License
2 of 16 ATTAR et al.
has to be considered when the amplifier needs to show acceptable GBW (Gain-Bandwidth product) and PM (Phase Mar-
gin).9,10 In this way, several frequency compensation approaches are introduced for mainly three-stage amplifiers while
some are developed further in compliance with four-stages amplifiers.11,12 Among basic methods, Nested Miller Com-
pensation (NMC) and Reversed Nested Miller Compensation (RNMC) have been investigated and developed further.13,14
These two methods, perform frequency compensation via two Miller loops. The main drawback of NMC and RNMC is
needing large-value Miller capacitors.15,16 For instance, almost a larger than 100 pF compensation capacitor is required for
a 100 pF load capacitor. This limitation may satisfy designers to consider compensation capacitors off-chip. Also, several
compensation approaches exploit active blocks in the compensation network.17,18 For example, using a Miller capacitor
at the output of the voltage buffer or input of the current buffer bans one direction of the path. This may eliminate RHP
Zero (Right Half Plan Zero) and improve frequency response in terms of PM.19,20 Even differential blocks are involved in
compensation networks that can share a single capacitor in multiple loops. This feature is important since the number
of needed capacitors can be reduced while their values can be selected as small as possible.21,22 The reason behind this
is the fact that differential block DC-gain is multiplying with compensation capacitor in TF symbolical calculations.23–25
So differential blocks with larger DC-gain may result in smaller compensation capacitors and less die occupation conse-
quently. Here in this work, a four-stage amplifier frequency is compensated by two Miller capacitors and two differential
blocks.26–28
Section 2 describes the proposed configuration and provides a symbolic analysis to calculate TF (Transfer Function).
Also, circuit realization and circuit dynamics are discussed in this section. Simulation results are reported in Section 3
while both the MATLAB and the Hspice are exploited for symbolic analysis and circuit simulation, respectively. Finally,
the conclusion is brought in Section 4.
2 PROPOSED CONFIGURAT ION
The linear model of the proposed amplifier is shown in Figure 1. According to this figure, the first and third stages have
positive gains while the second and last stages are inverting stages. The frequency compensation network is applied
symmetrically without any capacitive load on the output node. Also two compensation capacitors Cc1 and Cc2 are placed
at the output of differential blocks. These two capacitors are commonly shared in four possible loops as illustrated by
Figure 2. According to these loops, compensation capacitors affect mostly “C” and “D” nodes to determine frequency
response.
F I G U R E 1 The proposed four-stage amplifier with utilized a frequency compensation network. Totally five gm stages are involved with
two compensation capacitors.
FIGURE 2 Four possible loops in the proposed structure.

ATTAR et al. 3 of 16
The major aim of using two differential blocks to form compensation network is to create four Miller loops via two
Miller capacitors. So each compensation capacitor is shared by two loops. In this way, the needed number of Miller capac-
itor is reduced to half. Additionally, Miller capacitors are placed at the output of differential blocks that virtually increase
their effect by multiplying the capacitors and the differential stage DC gain. As a results the size of needed compensation
capacitors are reduced too.
Based on Equations (1)–(6), applying KCL (Kirchhoff Current Law) equations on nodes leads to a set of equations.
Solving these equations against node voltages reveals TF symbolically as described by Equation (7) with the three condi-
tions that assumed larger than unity for each stage DC gain, a larger value for load capacitor compared to compensation
capacitors, and smaller values for parasitic capacitors in comparison of Miller capacitors. The simplifier coefficients are
reported by Equations (8)–(16).
VA
KCL at Node A ∶ + VA C1 s − Vin gm1 = 0 (1)
R1
VB
KCL at Node B ∶ + (VB − VC )CC1 s − (VA − VD )gf 1 = 0 (2)
Rf 1
Vc
KCL at Node C ∶ + VC C2 s + VA gm2 + (VC − VB )CC1 s = 0 (3)
R2
VD
KCL at Node D ∶ + VD C3 s − VC gm3 + (VD − VE )Cc2 s = 0 (4)
R3
VE
KCL at Node E ∶ + (VE − VD )Cc2 s − (Vout − VC )gf 2 = 0 (5)
Rf 2
Vout
KCL at Node Out ∶ + Vout CL s + VD gm4 = 0 (6)
RL
As2 + Bs + C
H(s) = (7)
Ds6 + Es5 + Fs4 + Gs3 + Ks2 + Ms + 1
A = Cc1 Cc2 R1 R2 R3 RL Rf 1 Rf 2 gm1 gm2 gm3 gm4 (8)
B = Cc1 R1 R2 R3 RL Rf 1 gm1 gm2 gm3 gm4 + Cc2 R1 R2 R3 RL Rf 2 gm1 gm2 gm3 gm4 (9)
C = R1 R2 R3 RL gm1 gm2 gm3 gm4 (10)
D = C1 C2 C3 CL Cc1 Cc2 R1 R2 R3 RL Rf 1 Rf 2 (11)
E = C1 C2 CL Cc1 Cc2 R1 R2 RL Rf 1 Rf 2 (12)
F = C1 CL Cc1 Cc2 R1 RL Rf 1 Rf 2 (13)
G = CL Cc1 Cc2 RL Rf 1 Rf 2 (14)
K = Cc1 Cc2 R3 RL Rf 1 Rf 2 gf 2 gm4 (15)
M = Cc2 R3 RL Rf 2 gf 2 gm4 (16)
In this way, the roots of the TF numerator and denumerator can represent zeros and poles of the TF, respectively. So
two left-sided zeros are specified by Equations (18)–(19) and six poles are approximated by Equations (21) and (26).
B C
s2 + s+ =0 (17)
A A
B Cc1 Rf 1 + Cc2 Rf 2
Z1 ≈ = (18)
A Cc1 Rf 1 Cc2 Rf 2
C 1
Z2 ≈ = (19)
B Cc1 Rf 1 + Cc2 Rf 2
E 5 F 4 G 3 K 2 M 1
s6 + s + s + s + s + s+ =0 (20)
D D D D D D
G 1
P1 ≈ = (21)
F Cc2 R3 RL Rf 2 gf 2 gm4
G 1
P2 ≈ = (22)
F Cc1 Rf 1
K R3 gf 2 gm4
P3 ≈ = (23)
G CL
G 1
P4 ≈ = (24)
F C1 R1
F 1
P5 ≈ = (25)
E C2 R2
E 1
P6 ≈ = (26)
D C3 R3
It is an approximation and is valid if the roots are ten times far from each other. In this view, P1 is the dominant pole
without any dependence to load capacitor.
To calculate Gain-DC, we can consider TF for S = 0, as Equation (27):
GainDC ∶ H(S) |s=0 = C = −R1 R2 R3 RL gm1 gm2 gm3 gm4 (27)
In addition, the PM and GBW of the system are described in Equations (28) and (29):
(
GBW GBW GBW GBW GBW
PM = 180 − tan−1 + tan−1 + tan−1 + tan−1 + tan−1
P1 P2 P3 P4 P5
)
GBW GBW GBW
+tan−1 − tan−1 − tan−1 (28)
P6 Z1 Z2
DC_Gain
GBW ≈ (29)
P1
At last but not least, circuit realization of the proposed amplifier is suggested via Figure 3. In this scheme, M1 and M2
play input differential pair with current mirror load via M3 and M4 while M5 supplies currents for both branches. Also,
the second stage includes M6 and M7 as a common source stage with negative gain. The third stage as a positive stage
involves M8 –M9 –M10 –M12 while the fourth stage exploits M11 and M13 . Additionally, two similar differential stages are
shown in the figure. Both differential blocks in compensation network are similar in size. The only important point is
that these stages have to be designed in a way that consume as low as possible power. So their sizes are considered small
compared to the similar first stage.
With the mentioned background, a straightforward design methodology can be developed. In this vein, consider-
ing negative loops for Miller capacitors, potential structures can be suggested, then exploiting KCL equations, symbolic
TF could be extracted. Also, initial numerical values can produce responses in the frequency domain. Now, optimizing
numerical values leads to desirable performance. The optimization process can be considered as try-and-error efforts or
defining evolutionary algorithms. So obtained parameters including transconductances, resistors, and capacitors can be
realized via the circuit.
FIGURE 3 Circuit realization of the proposed amplifier.
3 S I M UL AT ION R E SU LT S
The described amplifier in Figure 3 is simulated using the HSPICE circuit simulator and 0.18 μm CMOS (Complemen-
tary Metal Oxide Semiconductor) technology. The MOSFETs’ sizes are tabulated in Table 1, while circuit parameters are
reported in Table 2. The supply voltage is set to 1.8 V.
First of all, Figure 4 represents two distinct frequency responses extracted from simplified symbolic TF in Equation (2)
and circuit simulation. According to this figure, both methods show an acceptable match at least in the operational fre-
quency range between DC frequencies to GBW frequency. The error is associated with GBW frequency which is mainly
related to parasitic elements. Based on the reported frequency response the proposed amplifier shows 169 dB as DC gain
while providing 10.7 MHz as GBW. These values are desirable since the amplifier is driving a relatively large load capaci-
tor of about 500 pF. It should be noted that the total exploited compensation capacitors value is 1 pF which is considerably
small versus conventional methods such as NMC and RNMC. So the presented structure can save the die area in an
elegant way.
On the other hand, to verify performance shown in frequency response, Table 3 reported as corners responses. In this
regard, “s” denotes slower operation, and “F” denotes the faster operation of MOSFETs while the first letter is related
T A B L E 1 MOSFETs dimensions.
MOSFET W/L (𝛍m) MOSFET W/L (𝛍m)
M1 and M2 2 × (10/0.7) M9 , M10 , M11 2 × (3.6/0.36)

M3 and M4 10/1.4 M12 4 × (3.6/0.36)
M5 10/0.36 M13 8 × (3.6/0.36)
M6 4 × (5/0.36) Mf1 , Mf2 , Mf6 , Mf7 0.72/0.18
M7 2 × (10/0.36) Mf3 , Mf8 0.36/0.18
M8 2 × (10/0.7) Mf5 , Mf10 1.44/0.18
Mf4 , Mf9 0.36/0.36
T A B L E 2 Circuit details.
Circuit parameter Symbol Value
First stage gm (A/V) gm1 50e−6
Second stage gm (A/V) gm2 300e−6
Third stage gm (A/V) gm3 300e−6
Fourth stage gm (A/V) gm4 350e−6
differential blocks gm (A/V) gmf1 10e−6

gmf 2 10e−6
Compensation capacitors (F) CC1 0.4e−12

CC2 0.4e−12
Load capacitor (F) CL 500e−12
Bias voltages (V) V b1 0.68

V b2 0.76
First stage output resistor (kΩ) R1 221
Second stage output resistor (kΩ) R2 188
Third stage output resistor (kΩ) R3 210
Fourth stage output resistor (Ω) RL 250
Differential blocks output resistor (kΩ) Rf 1 and Rf 2 55
to the NMOS, and the second letter is associated with the PMOS transistors. In accordance with this table, the proposed
circuit shows acceptable performance for different corners. In addition, Figure 5 is shown the frequency response of
symbolic TF for two exact and simplified versions. As shown by the figure, the simplified and exact TF are appropriately
matched together if we consider just the operational range.
There are three frequency responses in this work. The exact TF, simplified TF and circuit simulator result. As shown
in Figure 4, it is obvious that three poles (P4 , P5 and P6 ) are neglected by simplified TF since these dynamics are far enough
to be neglected. The reason behind this is the fact that each dynamic can affect the frequency response from frequencies
ten times smaller to ten times larger than where it occurs. So, if a dynamic occurs at frequencies greater than ten times
the unit gain, it practically has no effect on the performance of the system in the operating range.
The noise consideration is performed for the first stage. In MOSFET devices, two important noise sources are existing,
which are flicker noise (below 1 MHz) and thermal noise. First, the noise follows a 1/f 𝜐 dependence and is known as flicker
noise (v = 0.8–1.2) or 1/f noise. Above the corner frequency, f c , the noise normally is frequency independent (thermal
and shot noise). Above the second characteristic frequency, fC′ , the noise increases sharply due to parasitic capacitances
coupling noise between different regions of the device. CMOS amplifiers tend to be noisier than bipolar amplifiers, only
FIGURE 4 Frequency response of the proposed amplifier, extracted from both simplified symbolic TF and circuit simulator.
T A B L E 3 Corner simulations results.

Corner TT FF SS SF FS
◦
Temp ( C) 27 85 −10 27 85 −10 27 85 −10 27 85 −10 27 85 −10
I dd (μA) 211 206 215 210 214 211 205 210 214 212 210 216 212 215 207
DC gain (dB) 169 171 164 174 171 178 185 178 168 170 169 174 155 160 169
GBW (MHz) 10.07 9.5 11.6 13.4 12.5 9.6 8.2 9.6 10.2 9.6 12.2 9.1 12.5 12.6 11.1
PM (deg) 82 84 79 79 78 85 78 85 80 81 78 86 85 77 79
GM (dB) 22.7 20.3 26.7 21.5 21.3 20.5 20.2 19.9 23.1 22.4 24.2 19.5 23.6 19.8 22.2
SR 1.40 1.35 1.45 1.41 1.42 1.45 1.42 1.38 1.46 1.41 1.41 1.49 1.42 1.43 1.32
Settling time (μs) 14 15 21 13 16 24 14 17 19 15 14 21 12 14 22
FIGURE 5 Frequency response of the proposed amplifier, extracted from exact and simplified symbolic TF.
minimal bias current is needed for the input stage allowing for designs with low input current noise. As we know the
noise contributions of the second and third stages of the Op-Amp are negligible, because they are divided by the gain of
the previous stages when referred to the main input. Also, noise contribution of current source M5 is negligible. With the
assumption that M1 and M2 are equal regarding size, also M3 and M4 are equal in size, the total input referred flicker
noise power spectral density (PSD) and thermal noise PSD are as Equations (30) and (31):
2Kfn 2Kfp 2
1 1 g
V 2 Flic ker = . + . . 2 m3 (30)
Cox (WL)1 f Cox (WL)3 f g m1
8KT𝛾 8KT𝛾
V 2 Thermal = + 2 .gm3 (31)
gm1 g m1
The value of 𝛾 is 1 and 2/3 in the triode and saturation regions, respectively, while the gm can be described as
Equation (18).
√ ( )
W
gm1 = 2𝜇n Cox ID1 (32)
L
According Equations (30), (31), and (32), there are three techniques that can be used to reduce the flicker noise and
thermal noise:
1. Determination of input pair type for M1 and M2.

2. Optimization of the bias current ID1 of the input pair.
3. Optimization of the sizes and aspect ratios of the MOSFETs.
3.1 Determination of input pair type for M1 and M2
The first approach to minimizing the 1/f noise uses circuit topology and transistor selection. The transistor selection is
easy. In this structure, NMOS should be chosen for input pair M1 and M2 for the following three reasons:
1. Selecting a NMOS transistor for the input pair reduce thermal noise according to Equations (31) and (32), since NMOS
transistor have larger carrier mobility than PMOS transistor.
2. The NMOS flicker noise coefficient K fn is smaller than that of PMOS flicker noise coefficient K fp for the process we use
(In the 0.18 μm TSMC CMOS process flicker noise coefficient for PMOS is 2.932E−23 and for NMOS is 3.564E−24),
which is helpful for achieving lower flicker noise according to Equation (30).
3. NMOS transistor has a higher transition frequency f T than PMOS transistor, which help to achieve a higher bandwidth.
3.2 Optimization of the bias current I D1 of the input pair
The bias current I D1 of the input pair M1 and M2 must be maximized to decrease both types of noise. This is achieved by
selecting a large size and high aspect ratio for the input pair.
3.3 Optimization of the sizes and aspect ratios of the MOSFETs
To decrease the flicker noise, a large size for (W/L)1 is chosen and the channel lengths L3,4 are designed larger than that
of the input pair M1 and M2 based on Equation (30).
The aspect ratio (W/L)1 is maximized and made larger than (W/L)3 to reduce the thermal noise according to
Equations (31) and (32). After those choices, the input pair dominates the noise contribution of both types. From
Equation (30), the charge of the input pair’s gate length can increase or decrease the flicker noise.16
9 of 16
GBW and PM deviations versus differential blocks transconductances.
GBW and PM deviations versus compensation capacitors.

FIGURE 6
FIGURE 7
ATTAR et al.
Additionally, for a more in-depth view, performance sensitivity against compensation network parameters are shown
in Figures 6 and 7. In this vein, Figure 6 expresses GBW and PM values versus leveraged differential block transconduc-
tances (gmf 1 and gmf 2 ) while Figure 7 demonstrates GBW and PM deviations against exploited Miller capacitors. As shown
by these analyses, the simulated amplifier perfectly shows acceptable GBW and PM values versus both transconductance
and compensation capacitor probable mismatches.
Moreover, the pole-zero map is demonstrated in Figure 8 and Table 4. According to this map, three poles including
two complex poles, are far enough to be ignored while three poles and two zeros fall into the operational frequency range.
The blue dashed rectangular shows influential dynamics and the green dashed rectangular highlights the locations of
two zeros and the second pole.
Additionally it should be noted that Equations (17)–(26) are just rough approximations since showing just real
parts of poles. While in accordance to pole-zero map in Figure 8, at least two poles shown as complex conjugate
values.
In addition, to consider probable mismatches in the design procedure, circuit parameters include all MOSFETs
dimensions and capacitors are posed to 30% variations based on Gaussian distribution. One thousand times simula-
tions are performed in this way and result in terms of GBW and PM are reported in Figure 9 and Table 5. According
to this figure, the described variations can cause illustrated deviations which is considered an acceptable response
against relatively large 30% variations. So this analysis shows the robustness and reliability of the proposed amplifier in
another aspect.
Besides, Figure 10 expresses the step response of the proposed amplifier which verifies a settling time of about 0.14 μs
for both rising and falling edges.
Furthermore, Figure 11 shows the frequency response of the proposed amplifier for three different load capacitors.
According to this figure, the proposed amplifier is unstable for small load capacitors since the operation is critically depen-
dent to the third pole (Equation (23)). According to this figure, the PM for 50 pF load degenerated to less than 55◦ while
the amplifier is unstable for 5 pF load capacitor.
According to Figure 11, the proposed amplifier shows higher PM for a larger load capacitor. On the other hand,
the load capacitor is related to the third pole. As a result, changing the load capacitor manipulates the occurred
pole-zero cancellation in Figure 8. In the case of different load capacitor, setting the poles and zero locations for proper
canceling needs changing other elements in the compensation network. So the presented scenario is valid for large
capacitive loads.
As we know, the amplifier possesses different parameters including DC gain, GBW, PM, Slew Rate (SR) and load
capacitor. So, it is a biased comparison if we consider only one parameter.
To fair comparison of the proposed amplifier with other state of art works, the Figure of Merit (FOM) idea is exploited.
In this regard, seven FOMs are used as criteria via Equations (33)–(38). These relations consider different aspects of an
amplifier. For instance, FOM1 highlights small signal behavior via GBW value, and FOM2 concentrates on large signal
behavior by considering SR value. Also, FOM3 and FOM4 remove the effects of supply voltage dependency by replacing
power with current consumption. Additionally, FOM5 involves compensation capacitor value, so a larger value for this
FOM shows probable smaller die occupation. Finally, FOM6 takes into account the compensation capacitor without the
load capacitor. The comparison of parameters and FOMs are reported in Table 6.
According to this Table 6, the proposed amplifier uses very small Miller capacitors which can reduce die area
considerably. While compensation network is mostly active which increases design complexity.
𝜔GBW × CL ( )
Hz × F
FOM1 = (33)
Power W
SR × CL ( )
1
FOM2 = (34)
Power V
𝜔GBW × CL ( )
Hz × F
FOM3 = (35)
Idd A
SR × CL
FOM4 = (36)
Idd
FIGURE 8 Pole-zero locations of the proposed amplifier. The dashed blue rectangular shows circuit dynamics in the operational
frequency range.
T A B L E 4 Poles and zeros numerical values.
P1 = −0.12 Hz P2 = −3.2 MHz P3 = −14.06 MHz

P4 = −0.28 GHz P5 = (−0.59 + 0.96i) GHz P6 = (−0.59–0.96i) GHz
Z1 = −3.2 MHz Z2 = −3.19 MHz
FIGURE 9 Monte-Carlo results for thousand iterations.

T A B L E 5 Final results of the Monte-Carlo simulation.

Minimum Maximum Mean Standard deviation Circuit result
PM (deg) 76 86 81 3.8 82
GBW (MHz) 9 16 13 3.4 10.7
F I G U R E 10 Step response of the proposed amplifier.
F I G U R E 11 Frequency response for different load capacitors.
𝜔GBW × CL2 ( )
Hz × F
FOM5 = (37)
Power × CCtot W
𝜔GBW ( )
Hz
FOM6 = (38)
Power × CCtot W × F
ATTAR et al.
T A B L E 6 Comparison table.
DC Compensation Slew Supply CMOS
gain Load Power GBW capacitor rate voltage technology
(dB) (pF) (𝛍W) (MHz) (pF) (V/𝛍S) P.M (◦ ) FOM1 FOM2 FOM3 FOM4 FOM5 FOM6 (V) (𝛍m)
NMC29 100 100 345 0.22 110 0.25 68.3 0.06 0.07 0.12 0.14 0.054 57e−7 3.3 0.36
NMCNR29 100 100 345 0.32 78 0.30 70.5 0.09 0.08 0.18 0.17 0.115 12 e−6 3.3 0.36
DPZC30 100 100 345 0.40 49.5 0.39 90.5 0.11 0.11 0.23 0.22 0.222 23 e−6 2 0.35
NGCC31 >100 100 365 0.25 96 0.33 69.1 0.06 0.09 0.13 0.18 0.062 71 e−7 1.8 0.36
NMCF32 102 100 345 0.67 34 0.57 69.6 0.19 0.16 0.38 0.33 0.558 57 e−6 1.2 0.36
DFCFC33 >100 100 372 0.96 35 0.80 66.6 0.25 0.23 0.51 0.43 0.714 73 e−6 3.3 0.36
34
AFFC >100 100 424 2.60 15 12.00 70.4 0.61 2.83 1.22 5.66 4.066 4 e−4 2 0.8
35
ACBC >100 100 365 2.06 18 1.22 69.6 0.56 0.33 1.12 0.66 3.111 3 e−4 3.3 0.36
36
RNMC >100 120 330 2.50 8 - 50 0.90 - 1.62 - 13.50 94 e−5 1.8 0.18
37
DCCII 115 100 310 9.63 3.9 7.01 85 3.11 2.26 5.60 5.18 79.65 0.008 1.8 0.18
VM38 104 10,000 360 16 6 0.1 86 444 2.78 800 5 740,740 0.007 1.8 0.18
CM38 106 10,000 360 11 2 0.1 80 305 2.78 550 5 1,527,777 0.015 1.8 0.18
39 173 1000 156 3 10 1.18 55 19.23 7.56 34.61 13.6 1923 0.002 2.5 0.065
40 - 250 10,000 2 35 1.5 - 0.05 0.04 0.25 0.2 0.35 5 e−6 5 1.5
41
120 10 1500 2 5 5 60 0.01 0.03 0.03 0.09 0.03 3 e−4 2 1.5
42
100 100 14,000 1 65 2.1 63 0.007 0.01 0.03 0.05 0.01 1 e−6 2 0.8
43
108 500 14,000 40.2 17.6 17.5 62 1.42 0.62 4.26 3.1 40.7 2 e−4 1 0.12
44 175 500 156 3 9.9 1.09 63 31.73 3.49 31.73 3.49 485 1 e−3 3 0.35
This Work 169 500 380 10.07 1 6.3 82 14.07 8.28 25.32 14.89 6625 0.026 1.8 0.18
13 of 16
4 CO N C LU S I O N
A four-stage CMOS operational amplifier is frequency compensated via two differential blocks and two Miller capacitors.
The symbolical TF is calculated and compared with results from the HSPICE circuit simulator while 0.18 μm CMOS
technology is exploited. Ample simulations are reported to show frequency response and critical parameters such as
DC-gain, GBW, and, PM. Using reduced value for compensation capacitors besides competitive results make the proposed
amplifier an ideal choice for realizing more complex blocks in modern electronics such as data convertors and modulators.
AU THOR CONTRIBUTIONS
Mahdis Attar: Resources (lead); software (lead); validation (lead); writing – original draft (lead). Hadi Dehbovid: Inves-
tigation (equal); project administration (equal); writing – review and editing (equal). Ali Reza Ghorbani: Investigation
(equal); methodology (equal); project administration (equal); writing – review and editing (equal). Habib Adarang:
Investigation (equal); methodology (equal); project administration (equal); writing – review and editing (equal).
CONFLICT OF INTEREST STATEMENT

The authors who name are listed in the manuscript certify that they have NO affiliations with or involvement in any
organization or entity with any financial interest (such as honoraria; educational grants; participation in speakers’
bureaus; membership, employment, consultancies, stock ownership, or other equity interest; and expert testimony or
patent-licensing arrangements), or non-financial interest (such as personal or professional relationships, affiliations,
knowledge or beliefs) in the subject matter or materials discussed in this manuscript.
PEER REVIEW
The peer review history for this article is available at https://www.webofscience.com/api/gateway/wos/peer-review/10.
1002/eng2.12810.
DATA AVAILABILITY STATEMENT

The data that support the findings of this study are available from the corresponding author upon reasonable request.
ORCID
Mahdis Attar https://orcid.org/0000-0001-8703-4024
REFERENCES
1. Chaharmahali I, Mianvelayat MV, Biabanifard S. Enhanced comparator-based switched-capacitor integrator using current conveyor. Int
J Numer Modell Electron Netw Devices Fields. 2020;33:e2729.
2. Zanjani S, Masoud TA, Biabanifard S. A high-performance CMOS four-stage amplifier. Int J Numer Modell Electron Netw Devices Fields.
2019;32(6):e2647.
3. Asiyabi T, Zanjani MS, Goodarzi M, Biabanifard S. Four stage OTA CMOS frequency compensation based on double differential feedback
paths. Analog Integr Circ Sig Process. 2019;101(1):155-168.
4. Valianpour E, Chaharmahali I, Biabanifard S. Nonlinear current source charge scheme for comparator based switched capacitor integrator.
Int J Numer Modell Electron Netw Devices Fields. 2019;32(3):e2542.
5. Asadi S, Yaghoub MCE, Biabanifard S. A new approach for signal and noise FET modeling including wave propagation effects. Int J Numer
Modell Electron Netw Devices Fields. 2015;28(6):755-766.
6. Hosseini Largani S, Mehdi SS, Biabanifard S, Jalali A. A new frequency compensation technique for three stages OTA by differential
feedback path. Int J Numer Modell Electron Netw Devices Fields. 2015;28(4):381-388.
7. Akbari M, Biabanifard S, Asadi S. Input referred noise reduction technique for trans-conductance amplifiers. Electr Comput Eng: Int J
(ECIJ). 2015;4(4):11-22.
8. Akbari M, Biabanifard S, Asadi S, Yagoub MCE. High performance folded cascode OTA using positive feedback and recycling structure.
Analog Integr Circuits Signal Process. 2015;82:217-227.
9. Akbari M, Biabanifard S, Asadi S, Yagoub MCE. Design and analysis of DC gain and transconductance boosted recycling folded cascode
OTA. AEU Int J Electron Commun. 2014;68(11):1047-1052.
10. Akbari M, Biabanifard S, Hashemipour O. Design of ultra-low-power CMOS amplifiers based on flicker noise reduction. Paper presented
at: 2014 22nd Iranian Conference on Electrical Engineering (ICEE). IEEE; 2014.
11. Largani SM, Hosseini SS, Biabanifard S, Jalali A. A new SMC compensation strategy for three stage amplifiers based on differential
feedback path. Paper presented at: In 2014 22nd Iranian Conference on Electrical Engineering (ICEE), pp. 185–189. IEEE; 2014.
12. Biabanifard S, Largani SMH, Biabanifard A, et al. Three stages CMOS operational amplifier frequency compensation using single miller
capacitor and differential feedback path. Analog Integr Circuits Signal Process. 2018;97(2):195-205.
13. Aghaee T, Biabanifard S, Golmakani A. Gain boosting of recycling folded cascode OTA using positive feedback and introducing new input
path. Analog Integr Circuits Signal Process. 2017;90(1):237-246.
14. Roohbakhsh D, Sanaee AM, Aghaee T. Four-stage CMOS operational transconductance amplifier: compensated via double differential
blocks. Int J Numer Modell Electron Netw Devices Fields. 2023;36(4):e3067.
15. Sanaei AM, Biabanifard A, Khadem MS, Aghaee T. Double differential blocks based frequency compensation: a four-stage CMOS
amplifier. J Circuits Syst Comput. 2022;31(15):2250273.
16. Zanjani MS, Sadrnia H, Biabanifard A. Five-stage CMOS OTA frequency compensated via nested differential feedback. Int J Numer Modell
Electron Netw Devices Fields. 2023;36(4):e3079.
17. Zanjani MS, Biabanifard A. Frequency compensation network for three-stage CMOS operational amplifier. J Circuits Syst Comput.
2023;32(8):2350136.
18. Biabanifard M, Mehdi Largani S, Biabanifard A, Hosseini J. Bulk-driven current conveyer based-CMOS analog multiplier. Electr Electron
Eng: Int J (ELELIJ). 2015;4:55-62.
19. Zaherfekr M, Biabanifard A. Improved reversed nested miller frequency compensation technique based on current comparator for
three-stage amplifiers. Analog Integr Circ Sig Process. 2019;98(3):633-642.
20. Rezaei I, Soldoozy A, Khani AAM, Biabanifard A. Circuit design of a three-stage CMOS amplifier by circuit theory and analysis miller
compensation network. Memories-Materials, Devices, Circuits and Systems; 2023:100084.
21. Rezaei I, Zanjani MS, Khani AAM, Biabanifard A. Single miller frequency compensation: three stage CMOS. Memories-Mater Devices
Circuits Syst. 2023;4:100037.
22. Rezaei I, Khani AAM, Dadgar M, Attar M. Fully active frequency compensation analysis on multi-stages CMOS amplifier. Memories-Mater
Devices Circuits Syst. 2023;5:100068.
23. Ghorbanzadeh S, Dehbovid H, Ghorbani A, Pahnekolaei SMA. Design and analysis of a two stage class AB operational trans-conductance
amplifier in 180-nm technology. J Appl Dyn Syst Control. 2022;5(2):35-43.
24. Ghorbanzadeh S, Dehbovid H, Ghorbani A, Pahnekola MA. Two-stage class-AB OTA with improved specifications. Analog Integr Circ Sig
Process. 2022;111(2):159-168.
25. Dehbovid H, Adarang H, Rabiee H. Analysis of Settling Time in Charge Pump Phase-Locked Loops Regarding Non-ideal Effect. Nashriyyah-I
Muhandisi-I Barq va Muhandisi-I Kampyutar-I Iran, A-Muhandisi-I Barq; 2022:146-152.
26. Ghorbanzadeh S, Dehbovid H, Ghorbani A, Pahnekola MA. A topology of class-AB OTA with increased DC-gain and slew-rate. J Appl
Dyn Syst Control. 2021;4(2):32-40.
27. Dehbovid H, Adarang H, Tavakoli MB. Nonlinear analysis of jitter transfer in charge pump phase-locked loops regarding channel length
modulation effect. Nashriyyah-i Muhandisi-i Barq Va Muhandisi-i Kampyutar-i Iran. 2018;63(2):115.
28. Dehbovid H, Adarang H, Tavakoli MB. Nonlinear analysis of VCO jitter generation using Volterra series. COMPEL Int J Comput Math
Electr Electron Eng. 2018;37(2):755-771.
29. Grasso AD, Marano D, Palumbo G, Pennisi S. Analytical comparison of reversed nested miller frequency compensation techniques. Int
J Circuit Theory Appl. 2010;38(7):709-737.
30. Grasso AD, Marano D, Palumbo G, Pennisi S. Reversed double pole-zero cancellation frequency compensation technique for three-stage
amplifiers. Ph.D. Res Microelectron Electron, Otranto, Italy. 2006;2006:153-156. doi:10.1109/RME.2006.1689919
31. Peng X, Sansen W. Nested feed-forward Gm-stage and nulling resistor plus nested-Miller compensation for multistage amplifiers. In
Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No. 02CH37285). IEEE; 2002.
32. Wang C-C, Huang C-C, Lee T-J, Fat Chio U. A linear LDO regulator with modified NMCF frequency compensation independent of off-chip
capacitor and ESR. Paper presented at: APCCAS 2006–2006 IEEE Asia Pacific Conference on Circuits and Systems. IEEE; 2006.
33. Leung KN, Mok PKT, Ki W-H, Sin JKO. Three-stage large capacitive load amplifier with damping-factor-control frequency compensation.
IEEE J Solid State Circuits. 2000;35(2):221-230.
34. Lee H, Mok PKT. Active-feedback frequency-compensation technique for low-power multistage amplifiers. IEEE J Solid State Circuits.
2003;38(3):511-520.
35. Peng X, Sansen W. AC boosting compensation scheme for low-power multistage amplifiers. IEEE J Solid State Circuits.
2004;39(11):2074-2079.
36. Biabanifard S, Mehdi Largani S, Akbari M, Asadi S, Yagoub MCE. High performance reversed nested miller frequency compensation.
Analog Integr Circuits Signal Process. 2015;85:223-233.
37. Shahsavari S, Sadegh Biabanifard S, Largani MH, Hashemipour O. DCCII based frequency compensation method for three stage
amplifiers. AEU-Int J Electron Commun. 2015;69(1):176-181.
38. Biabanifard S, Mehdi Hosseini S, Biabanifard M, Asadi S, Yagoub MCE. Multi stage OTA design: from matrix description to circuit
realization. Microelectron J. 2018;77:49-65.
39. Grasso AD, Marano D, Palumbo G, Pennisi S. Single miller capacitor frequency compensation techniques: theoretical comparison and
critical review. Int J Circuit Theory Appl. 2022;50(5):1462-1486.
40. Pernici S, Nicollini G, Castello R. A CMOS low-distortion fully differential power amplifier with double nested miller compensation. IEEE
J Solid State Circuits. 1993;28(7):758-763.
41. Eschauzier RGH, Hogervorst R, Huijsing JH. A programmable 1.5 V CMOS class-AB operational amplifier with hybrid nested miller
compensation for 120 dB gain and 6 MHz UGF. IEEE J Solid State Circuits. 1994;29(12):1497-1504.
42. You F, Embabi SHK, Sanchez-Sinencio E. Multistage amplifier topologies with nested G/sub m/-C compensation. IEEE J Solid State
Circuits. 1997;32(12):2000-2011.
43. Yan W, Kolm R, Zimmermann H. Efficient four-stage frequency compensation for low-voltage amplifiers. 2008 IEEE International
Symposium on Circuits and Systems (ISCAS). IEEE; 2008.
44. Grasso AD, Palumbo G, Pennisi S. High-performance four-stage CMOS OTA suitable for large capacitive loads. IEEE Trans Circuits Syst
I: Regul Pap. 2015;62(10):2476-2484.
How to cite this article: Attar M, Dehbovid H, Ghorbani A, Adarang H. Four stage CMOS operational amplifier,
frequency compensated via active miller network. Engineering Reports. 2023;e12810. doi: 10.1002/eng2.12810

Engineering Reports - 2023 - Attar - Four Stage CMOS Operational Amplifier Frequency Compensated Via Active Miller Network

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Engineering Reports - 2023 - Attar - Four Stage CMOS Operational Amplifier Frequency Compensated Via Active Miller Network

Uploaded by

Copyright:

Available Formats

Received: 27 July 2023 Revised: 16 October 2023 Accepted: 18 October 2023

Four stage CMOS operational amplifier, frequency

Mahdis Attar1 Hadi Dehbovid2 Alireza Ghorbani1 Habib Adarang2

Engineering Reports. 2023;e12810. wileyonlinelibrary.com/journal/eng2 1 of 16

2 PROPOSED CONFIGURAT ION

FIGURE 2 Four possible loops in the proposed structure.

A = Cc1 Cc2 R1 R2 R3 RL Rf 1 Rf 2 gm1 gm2 gm3 gm4 (8)

C = R1 R2 R3 RL gm1 gm2 gm3 gm4 (10)

D = C1 C2 C3 CL Cc1 Cc2 R1 R2 R3 RL Rf 1 Rf 2 (11)

E = C1 C2 CL Cc1 Cc2 R1 R2 RL Rf 1 Rf 2 (12)

F = C1 CL Cc1 Cc2 R1 RL Rf 1 Rf 2 (13)

G = CL Cc1 Cc2 RL Rf 1 Rf 2 (14)

K = Cc1 Cc2 R3 RL Rf 1 Rf 2 gf 2 gm4 (15)

M = Cc2 R3 RL Rf 2 gf 2 gm4 (16)

GainDC ∶ H(S) |s=0 = C = −R1 R2 R3 RL gm1 gm2 gm3 gm4 (27)

FIGURE 3 Circuit realization of the proposed amplifier.

M1 and M2 2 × (10/0.7) M9 , M10 , M11 2 × (3.6/0.36)

First stage gm (A/V) gm1 50e−6

Second stage gm (A/V) gm2 300e−6

Third stage gm (A/V) gm3 300e−6

Fourth stage gm (A/V) gm4 350e−6

differential blocks gm (A/V) gmf1 10e−6

Compensation capacitors (F) CC1 0.4e−12

Bias voltages (V) V b1 0.68

Second stage output resistor (kΩ) R2 188

Third stage output resistor (kΩ) R3 210

Fourth stage output resistor (Ω) RL 250

Differential blocks output resistor (kΩ) Rf 1 and Rf 2 55

T A B L E 3 Corner simulations results.

1. Determination of input pair type for M1 and M2.

3.1 Determination of input pair type for M1 and M2

3.2 Optimization of the bias current I D1 of the input pair

3.3 Optimization of the sizes and aspect ratios of the MOSFETs

GBW and PM deviations versus differential blocks transconductances.

GBW and PM deviations versus compensation capacitors.

T A B L E 4 Poles and zeros numerical values.

P1 = −0.12 Hz P2 = −3.2 MHz P3 = −14.06 MHz

FIGURE 9 Monte-Carlo results for thousand iterations.

T A B L E 5 Final results of the Monte-Carlo simulation.

F I G U R E 10 Step response of the proposed amplifier.

F I G U R E 11 Frequency response for different load capacitors.

CONFLICT OF INTEREST STATEMENT

DATA AVAILABILITY STATEMENT

You might also like