(сервискомп-анна.рф) Lenovo G505s Compal LA-A091p r1.0

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1 1
2
Compal Confidential 2
VALGC_GD M/B Schematics Document

AMD Fs1r2 Richland Processor with DDRIII + Bolton-M3 FCH
AMD Mars XT M2
LA-A091P
3
2013-04-16 3
REV:1.0
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/11/13 Deciphered Date 2013/11/12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
VALGD MB L
Date: Friday, April 12, 2013 Sheet 1 of 57
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A B C D E
Compal confidential
File Name :LA-A091P
AMD MARS XT M2 128 bits

PCIEx8 Gen2
1
Sun Pro M2 64bit AMD FS1r2 APU 1
VRAM: DDR3 type, 1GB/ 2GB
page 16~25 Memory BUS(DDRIII) 204pin DDRIII-SO-DIMM X2
Richland Dual Channel BANK 0, 1, 2 page 9,10
LVDS
DP Port0
uPGA 722 pin DDR3 / DDR3L 1600MHz
LVDS Conn. translator DP0 35mm x 35mm
page 27
RTD2132S
page 26
HDMI Conn. DP Port2
page 29
DP2
DP1 page 5,6,7,8
x4 UMI Gen. 1
2.5GT/s per lane
GPP1 GPP0
Left USB3.0 x2 Int. Camera
PCIe Mini Card USB30 x2 USB30 Port 0,1 USB20 Port 3
page 39 page 27
WLAN+BT4.0 Combo
USB20 x1 USB20 x6 Touch Screen Card Reader
2 2
Realtek RTS5170
PCIe Port 1 USB20 Port 4
page 39 USB20 Port 6 page 37
USB20 Port 2 page 30
LAN Right USB2.0
PCIe Port 0
RJ45 Conn. Atheros USB20 Port 0

page 39
page 32 AR8162
QCA8172(10/100)
page 31
Bolton M3 SATA Gen3 HDD Conn.
SATA Port 0
page 34
CRT Conn. FCH CRT (VGA DAC)

page 28
uFCBGA-656 SATA ODD Conn.
SATA Port 1
24.5mm x 24.5mm page 34
Thermal Sensor Int. MIC Conn.

page 33
3
EC page 35 3
Touch Pad ENE KB9012
page 37 page 36
Audio Codec Int. Speaker Conn.
AZALIA CONEXANT page 35
Int. KBD CX20757
page 37 page 35
SPI ROM
4MB page 12 page 11~15
Audio Combo Jacks
HP & MIC
page 37
Sub-borad
15"
14"
4 4
Power/B LED/B
LS9902P
LS9903P
IO/B ODD/B
LS9901P LS9904P MB Block Diagram
Size Document Number Rev
Custom 0.1
VALGD MB L
A B C D E
A B C D E
Voltage Rails
SIGNAL
STATE SLP_S3# SLP_S5# +VALW +V +VS Clock
+5VS
+3VS Full ON HIGH HIGH ON ON ON ON
+2.5VS
S1(Power On Suspend) HIGH HIGH ON ON ON LOW
power +1.5VS
plane +1.2VS S3 (Suspend to RAM) HIGH HIGH ON ON OFF OFF
1
+1.1VS LOW 1
+5VALW +1.5V S4 (Suspend to Disk) HIGH ON OFF OFF OFF
+0.75VS
+B +1.5V_APU
+APU_CORE S5 (Soft OFF) LOW LOW ON OFF OFF OFF
+3VALW
+APU_CORE_NB
+VGA_CORE
State +1.1VALW
+3.3VGS BOARD ID Table Board ID / SKU ID Table for AD channel
+1.8VGS
+1.5VGS
Board ID PCB Revision
0 ID BRD ID Ra Rb Vab
+0.95VGS
1 0 R10 MP x 0 0V
2 0.2 Ra = R310
3 1 R03 PVT 100K 8.2K 0.25V Rb = R311
S0 4
O O O O 2 R02 DVT 100K 18K 0.5V
5
6 3 R01 EVT 100K 33K 0.82V
S3 7
O O O X
2
BOM Structure Table 2
S5 S4/AC
O O X X USB Port Table BOM Structure BTO Item
4 External PX@ VGA circuit
S5 S4/ Battery only USB 2.0 USB 3.0 Port
O X X X USB Port 14@ For 14"
0 USB Port 2.0 (Right Side) 15@ For 15"
S5 S4/AC & Battery
don't exist X X X X 1 45@ HDMI LOGO
2 Mini Card(WLAN) CMOS@ CMOS Camera part
3 Camera / 8162@ AR8162 LAN part
S
M
B
U
S
C
o
n
tr
o
l
T
a
b
le
4 Touch Screen 8172@ AR8172 LAN part

5 CMOS@ For CMOS circuit
T
h
e
rm
a
l
W
L
A
N
S
e
n
so
r
6 TS@ For Touch Screen circuit

S
O
U
R
C
E
V
G
A
B
A
T
T
K
B
9
0
1
2
S
O
D
IM
M
F
C
H
A
P
U
R
T
D
2
1
3
2
Card Reader
W
W
A
N
7 X76@ X76 Level part for VRAM

S
M
B
_E
C
_C
K
1
8 GCLK@ Ues GCLK circuit

K
B
9
0
1
2
X
S
M
B
_E
C
_D
A
1
+
3
V
A
L
W
+
3
V
A
L
W
9 NOGCLK@ No use GCLK circuit

S
M
B
_E
C
_C
K
2
_S
U
S
0 10 GCLK302@ 302 part for DIS

K
B
9
0
1
2
USB 2.0 Port (Left Side)

X
X
S
M
B
_E
C
_D
A
2
_S
U
S
+
1
.5
V
+
3
V
A
L
W
1 11 USB 2.0 Port (Left Side) GCLK238@ 238 part for UMA
XHCI
F
C
H
_S
C
L
K
0
2 12 LVDS@ LVDS circuit

F
C
H
X
3 3
F
C
H
_S
D
A
T
A
0
+
3
V
S
+
3
V
S
+
3
V
S
3 13 PXNOGCLK@ No use GCLK circuit in GPU

S
M
B
_E
C
_C
K
2
LDO@ LDO mode for LAN

K
B
9
0
1
2
V
S
M
B
_E
C
_D
A
2
SWR@ SWR mode for LAN

USB OC MAPPING
+
3
V
S
DEBUG@ For debug

(L
V
sh
if
te
r)
OC# USB Port ME part

ME@
0 USB20 port10,port11 USB30 port0,port1 MIC@ MIC part
EC SM Bus1 address EC SM Bus2 address 1 USB20 port0 885N@ Unpop in KBC page
2 JUMP@ JUMP
Device Address Device Address
3 TEST POINT@ TSET POINT
Smart Battery 0001 011X b Thermal Sensor 1001_101xb
SHORT PAD@ SHORT PAD
SB-TSI(default) 1001_100xb
EMI@ EMI part
VGA(int. thermal) 1000_001xb APU PCIE PORT LIST FCH PCIE PORT LIST
@ESD@ Reserve for ESD
RTD2132S 1010_1000b Port Device Port Device
@EMI@ Reserve for EMI
VGA(ext. thermal) 0100_1101b
1 LAN 1 @ Unpop
2 WLAN 2 MARS@ VRAM CHB parts for MARS
PCH SM Bus address
4 3 3 2132S@ Panel PWM part for RTD2132S 4
Device Address 4 4 2132R@ Panel PWM part for RTD2132R

DDR DIMM0 1001 000Xb ShareROM@ Reserve for ShareROM
DDR DIMM2 1001 010Xb Strap@ Reserve for Strap pin
Notes List
Custom 0.1
VALGD MB L
A B C D E
5 4 3 2 1
X76@ Mars XT VRAM STRAP X76@ X76@ Sun PRO VRAM STRAP X76@
Vendor PS_3[3] PS_3[2] PS_3[1] R_pu R_pd Vendor PS_3[3] PS_3[2] PS_3[1] R_pu R_pd
UV5,UV6,UV7,UV8, RV20 RV27 UV9,UV10,UV11,UV12 RV20 RV27
UV9,UV10,UV11,UV12
Samsung 2048Mbits Samsung 2048Mbits

SA000068U00 SA000068R00
128M16 K4W2G1646E-BC1A FBGA
0 0 0 NC 4.75K SS2G 256M16 K4W4G1646B-HC11 FBGA
0 0 0 NC 4.75K
MS2G
D D
Micron 2048Mbits Micron 2048Mbits
MM2G SA000067500 0 0 1 8.45K 2K SM2G SA000065D00
128Mx16 MT41J128M16JT-093G:k 256M16 MT41K256M16HA-107G
0 0 1 8.45K 2K
Hynix 2048Mbits Samsung 1024Mbits
MH2G SA000065300 SA000068U00
128M16 H5TQ2G63DFR-N0C FBGA
0 1 0 4.53K 2K SS1G 128M16 K4W2G1646E-BC1A FBGA
0 1 1 6.98K 4.99K
Micron 1024Mbits
SM1G SA000067500
128Mx16 MT41J128M16JT-093G:k
1 1 0
3.4K 10K
Hynix 1024Mbits
SH1G SA000065300
128M16 H5TQ2G63DFR-N0C FBGA
1 1 1 4.75K NC
Power-Up/Down Sequence
C "Mars" has the following requirements with regards to power-supply sequencing to C
avoid damaging the ASIC:

All the ASIC supplies must reach their respective nominal voltages within 20ms
Ʉ
of the start of the ramp-up sequence, though a shorter ramp-up duration is

preferred. The maximum slew rate on all rails is 50mV/us.
The external pull ups on the DDC/AUX signals (if applicable) should ramp up
Ʉ
before or after both VDDC and VDD_CT have ramped up.

VDDC and VDD_CT should not ramp up simultaneously. For example, VDDC should
Ʉ
reach 90% before VDD_CT starts to ramp up (or vice versa).

For power down, reversing the ramp-up sequence is recommended.
Ʉ
VDDR3(+3VGS)
PCIE_VDDC(+0.95VGS)
B VDDR1(+1.5VGS) B
VDDC/VDDCI(+VGA_CORE)
VDD_CT(+1.8VGS)
PERSTb
REFCLK
Straps Reset
Straps Valid
A A
Global ASIC Reset
T4+16clock
VGA Notes List
Custom 0.1
VALGD MB L
5 4 3 2 1
A B C D E
PCIE_CRX_GTX_P[0..7] PCIE_CTX_GRX_P[0..7]
<16> PCIE_CRX_GTX_P[0..7] PCIE_CTX_GRX_P[0..7] <16>
PCIE_CRX_GTX_N[0..7] PCIE_CTX_GRX_N[0..7]
<16> PCIE_CRX_GTX_N[0..7] PCIE_CTX_GRX_N[0..7] <16>
JCPU1A
PCI EXPRESS
PCIE_CRX_GTX_P0 AB8 AB2 PCIE_CTX_C_GRX_P0 0.1U_0402_16V7K 1 2 CV209 PX@ PCIE_CTX_GRX_P0
PCIE_CRX_GTX_N0 AB7 P_GFX_RXP0 P_GFX_TXP0 AB1 PCIE_CTX_C_GRX_N0 0.1U_0402_16V7K 1 2 CV215 PX@ PCIE_CTX_GRX_N0
PCIE_CRX_GTX_P1 AA9 P_GFX_RXN0 P_GFX_TXN0 AA3 PCIE_CTX_C_GRX_P1 0.1U_0402_16V7K 1 2 CV205 PX@ PCIE_CTX_GRX_P1
PCIE_CRX_GTX_N1 AA8 P_GFX_RXP1 P_GFX_TXP1 AA2 PCIE_CTX_C_GRX_N1 0.1U_0402_16V7K 1 2 CV203 PX@ PCIE_CTX_GRX_N1
PCIE_CRX_GTX_P2 AA5 P_GFX_RXN1 P_GFX_TXN1 Y5 PCIE_CTX_C_GRX_P2 0.1U_0402_16V7K 1 2 CV204 PX@ PCIE_CTX_GRX_P2
PCIE_CRX_GTX_N2 AA6 P_GFX_RXP2 P_GFX_TXP2 Y4 PCIE_CTX_C_GRX_N2 0.1U_0402_16V7K 1 2 CV212 PX@ PCIE_CTX_GRX_N2
1 PCIE_CRX_GTX_P3 Y8 P_GFX_RXN2 P_GFX_TXN2 Y2 PCIE_CTX_C_GRX_P3 0.1U_0402_16V7K 1 2 CV211 PX@ PCIE_CTX_GRX_P3 1
PCIE_CRX_GTX_N3 Y7 P_GFX_RXP3 P_GFX_TXP3 Y1 PCIE_CTX_C_GRX_N3 0.1U_0402_16V7K 1 2 CV213 PX@ PCIE_CTX_GRX_N3
PCIE_CRX_GTX_P4 W9 P_GFX_RXN3 P_GFX_TXN3 W3 PCIE_CTX_C_GRX_P4 0.1U_0402_16V7K 1 2 CV210 PX@ PCIE_CTX_GRX_P4
PCIE_CRX_GTX_N4 W8 P_GFX_RXP4 P_GFX_TXP4 W2 PCIE_CTX_C_GRX_N4 0.1U_0402_16V7K 1 2 CV206 PX@ PCIE_CTX_GRX_N4
PCIE_CRX_GTX_P5 W5 P_GFX_RXN4 P_GFX_TXN4 V5 PCIE_CTX_C_GRX_P5 0.1U_0402_16V7K 1 2 CV207 PX@ PCIE_CTX_GRX_P5
PCIE_CRX_GTX_N5 W6 P_GFX_RXP5 P_GFX_TXP5 V4 PCIE_CTX_C_GRX_N5 0.1U_0402_16V7K 1 2 CV25 PX@ PCIE_CTX_GRX_N5
PCIE_CRX_GTX_P6 V8 P_GFX_RXN5 P_GFX_TXN5 V2 PCIE_CTX_C_GRX_P6 0.1U_0402_16V7K 1 2 CV51 PX@ PCIE_CTX_GRX_P6
PCIE_CRX_GTX_N6 V7 P_GFX_RXP6 P_GFX_TXP6 V1 PCIE_CTX_C_GRX_N6 0.1U_0402_16V7K 1 2 CV24 PX@ PCIE_CTX_GRX_N6
GRAPHICS
PCIE_CRX_GTX_P7 U9 P_GFX_RXN6 P_GFX_TXN6 U3 PCIE_CTX_C_GRX_P7 0.1U_0402_16V7K 1 2 CV214 PX@ PCIE_CTX_GRX_P7
PCIE_CRX_GTX_N7 U8 P_GFX_RXP7 P_GFX_TXP7 U2 PCIE_CTX_C_GRX_N7 0.1U_0402_16V7K 1 2 CV208 PX@ PCIE_CTX_GRX_N7
U5 P_GFX_RXN7 P_GFX_TXN7 T5
U6 P_GFX_RXP8 P_GFX_TXP8 T4
T8 P_GFX_RXN8 P_GFX_TXN8 T2
T7 P_GFX_RXP9 P_GFX_TXP9 T1
R9 P_GFX_RXN9 P_GFX_TXN9 R3
R8 P_GFX_RXP10 P_GFX_TXP10 R2
R5 P_GFX_RXN10 P_GFX_TXN10 P5
R6 P_GFX_RXP11 P_GFX_TXP11 P4
P8 P_GFX_RXN11 P_GFX_TXN11 P2
P7 P_GFX_RXP12 P_GFX_TXP12 P1
N9 P_GFX_RXN12 P_GFX_TXN12 N3
N8 P_GFX_RXP13 P_GFX_TXP13 N2
N5 P_GFX_RXN13 P_GFX_TXN13 M5
N6 P_GFX_RXP14 P_GFX_TXP14 M4
M8 P_GFX_RXN14 P_GFX_TXN14 M2
M7 P_GFX_RXP15 P_GFX_TXP15 M1
P_GFX_RXN15 P_GFX_TXN15
AE5 AD5 PCIE_PTX_DRX_P0 C35 1 2 0.1U_0402_16V7K
<31> PCIE_PRX_DTX_P0 AE6 P_GPP_RXP0 P_GPP_TXP0 AD4 1 2 PCIE_PTX_C_DRX_P0 <31>
PCIE_PTX_DRX_N0 C36 0.1U_0402_16V7K LAN
<31> PCIE_PRX_DTX_N0 AD8 P_GPP_RXN0 P_GPP_TXN0 AD2 PCIE_PTX_DRX_P1 1 2 PCIE_PTX_C_DRX_N0 <31>
C82 0.1U_0402_16V7K
<30> PCIE_PRX_DTX_P1 AD7 P_GPP_RXP1 P_GPP_TXP1 AD1 1 2 PCIE_PTX_C_DRX_P1 <30>
PCIE_PTX_DRX_N1 C103 0.1U_0402_16V7K WLAN
<30> PCIE_PRX_DTX_N1 AC9 P_GPP_RXN1 P_GPP_TXN1 AC3 PCIE_PTX_C_DRX_N1 <30>
2 P_GPP_RXP2 P_GPP_TXP2 2
GPP
AC8 AC2
AC5 P_GPP_RXN2 P_GPP_TXN2 AB5
AC6 P_GPP_RXP3 P_GPP_TXP3 AB4
P_GPP_RXN3 P_GPP_TXN3
AG8 AG2 UMI_TXP0_C C37 1 2 0.1U_0402_16V7K
<11> UMI_RXP0 AG9 P_UMI_RXP0 P_UMI_TXP0 AG3 UMI_TXN0_C 1 2 UMI_TXP0 <11>
C38 0.1U_0402_16V7K
<11> UMI_RXN0 AG6 P_UMI_RXN0 P_UMI_TXN0 AF4 UMI_TXP1_C 1 2 UMI_TXN0 <11>
C39 0.1U_0402_16V7K
<11> UMI_RXP1 AG5 P_UMI_RXP1 P_UMI_TXP1 AF5 1 2 UMI_TXP1 <11>
UMI_TXN1_C C40 0.1U_0402_16V7K
<11> UMI_RXN1 AF7 P_UMI_RXN1 P_UMI_TXN1 AF1 UMI_TXP2_C 1 2 UMI_TXN1 <11>
C41 0.1U_0402_16V7K
<11> UMI_RXP2 AF8 P_UMI_RXP2 P_UMI_TXP2 AF2 UMI_TXN2_C 1 2 UMI_TXP2 <11>
C42 0.1U_0402_16V7K
<11> UMI_RXN2 AE8 P_UMI_RXN2 P_UMI_TXN2 AE2 UMI_TXP3_C 1 2 UMI_TXN2 <11>
C43 0.1U_0402_16V7K
<11> UMI_RXP3 UMI_TXP3 <11>
UMI
AE9 P_UMI_RXP3 P_UMI_TXP3 AE3 UMI_TXN3_C C44 1 2 0.1U_0402_16V7K

<11> UMI_RXN3 P_UMI_RXN3 P_UMI_TXN3 UMI_TXN3 <11>
1 2 P_ZVDDP AG11 AH11 P_ZVSS 1 2
+1.2VS P_ZVDDP P_ZVSS
R1 196_0402_1% R2 196_0402_1%
ME@ LOTES_ACA-ZIF-109-P12-A_FS1R2
3 3
Power Sequence of APU

+1.5V
+2.5VS Group A
+1.5VS
+APU_CORE
Group B
4 +APU_CORE_NB 4
+1.2VS

FS1r2 PCIE/UMI
Custom 0.1
VALGD MB L
A B C D E
A B C D E
1 1
JCPU1B JCPU1C
MEMORY CHANNEL A MEMORY CHANNEL B
<9> DDRA_SMA[15..0] U20 E13 DDRA_SDQ[63..0] <9> <10> DDRB_SMA[15..0] T27 A14 DDRB_SDQ[63..0] <10>
DDRA_SMA0 DDRA_SDQ0 DDRB_SMA0 DDRB_SDQ0
DDRA_SMA1 R20 MA_ADD0 MA_DATA0 J13 DDRA_SDQ1 DDRB_SMA1 P24 MB_ADD0 MB_DATA0 B14 DDRB_SDQ1
DDRA_SMA2 R21 MA_ADD1 MA_DATA1 H15 DDRA_SDQ2 DDRB_SMA2 P25 MB_ADD1 MB_DATA1 D16 DDRB_SDQ2
DDRA_SMA3 P22 MA_ADD2 MA_DATA2 J15 DDRA_SDQ3 DDRB_SMA3 N27 MB_ADD2 MB_DATA2 E16 DDRB_SDQ3
DDRA_SMA4 P21 MA_ADD3 MA_DATA3 H13 DDRA_SDQ4 DDRB_SMA4 N26 MB_ADD3 MB_DATA3 B13 DDRB_SDQ4
DDRA_SMA5 N24 MA_ADD4 MA_DATA4 F13 DDRA_SDQ5 DDRB_SMA5 M28 MB_ADD4 MB_DATA4 C13 DDRB_SDQ5
DDRA_SMA6 N23 MA_ADD5 MA_DATA5 F15 DDRA_SDQ6 DDRB_SMA6 M27 MB_ADD5 MB_DATA5 B16 DDRB_SDQ6
DDRA_SMA7 N20 MA_ADD6 MA_DATA6 E15 DDRA_SDQ7 DDRB_SMA7 M24 MB_ADD6 MB_DATA6 A16 DDRB_SDQ7
DDRA_SMA8 N21 MA_ADD7 MA_DATA7 DDRB_SMA8 M25 MB_ADD7 MB_DATA7
DDRA_SMA9 M21 MA_ADD8 H17 DDRA_SDQ8 DDRB_SMA9 L26 MB_ADD8 C17 DDRB_SDQ8
DDRA_SMA10 U23 MA_ADD9 MA_DATA8 F17 DDRA_SDQ9 DDRB_SMA10 U26 MB_ADD9 MB_DATA8 B18 DDRB_SDQ9
DDRA_SMA11 M22 MA_ADD10 MA_DATA9 E19 DDRA_SDQ10 DDRB_SMA11 L27 MB_ADD10 MB_DATA9 B20 DDRB_SDQ10
DDRA_SMA12 L24 MA_ADD11 MA_DATA10 J19 DDRA_SDQ11 DDRB_SMA12 K27 MB_ADD11 MB_DATA10 A20 DDRB_SDQ11
DDRA_SMA13 AA25 MA_ADD12 MA_DATA11 G16 DDRA_SDQ12 DDRB_SMA13 W26 MB_ADD12 MB_DATA11 E17 DDRB_SDQ12
DDRA_SMA14 L21 MA_ADD13 MA_DATA12 H16 DDRA_SDQ13 DDRB_SMA14 K25 MB_ADD13 MB_DATA12 B17 DDRB_SDQ13
DDRA_SMA15 L20 MA_ADD14 MA_DATA13 H19 DDRA_SDQ14 DDRB_SMA15 K24 MB_ADD14 MB_DATA13 B19 DDRB_SDQ14
MA_ADD15 MA_DATA14 F19 DDRA_SDQ15 MB_ADD15 MB_DATA14 C19 DDRB_SDQ15
DDRA_SBS0# U24 MA_DATA15 DDRB_SBS0# U27 MB_DATA15
<9> DDRA_SBS0# DDRA_SBS1# U21 MA_BANK0 H20 DDRA_SDQ16 <10> DDRB_SBS0# DDRB_SBS1# T28 MB_BANK0 C21 DDRB_SDQ16
<9> DDRA_SBS1# DDRA_SBS2# L23 MA_BANK1 MA_DATA16 F21 DDRA_SDQ17 <10> DDRB_SBS1# DDRB_SBS2# K28 MB_BANK1 MB_DATA16 B22 DDRB_SDQ17
<9> DDRA_SBS2# MA_BANK2 MA_DATA17 J23 DDRA_SDQ18 <10> DDRB_SBS2# MB_BANK2 MB_DATA17 C23 DDRB_SDQ18
<9> DDRA_SDM[7..0] DDRA_SDM0 E14 MA_DATA18 H23 DDRA_SDQ19 <10> DDRB_SDM[7..0] DDRB_SDM0 D14 MB_DATA18 A24 DDRB_SDQ19
DDRA_SDM1 J17 MA_DM0 MA_DATA19 G20 DDRA_SDQ20 DDRB_SDM1 A18 MB_DM0 MB_DATA19 D20 DDRB_SDQ20
DDRA_SDM2 E21 MA_DM1 MA_DATA20 E20 DDRA_SDQ21 DDRB_SDM2 A22 MB_DM1 MB_DATA20 B21 DDRB_SDQ21
DDRA_SDM3 F25 MA_DM2 MA_DATA21 G22 DDRA_SDQ22 DDRB_SDM3 C25 MB_DM2 MB_DATA21 E23 DDRB_SDQ22
DDRA_SDM4 AD27 MA_DM3 MA_DATA22 H22 DDRA_SDQ23 DDRB_SDM4 AF25 MB_DM3 MB_DATA22 B23 DDRB_SDQ23
DDRA_SDM5 AC23 MA_DM4 MA_DATA23 DDRB_SDM5 AG22 MB_DM4 MB_DATA23
2 DDRA_SDM6 AD19 MA_DM5 G24 DDRA_SDQ24 DDRB_SDM6 AH18 MB_DM5 E24 DDRB_SDQ24 2
DDRA_SDM7 AC15 MA_DM6 MA_DATA24 E25 DDRA_SDQ25 DDRB_SDM7 AD14 MB_DM6 MB_DATA24 B25 DDRB_SDQ25
MA_DM7 MA_DATA25 G27 DDRA_SDQ26 MB_DM7 MB_DATA25 B27 DDRB_SDQ26
DDRA_SDQS0 G14 MA_DATA26 G26 DDRA_SDQ27 DDRB_SDQS0 C15 MB_DATA26 D28 DDRB_SDQ27
<9> DDRA_SDQS0 DDRA_SDQS0# H14 MA_DQS_H0 MA_DATA27 F23 DDRA_SDQ28 <10> DDRB_SDQS0 DDRB_SDQS0# B15 MB_DQS_H0 MB_DATA27 B24 DDRB_SDQ28
<9> DDRA_SDQS0# DDRA_SDQS1 G18 MA_DQS_L0 MA_DATA28 H24 DDRA_SDQ29 <10> DDRB_SDQS0# DDRB_SDQS1 E18 MB_DQS_L0 MB_DATA28 D24 DDRB_SDQ29
<9> DDRA_SDQS1 DDRA_SDQS1# H18 MA_DQS_H1 MA_DATA29 E28 DDRA_SDQ30 <10> DDRB_SDQS1 DDRB_SDQS1# D18 MB_DQS_H1 MB_DATA29 D26 DDRB_SDQ30
<9> DDRA_SDQS1# J21 MA_DQS_L1 MA_DATA30 F27 <10> DDRB_SDQS1# E22 MB_DQS_L1 MB_DATA30 C27
DDRA_SDQS2 DDRA_SDQ31 DDRB_SDQS2 DDRB_SDQ31
<9> DDRA_SDQS2 DDRA_SDQS2# H21 MA_DQS_H2 MA_DATA31 <10> DDRB_SDQS2 DDRB_SDQS2# D22 MB_DQS_H2 MB_DATA31
<9> DDRA_SDQS2# DDRA_SDQS3 E27 MA_DQS_L2 AB28 DDRA_SDQ32 <10> DDRB_SDQS2# DDRB_SDQS3 B26 MB_DQS_L2 AG26 DDRB_SDQ32
<9> DDRA_SDQS3 DDRA_SDQS3# E26 MA_DQS_H3 MA_DATA32 AC27 DDRA_SDQ33 <10> DDRB_SDQS3 DDRB_SDQS3# A26 MB_DQS_H3 MB_DATA32 AH26 DDRB_SDQ33
<9> DDRA_SDQS3# DDRA_SDQS4 AE26 MA_DQS_L3 MA_DATA33 AD25 DDRA_SDQ34 <10> DDRB_SDQS3# DDRB_SDQS4 AG24 MB_DQS_L3 MB_DATA33 AF23 DDRB_SDQ34
<9> DDRA_SDQS4 DDRA_SDQS4# AD26 MA_DQS_H4 MA_DATA34 AA24 DDRA_SDQ35 <10> DDRB_SDQS4 DDRB_SDQS4# AG25 MB_DQS_H4 MB_DATA34 AG23 DDRB_SDQ35
<9> DDRA_SDQS4# MA_DQS_L4 MA_DATA35 <10> DDRB_SDQS4# MB_DQS_L4 MB_DATA35
DDRA_SDQS5 AB22 AE28 DDRA_SDQ36 DDRB_SDQS5 AG21 AG27 DDRB_SDQ36
<9> DDRA_SDQS5 DDRA_SDQS5# AA22 MA_DQS_H5 MA_DATA36 AD28 DDRA_SDQ37 <10> DDRB_SDQS5 DDRB_SDQS5# AF21 MB_DQS_H5 MB_DATA36 AF27 DDRB_SDQ37
<9> DDRA_SDQS5# DDRA_SDQS6 AB18 MA_DQS_L5 MA_DATA37 AB26 DDRA_SDQ38 <10> DDRB_SDQS5# DDRB_SDQS6 AG17 MB_DQS_L5 MB_DATA37 AH24 DDRB_SDQ38
<9> DDRA_SDQS6 MA_DQS_H6 MA_DATA38 <10> DDRB_SDQS6 MB_DQS_H6 MB_DATA38
DDRA_SDQS6# AA18 AC25 DDRA_SDQ39 DDRB_SDQS6# AG18 AE24 DDRB_SDQ39
<9> DDRA_SDQS6# DDRA_SDQS7 AA14 MA_DQS_L6 MA_DATA39 <10> DDRB_SDQS6# DDRB_SDQS7 AH14 MB_DQS_L6 MB_DATA39
<9> DDRA_SDQS7 MA_DQS_H7 <10> DDRB_SDQS7 MB_DQS_H7
DDRA_SDQS7# AA15 Y23 DDRA_SDQ40 DDRB_SDQS7# AG14 AE22 DDRB_SDQ40
<9> DDRA_SDQS7# MA_DQS_L7 MA_DATA40 AA23 DDRA_SDQ41 <10> DDRB_SDQS7# MB_DQS_L7 MB_DATA40 AH22 DDRB_SDQ41
DDRA_CLK0 T21 MA_DATA41 Y21 DDRA_SDQ42 DDRB_CLK0 R26 MB_DATA41 AE20 DDRB_SDQ42
<9> DDRA_CLK0 T22 MA_CLK_H0 MA_DATA42 AA20 DDRA_SDQ43 <10> DDRB_CLK0 R27 MB_CLK_H0 MB_DATA42 AH20 DDRB_SDQ43
DDRA_CLK0# DDRB_CLK0#
<9> DDRA_CLK0# DDRA_CLK1 R23 MA_CLK_L0 MA_DATA43 AB24 DDRA_SDQ44 <10> DDRB_CLK0# DDRB_CLK1 P27 MB_CLK_L0 MB_DATA43 AD23 DDRB_SDQ44
<9> DDRA_CLK1 R24 MA_CLK_H1 MA_DATA44 AD24 DDRA_SDQ45 <10> DDRB_CLK1 P28 MB_CLK_H1 MB_DATA44 AD22 DDRB_SDQ45
DDRA_CLK1# DDRB_CLK1#
<9> DDRA_CLK1# MA_CLK_L1 MA_DATA45 AA21 DDRA_SDQ46 <10> DDRB_CLK1# MB_CLK_L1 MB_DATA45 AD21 DDRB_SDQ46
DDRA_CKE0 H28 MA_DATA46 AC21 DDRA_SDQ47 DDRB_CKE0 J26 MB_DATA46 AD20 DDRB_SDQ47
<9> DDRA_CKE0 H27 MA_CKE0 MA_DATA47 <10> DDRB_CKE0 J27 MB_CKE0 MB_DATA47
DDRA_CKE1 DDRB_CKE1
<9> DDRA_CKE1 MA_CKE1 AA19 DDRA_SDQ48 <10> DDRB_CKE1 MB_CKE1 AF19 DDRB_SDQ48
DDRA_ODT0 Y25 MA_DATA48 AC19 DDRA_SDQ49 DDRB_ODT0 W27 MB_DATA48 AE18 DDRB_SDQ49
<9> DDRA_ODT0 DDRA_ODT1 AA27 MA_ODT0 MA_DATA49 AC17 DDRA_SDQ50 <10> DDRB_ODT0 DDRB_ODT1 Y28 MB_ODT0 MB_DATA49 AE16 DDRB_SDQ50
<9> DDRA_ODT1 MA_ODT1 MA_DATA50 AA17 DDRA_SDQ51 <10> DDRB_ODT1 MB_ODT1 MB_DATA50 AH16 DDRB_SDQ51
DDRA_SCS0# V22 MA_DATA51 AB20 DDRA_SDQ52 DDRB_SCS0# V25 MB_DATA51 AG20 DDRB_SDQ52
3 <9> DDRA_SCS0# DDRA_SCS1# AA26 MA_CS_L0 MA_DATA52 Y19 DDRA_SDQ53 <10> DDRB_SCS0# DDRB_SCS1# Y27 MB_CS_L0 MB_DATA52 AG19 DDRB_SDQ53 3
<9> DDRA_SCS1# MA_CS_L1 MA_DATA53 AD18 DDRA_SDQ54 <10> DDRB_SCS1# MB_CS_L1 MB_DATA53 AF17 DDRB_SDQ54
DDRA_SRAS# V21 MA_DATA54 AD17 DDRA_SDQ55 DDRB_SRAS# V24 MB_DATA54 AD16 DDRB_SDQ55
<9> DDRA_SRAS# DDRA_SCAS# W24 MA_RAS_L MA_DATA55 <10> DDRB_SRAS# DDRB_SCAS# V27 MB_RAS_L MB_DATA55
<9> DDRA_SCAS# W23 MA_CAS_L AA16 DDRA_SDQ56 <10> DDRB_SCAS# V28 MB_CAS_L AG15 DDRB_SDQ56
DDRA_SWE# DDRB_SWE#
<9> DDRA_SWE# MA_WE_L MA_DATA56 Y15 DDRA_SDQ57 <10> DDRB_SWE# MB_WE_L MB_DATA56 AD15 DDRB_SDQ57
MEM_MA_RST# H25 MA_DATA57 AA13 DDRA_SDQ58 MEM_MB_RST# J25 MB_DATA57 AG13 DDRB_SDQ58
<9> MEM_MA_RST# MEM_MA_EVENT# T24 MA_RESET_L MA_DATA58 AC13 DDRA_SDQ59 <10> MEM_MB_RST# MEM_MB_EVENT# T25 MB_RESET_L MB_DATA58 AD13 DDRB_SDQ59
<9> MEM_MA_EVENT# MA_EVENT_L MA_DATA59 Y17 DDRA_SDQ60 <10> MEM_MB_EVENT# MB_EVENT_L MB_DATA59 AG16 DDRB_SDQ60
W20 MA_DATA60 AB16 DDRA_SDQ61 MB_DATA60 AF15 DDRB_SDQ61
+MEM_VREF M_VREF MA_DATA61 AB14 DDRA_SDQ62 MB_DATA61 AE14 DDRB_SDQ62
1 2 M_ZVDDIO W21 MA_DATA62 Y13 DDRA_SDQ63 MB_DATA62 AF13 DDRB_SDQ63
+1.5V_APU M_ZVDDIO MA_DATA63 MB_DATA63
R3 39.2_0402_1%
15mil
Q
m
b
d
f
!
u
i
f
n
!
d
m
p
t
f
!
u
p
!
B
Q
V
!
x
j
u
i
j
o
!
2
#
EVENT# pull high 0.75V reference voltage +1.5V_APU
+1.5V_APU
2
4 R4 4
1K_0402_1%
R5 1 2 1K_0402_5% MEM_MA_EVENT# 15mil
1
R6 1 2 1K_0402_5% MEM_MB_EVENT# +MEM_VREF

2
1 2
R7
1K_0402_1% C45 C46 Security Classification Compal Secret Data Compal Electronics, Inc.
1000P_0402_50V7K 0.1U_0402_16V7K 2012/11/13 2013/11/12 Title
2 1 Issued Date Deciphered Date
FS1r2 DDRIII Memory I/F
1
Custom 0.1
VALGD MB L
A B C D E
A B C D E
JCPU1D
ANALOG/DISPLAY/MISC
LVDS@ C47 1 2 0.1U_0402_16V7K DP0_TXP0 L3 D1 DP0_AUXP C48 1 2 0.1U_0402_16V7K LVDS@ To LVDS If not used, pins are left unconnected (DG ref.)
<26> DP0_TXP0_C 1 2 0.1U_0402_16V7K DP0_TXN0 L2 DP0_TXP0 DP0_AUXP D2 DP0_AUXN 1 2 0.1U_0402_16V7K DP0_AUXP_C <26>
LVDS@ C49 C50 LVDS@ Translater 20101111
<26> DP0_TXN0_C DP0_TXN0 DP0_AUXN DP0_AUXN_C <26>
K5 LVDS E1 ML_VGA_AUXP C51 1 2 0.1U_0402_16V7K
K4 DP0_TXP1 DP1_AUXP E2 ML_VGA_AUXN 1 2 ML_VGA_AUXP_C <12>
C52 0.1U_0402_16V7K To FCH
DP0_TXN1 DP1_AUXN ML_VGA_AUXN_C <12> ML_VGA_AUXP R8 2 1 1.8K_0402_5%
K2 D5
K1 DP0_TXP2 DP2_AUXP D6 HDMICLK_NB <29> ML_VGA_AUXN R9 2 1 1.8K_0402_5%
DP0_TXN2 DP2_AUXN HDMIDAT_NB <29> To HDMI
DISPLAY PORT 0
J3 E5
J2 DP0_TXP3 DP3_AUXP E6
Place near APU DP0_TXN3 DP3_AUXN
C53 1 2 0.1U_0402_16V7K DP1_TXP0 H5 F5 DP0_AUXP R10 2 1 1.8K_0402_5%
1 <12> ML_VGA_TXP0 1 2 0.1U_0402_16V7K DP1_TXN0 H4 DP1_TXP0 DP4_AUXP F6 1
C54
<12> ML_VGA_TXN0 DP1_TXN0 DP4_AUXN DP0_AUXN 2 1 1.8K_0402_5%
To FCH R11
DISPLAY PORT MISC.

C55 1 2 0.1U_0402_16V7K DP1_TXP1 H2 G5
<12> ML_VGA_TXP1 1 2 0.1U_0402_16V7K DP1_TXN1 H1 DP1_TXP1 DP5_AUXP G6
C56
<12> ML_VGA_TXN1 DP1_TXN1 DP5_AUXN
C57 1 2 0.1U_0402_16V7K DP1_TXP2 G3 D3
<12> ML_VGA_TXP2 1 2 0.1U_0402_16V7K DP1_TXN2 G2 DP1_TXP2 DP0_HPD E3 DP0_HPD <26> +1.5V_APU
C58
<12> ML_VGA_TXN2 DP1_TXN2 DP1_HPD D7 FCH_CRT_HPD <12>
Asserted as an input to force the
DISPLAY PORT 1
1 2 0.1U_0402_16V7K DP1_TXP3 F2 DP2_HPD E7 TMDS_B_HPD# <29>
C59 processor into the HTC-active state
<12> ML_VGA_TXP3 1 2 0.1U_0402_16V7K DP1_TXN3 F1 DP1_TXP3 DP3_HPD F7
C60
<12> ML_VGA_TXN3 DP1_TXN3 DP4_HPD
2
G7
C61 1 2 0.1U_0402_16V7K DP2_TXP0 L9 DP5_HPD R12
<29> HDMI_TX2+_CK 1 2 0.1U_0402_16V7K DP2_TXN0 L8 DP2_TXP0 C6
C62 1K_0402_5%
<29> HDMI_TX2-_CK DP2_TXN0 DP_BLON B6
C63 1 2 0.1U_0402_16V7K DP2_TXP1 L5 DP_DIGON A6
<29> HDMI_TX1+_CK DP_INT_PWM <26>
1
C64 1 2 0.1U_0402_16V7K DP2_TXN1 L6 DP2_TXP1 DP_VARY_BL
<29> HDMI_TX1-_CK DP2_TXN1 HDMI
C1 DP_AUX_ZVSS R15 1 2 150_0402_1%
C65 1 2 0.1U_0402_16V7K DP2_TXP2 K8 DP_AUX_ZVSS
<29> HDMI_TX0+_CK 1 2 0.1U_0402_16V7K DP2_TXN2 K7 DP2_TXP2 AD12 APU_PROCHOT# 1 2
C66
<29> HDMI_TX0-_CK DP2_TXN2 TEST6 M18 H_PROCHOT# <36,48>
TEST POINT@ R45 0_0402_1%
DISPLAY PORT 2
TEST9 T1
C67 1 2 0.1U_0402_16V7K DP2_TXP3 J6 N18 TEST POINT@ SHORT PAD@
<29> HDMI_CLK+_CK DP2_TXP3 TEST10 T2
C68 1 2 0.1U_0402_16V7K DP2_TXN3 J5 F11 TEST POINT@
<29> HDMI_CLK-_CK DP2_TXN3 TEST14 T3
G11 1K_0804_8P4R_5% TEST POINT@
TEST15 T4
AE11 H11 SD309100180 TEST POINT@
<11> APU_CLK CLKIN_H TEST16 T5
AD11 J11 RP3 TEST POINT@
C61~C68 Close Connector <11> APU_CLK# CLKIN_L TEST17 F12 APU_TEST18
T6
1 8
CLK
AB11 TEST18 G12 APU_TEST19 2 7
<11> APU_DISP_CLK AA11 DISP_CLKIN_H TEST19 J12 APU_TEST20 3 6 +1.5V_APU Indicates to the FCH that a thermal trip
<11> APU_DISP_CLK# DISP_CLKIN_L TEST20 H12 APU_TEST24 4 5
TEST
THERMTRIP shutdown has occurred. Its assertion will cause the FCH to
B3 TEST24 AE10 TEST25_H R21 1 2 510_0402_1% temperature: 125 degree
<48> APU_SVC transition the system to S5 immediately
A3 SVC TEST25_H AD10 TEST25_L R25 1 2 510_0402_1%
<48> APU_SVD SVD TEST25_L +1.2VS
1
L10
2 TEST28_H T7TEST POINT@ 2
C3 M10
T8TEST POINT@ R22 R23
SER.
<48> APU_SVT SVT TEST28_L P19 1K_0402_5% 10K_0402_5%
APU_SIC AG12 TEST30_H R19
APU_SID AH12 SIC TEST30_L K22 APU_TEST31 R27 1 2 39.2_0402_1%
2 2
SID TEST31 T19
TEST32_H
B
RH140 1 2 0_0402_1% SHORT PAD@ AF10 N19
<11> APU_RST# 1 2 0_0402_1% SHORT PAD@ AB12 RESET_L TEST32_L AA12 APU_TEST35 1 2 300_0402_5%
RH141 R29 +1.5V_APU Q2
<11,48> APU_PWRGD PWROK TEST35
E
1
R30 DEBUG@ 2 300_0402_5% APU_THERMTRIP# 3 1 1 2
CTRL
H_THERMTRIP# <13>
C
ESD request AC10 W10 FS1R2 R32 1 2 10K_0402_5% R28 0_0402_1%
<11> APU_PROCHOT# PROCHOT_L FS1R2 +3VALW
APU_THERMTRIP# AE12 AC12 MMBT3904_NL_SOT23-3 SHORT PAD@
2 1 APU_PWRGD ALERT_L AF12 THERMTRIP_L DMAACTIVE_L ALLOW_STOP <11>
ALERT_L 1
100P_0402_50V8J C465 P18
TEST4 T9 TEST POINT@ C438
@ESD@ APU_TDI H10 R18
TDI TEST5 T10 TEST POINT@ ESD@
APU_TDO J10 1000P_0402_50V7K
APU_TCK F10 TDO 2
APU_TMS G10 TCK JTAG
SIT: For ESD requirement
APU_TRST# F9 TMS Y10
APU_DBRDY G9 TRST_L RSVD1 AA10
DBRDY RSVD2
RSVD
APU_DBREQ# H9 Y12
DBREQ_L RSVD3 K21
RSVD4
11/14 Change net name
B4
<48> APU_VDD_SEN_L C5 VSS_SENSE
A4 VDDP_SENSE +1.5V
<48> APU_VDDNB_SEN_H VDDNB_SENSE
Close to Header
SENSE
A5
C4 VDDIO_SENSE RP2
<48> APU_VDD_SEN_H B5 VDD_SENSE 1 8 APU_TDI
VDDR_SENSE 2 7 APU_TMS
Route as differential 3 6 APU_TCK
ME@ LOTES_ACA-ZIF-109-P12-A_FS1R2 4 5 APU_TRST#
with APU_VDD_SEN_L
1K_0804_8P4R_5%
The VDDIO voltage source provides power to the DDR3 output drivers and other SD309100180
3 miscellaneous functions within the processor. VDDIO_SENSE is internally tied to the 3
processor substrate and is used for sensing the memory controller and interface R596 1 2 1K_0402_5% APU_DBREQ#
voltage level at the processor. VDDIO_SENSE can be routed as a single-ended signal,
or it can be routed with VSS_SENSE as its complement.
+1.5V_APU
CPU TSI interface level shift HDT Debug conn

RP9 SD309100180 BSH111, the Vgs is:
1 8 APU_SIC +1.5V
2 7 APU_SID 1 2 0.1U_0402_16V4Z
min = 0.4V
C69 JHDT1
3 6 ALERT_L Max = 1.3V 1 2 APU_TCK
4 5 ALLOW_STOP 1 2
1 R33 2 1 R34 2 3 4 APU_TMS
+1.5VS +3VS 3 4
1K_0804_8P4R_5%
31.6K_0402_1% 30K_0402_1% 5 6 APU_TDI
R348 1DEBUG@ 2 1K_0402_5% ALLOW_STOP 5 6
R52 1 2 300_0402_5% APU_RST# 7 8 APU_TDO
7 8
2
G
R56 1 2 300_0402_5% APU_PWRGD Q3 APU_TRST# 9 10 APU_PWRGD

9 10
APU_SID 3 1 To EC RP1 11 12 APU_RST#
1 2 1K_0402_5% APU_SVT EC_SMB_DA2_SUS <36> 8 1 11 12
R40
S
DEBUG@ 7 2 13 14 APU_DBRDY
R35 1 2 1K_0402_5% APU_SVC BSH111 1N_SOT23-3 6 3 13 14
DEBUG@ 5 4 15 16 APU_DBREQ#
R38 1 2 1K_0402_5% APU_SVD 15 16
DEBUG@ 10K_0804_8P4R_5% 17 18 APU_TEST19
17 18
19 20 APU_TEST18
19 20
2
G
4 Q6 4
APU_SIC 3 1 To EC SAMTE_ASP-136446-07-B
EC_SMB_CK2_SUS <36>
ME@
S
BSH111 1N_SOT23-3

FS1r2 Display/MISC/HDT
Custom 0.1
VALGD MB L
A B C D E
A B C D E
Power Name Consumption

VDD
+APU_CORE 60A JCPU1F
VDDNB J20 A19
+APU_CORE L4 VSS_1 VSS_73 A21
+APU_CORE_NB 29A R7 VSS_2 VSS_74 A23
W18 VSS_3 VSS_75 A25
VDDIO VSS_4 VSS_76
A15 A7
+1.5V 3.2A VSS_5 VSS_77
C70
0.22U_0402_6.3V6K
C75
0.22U_0402_6.3V6K
C71
0.01U_0402_16V7K
C72
0.01U_0402_16V7K
C76
0.01U_0402_16V7K
C73
180P_0402_50V8J
C74
180P_0402_50V8J
AB17 AA4
AC22 VSS_6 VSS_78 AA7
VDDP / VDDR 1 1 1 1 1 1 1 VSS_7 VSS_79
+APU_CORE JCPU1E +APU_CORE AE21 AB13
+1.2VS 5A / 3.5A AF24 VSS_8 VSS_80 AB15
F8 R11 AH23 VSS_9 VSS_81 AB19
VDDA VDD_1 VDD_32 2 2 2 2 2 2 2 VSS_10 VSS_82
1 H6 T10 AH25 AB21 1
+2.5VS 0.5A J1 VDD_2 VDD_33 H8 B7 VSS_11 VSS_83 AB23
J14 VDD_3 VDD_34 G1 C14 VSS_12 VSS_84 AB25
P6 VDD_4 VDD_35 U11 C16 VSS_13 VSS_85 AB27
P10 VDD_5 VDD_36 W11 C2 VSS_14 VSS_86 AB9
J16 VDD_6 VDD_37 W13 C20 VSS_15 VSS_87 AC14
J18 VDD_7 VDD_38 W15 +APU_CORE_NB C22 VSS_16 VSS_88 AC16
J9 VDD_8 VDD_39 W17 C24 VSS_17 VSS_89 AC18
K19 VDD_9 VDD_40 W19 C26 VSS_18 VSS_90 AC20
K3 VDD_10 VDD_41 AB3 C28 VSS_19 VSS_91 AC24
VDD_11 VDD_42 VSS_20 VSS_92
C77
0.22U_0402_6.3V6K
C78
0.22U_0402_6.3V6K
C79
180P_0402_50V8J
C80
180P_0402_50V8J
C81
180P_0402_50V8J
K17 AD3 D13 AC26
M3 VDD_12 VDD_43 AD6 D15 VSS_21 VSS_93 AC28
VDD_13 VDD_44 1 1 1 1 1 VSS_22 VSS_94
K6 AE1 D17 AC4
V10 VDD_14 VDD_45 L1 D19 VSS_23 VSS_95 AC7
V18 VDD_15 VDD_46 Y6 D23 VSS_24 VSS_96 AD9
V3 VDD_16 VDD_47 M6 2 2 2 2 2 D25 VSS_25 VSS_97 AE13
F3 VDD_17 VDD_48 N11 D27 VSS_26 VSS_98 AE15
L18 VDD_18 VDD_49 N1 E4 VSS_27 VSS_99 AE17
V6 VDD_19 VDD_50 T3 E9 VSS_28 VSS_100 M9
W1 VDD_20 VDD_51 T6 F14 VSS_29 VSS_101 N10
T18 VDD_21 VDD_52 U19 (330uF_6.3V_4.2L_ESR17m)*1=(SF000002Z00) F16 VSS_30 VSS_102 N4
Y14 VDD_22 VDD_53 U1 +1.5V_APU F18 VSS_31 VSS_103 N7
AA1 VDD_23 VDD_54 Y16 F20 VSS_32 VSS_104 R10
AB6 VDD_24 VDD_55 Y18 F22 VSS_33 VSS_105 R4
AC1 VDD_25 VDD_56 Y3 F26 VSS_34 VSS_106 T11
C83
22U_0603_6.3V6M
C84
22U_0603_6.3V6M
C85
22U_0603_6.3V6M
C86
22U_0603_6.3V6M
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
C91
0.22U_0402_6.3V6K
C92
0.22U_0402_6.3V6K
C93
0.22U_0402_6.3V6K
C94
0.22U_0402_6.3V6K
C95
0.22U_0402_6.3V6K
C96
0.22U_0402_6.3V6K
C97
180P_0402_50V8J
C98
330U_2.5V_M
R1 D4 1 F28 T9
C87
C88
C89
C90
P3 F4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 G13 U10
K10 VDD_28 VDD_59 AF6 + G15 VSS_37 VSS_109 U18
H3 VDD_29 VDD_60 AF3 G17 VSS_38 VSS_110 U4
M19 VDD_30 VDD_61 L11 G19 VSS_39 VSS_111 U7
VDD_31 VDD_62 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 G21 VSS_40 VSS_112 V11
G23 VSS_41 VSS_113 AE19
2 C8 C11 G25 VSS_42 VSS_114 AE23 2
+APU_CORE_NB VDDNB_1 VDDNB_13 +APU_CORE_NB VSS_43 VSS_115
D10 C12 G4 AE25
B8 VDDNB_2 VDDNB_14 D9 J22 VSS_44 VSS_116 AE27
B12 VDDNB_3 VDDNB_15 D8 J24 VSS_45 VSS_117 AE4
C9 VDDNB_4 VDDNB_16 D12 J4 VSS_46 VSS_118 AE7
A9 VDDNB_5 VDDNB_17 D11 J7 VSS_47 VSS_119 AF14
A10 VDDNB_6 VDDNB_18 B11 K11 VSS_48 VSS_120 AF16
A8 VDDNB_7 VDDNB_19 A12 K14 VSS_49 VSS_121 AF18
VDDNB_8 VDDNB_20
across VDDIO and VSS VSS_50 VSS_122
A11 B10 +1.5V K9 AF20
VDDNB_9 VDDNB_21 split VSS_51 VSS_123
E10 E12 AC11 AF22
E11 VDDNB_10 VDDNB_22 B9 L19 VSS_52 VSS_124 AF26
C10 VDDNB_11 VDDNB_23 L7 VSS_53 VSS_125 AF28
VDDNB_12 VSS_54 VSS_126
C101
0.22U_0402_6.3V6K
C102
0.22U_0402_6.3V6K
C104
180P_0402_50V8J
C114
180P_0402_50V8J
K13 +VDDNB_CAP M11 AF9
VDDNB_CAP_1 K12 AF11 VSS_55 VSS_127 AG4
VDDNB_CAP_2 1 1 1 1 VSS_56 VSS_128
22U_0603_6.3V6M
C99
C100
22U_0603_6.3V6M
C105
180P_0402_50V8J
V19 AG7
V9 VSS_57 VSS_129 AH13
1 1 1 VSS_58 VSS_130
W16 AH15
H26 T23 2 2 2 2 W4 VSS_59 VSS_131 AH17
+1.5V_APU VDDIO_1 VDDIO_19 +1.5V_APU VSS_60 VSS_132
K20 T26 W7 AH19
J28 VDDIO_2 VDDIO_20 U22 2 2 2 Y11 VSS_61 VSS_133 AH21
K23 VDDIO_3 VDDIO_21 U25 Y20 VSS_62 VSS_134 P9
K26 VDDIO_4 VDDIO_22 U28 Y22 VSS_63 VSS_135 C18
L22 VDDIO_5 VDDIO_23 Y26 Y9 VSS_64 VSS_136 D21
L25 VDDIO_6 VDDIO_24 T20 A17 VSS_65 VSS_137 W14
L28 VDDIO_7 VDDIO_25 R28 A13 VSS_66 VSS_138 P11
M20 VDDIO_8 VDDIO_26 R25 K16 VSS_67 VSS_139 C7
M23 VDDIO_9 VDDIO_27 R22 F24 VSS_68 VSS_140 E8
M26 VDDIO_10 VDDIO_28 V20 G8 VSS_69 VSS_141 K18
N22 VDDIO_11 VDDIO_29 V23 H7 VSS_70 VSS_142 W12
N25 VDDIO_12 VDDIO_30 V26 Northbridge Power Pins J8 VSS_71 VSS_143
N28 VDDIO_13 VDDIO_31 W22 for Remote Decoupling VSS_72
P20 VDDIO_14 VDDIO_32 W25 JUMP@
3 P23 VDDIO_15 VDDIO_33 W28 J2 LOTES_ACA-ZIF-109-P12-A_FS1R2 3
P26 VDDIO_16 VDDIO_34 Y24 1 2
VDDIO_17 VDDIO_35 +1.5V +1.5V_APU
AA28 G28
+1.2VS VDDIO_18 VDDIO_36 ME@
VDDP decoupling PAD-OPEN 4x4m
AH6 AG10
AH5 VDDP_1 VDDR_1 AH8 VDDR decoupling
Need Short
VDDP_2 VDDR_2
180P_0402_50V8J
180P_0402_50V8J
AH4 AH9
VDDP_3 VDDR_3
C106
C107
C108
0.22U_0402_6.3V6K
C109
0.22U_0402_6.3V6K
AH3 AH10 JUMP@

VDDP_4 VDDR_4 +1.2VS
1 1 1 1 AH7 J3
VDDP_5
C110
180P_0402_50V8J
C111
180P_0402_50V8J
C112
1000P_0402_50V7K
C116
0.22U_0402_6.3V6K
C117
0.22U_0402_6.3V6K
1 2
+1.5V +1.5V_APU
AB10 1 1 1 1 1
VDDA PAD-OPEN 4x4m
2 2 2 2
2 2 2 2 2 SIT:Need Short
LOTES_ACA-ZIF-109-P12-A_FS1R2
ME@ Demo Board Capacitor
APU_CORE CORE_NB CORE_NB_CAP VDDIO_SUS
22uF x 10 22uF x 2 22uF x 2 (CPU side)
0.22uF x 2 10uF x 1 180pF x 1 22uF x 4
0.01uF x 3 0.22uF x 2 4.7uF x 4
180pF x 2 180pF x 3 0.22uF x 6 +2(split)
180pF x 1 + 2(split)
4
VDDP VDDR VDDA VDDIO_SUS 4
+2.5VS L1 40mil 0.22uF x 2 0.22uF x 2 4.7uF x 1 (DIMM x2)
FBMA-L11-201209-221LMA30T_0805 180pF x 2 1nF x 4 0.22uF x 1 100uF x 2
2 1 +VDDA
180pF x 2 3.3nF x 1 0.1uF x 12
C118
3300P_0402_50V7K
C119
0.22U_0402_6.3V6K
C120
4.7U_0402_6.3V6M
1 1
1

2
2 2
FS1r2 PWR/GND
Custom 0.1
Check DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS VALGD MB L
A B C D E
A B C D E
+1.5V +1.5V
+VREF_DQ
JDIMM1
1 2
3 VREF_DQ VSS1 4 DDRA_SDQ4 DDRA_SDQ[0..63]
DDRA_SDQ0 5 VSS2 DQ4 6 DDRA_SDQ5 DDRA_SDQ[0..63] <6>
DDRA_SDQ1 7 DQ0 DQ5 8 DDRA_SDM[0..7]
DQ1 VSS3 DDRA_SDM[0..7] <6>
9 10 DDRA_SDQS0#
DDRA_SDM0 11 VSS4 DQS#0 12 DDRA_SDQS0 DDRA_SDQS0# <6> DDRA_SMA[0..15]
DM0 DQS0 DDRA_SDQS0 <6> DDRA_SMA[0..15] <6>
13 14
DDRA_SDQ2 15 VSS5 VSS6 16 DDRA_SDQ6
DDRA_SDQ3 17 DQ2 DQ6 18 DDRA_SDQ7
19 DQ3 DQ7 20
1 DDRA_SDQ8 21 VSS7 VSS8 22 DDRA_SDQ12 1
25 DQ9 DQ13 26
DDRA_SDQS1# 27 VSS9 VSS10 28 DDRA_SDM1
<6> DDRA_SDQS1# 29 DQS#1 DM1 30
DDRA_SDQS1 MEM_MA_RST#
<6> DDRA_SDQS1 31 DQS1 RESET# 32 MEM_MA_RST# <6>
DDRA_SDQ11 35 DQ10 DQ14 36 DDRA_SDQ15 +1.5V
Place near DIMM1
37 DQ11 DQ15 38
DDRA_SDQ16 39 VSS13 VSS14 40 DDRA_SDQ20 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
DQ17 DQ21 2 2 2 2 2 2
43 44
DDRA_SDQS2# 45 VSS15 VSS16 46 DDRA_SDM2 C121 C122 C123 C124 C125 C126
<6> DDRA_SDQS2# DDRA_SDQS2 47 DQS#2 DM2 48
<6> DDRA_SDQS2 49 DQS2 VSS17 50 1 1 1 1 1 1
DDRA_SDQ22
DDRA_SDQ18 51 VSS18 DQ22 52 DDRA_SDQ23 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
DDRA_SDQ19 53 DQ18 DQ23 54
55 DQ19 VSS19 56 DDRA_SDQ28
DDRA_SDQ24 57 VSS20 DQ28 58 DDRA_SDQ29
DDRA_SDQ25 59 DQ24 DQ29 60
61 DQ25 VSS21 62 DDRA_SDQS3#
DDRA_SDM3 63 VSS22 DQS#3 64 DDRA_SDQS3 DDRA_SDQS3# <6>
65 DM3 DQS3 66 DDRA_SDQS3 <6>
71 DQ27 DQ31 72
VSS25 VSS26
DDRA_CKE0 73 74 DDRA_CKE1
<6> DDRA_CKE0 75 CKE0 CKE1 76 DDRA_CKE1 <6>
77 VDD1 VDD2 78 DDRA_SMA15
2 DDRA_SBS2# 79 NC1 A15 80 DDRA_SMA14 2
<6> DDRA_SBS2# 81 BA2 A14 82
DDRA_SMA12 83 VDD3 VDD4 84 DDRA_SMA11
DDRA_SMA9 85 A12/BC# A11 86 DDRA_SMA7
87 A9 A7 88
DDRA_SMA5 91 A8 A6 92 DDRA_SMA4
93 A5 A4 94
DDRA_SMA1 97 A3 A2 98 DDRA_SMA0 +1.5V +1.5V
99 A1 A0 100
DDRA_CLK0 101 VDD9 VDD10 102 DDRA_CLK1
<6> DDRA_CLK0 CK0 CK1 DDRA_CLK1 <6>
2
DDRA_CLK0# 103 104 DDRA_CLK1#
<6> DDRA_CLK0# 105 CK0# CK1# 106 DDRA_CLK1# <6>
R65 R66
DDRA_SMA10 107 VDD11 VDD12 108 DDRA_SBS1# +VREF_DQ 1K_0402_1% +VREF_CA 1K_0402_1%
DDRA_SBS0# 109 A10/AP BA1 110 DDRA_SRAS# DDRA_SBS1# <6>
<6> DDRA_SBS0# 111 BA0 RAS# 112 DDRA_SRAS# <6>
15mil 15mil
1
DDRA_SWE# 113 VDD13 VDD14 114 DDRA_SCS0# +VREF_DQ +VREF_CA
<6> DDRA_SWE# 115 WE# S0# 116 DDRA_SCS0# <6>
DDRA_SCAS# DDRA_ODT0
<6> DDRA_SCAS# CAS# ODT0 DDRA_ODT0 <6>
1000P_0402_50V7K
1000P_0402_50V7K
117 118
0.1U_0402_16V4Z
0.1U_0402_16V4Z
DDRA_SMA13 119 VDD15 VDD16 120 DDRA_ODT1
A13 ODT1 DDRA_ODT1 <6>
2
DDRA_SCS1# 121 122 1 1 1 1
<6> DDRA_SCS1# 123 S1# NC2 124 C127 C128 R67 C129 C130 R68
125 VDD17 VDD18 126 1K_0402_1% 1K_0402_1%
NCTEST VREF_CA +VREF_CA
127 128
DDRA_SDQ32 129 VSS27 VSS28 130 DDRA_SDQ36 2 2 2 2
1
133 DQ33 DQ37 134
<6> DDRA_SDQS4 139 DQS4 VSS31 140 DDRA_SDQ38
3 DDRA_SDQ35 143 DQ34 DQ39 144 3
DDRA_SDQ41 149 DQ40 DQ45 150
161 DQ43 DQ47 162
167 DQ49 DQ53 168
<6> DDRA_SDQS6 173 DQS6 VSS43 174 DDRA_SDQ54
DDRA_SDQ51 177 DQ50 DQ55 178
DDRA_SDQ57 183 DQ56 DQ61 184
195 DQ59 DQ63 196
DDRA_SA0 197 VSS51 VSS52 198 MEM_MA_EVENT#
SA0 EVENT# MEM_MA_EVENT# <6>
199 200
+3VS 201 VDDSPD SDA 202 FCH_SDATA0 <10,13,30>
203 SA1 SCL 204 FCH_SCLK0 <10,13,30>
VTT1 VTT2 +0.75VS
1 1
4 205 206 4
C131 C132 G1 G2
2.2U_0603_6.3V6K 0.1U_0402_16V4Z FOX_AS0A626-U8SN-7F
2 2 ME@

standard H:8mm THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRIII SO-DIMM 1
Custom 0.1
<Address: 00> DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
VALGD MB L
A B C D E
A B C D E
+1.5V +1.5V
+VREF_DQ JDIMM2
1 2
3 VREF_DQ VSS1 4 DDRB_SDQ4 DDRB_SDQ[0..63]
DDRB_SDQ0 5 VSS2 DQ4 6 DDRB_SDQ5 DDRB_SDQ[0..63] <6>
DDRB_SDQ1 7 DQ0 DQ5 8 DDRB_SDM[0..7]
DQ1 VSS3 DDRB_SDM[0..7] <6>
9 10 DDRB_SDQS0#
DDRB_SDM0 11 VSS4 DQS#0 12 DDRB_SDQS0 DDRB_SDQS0# <6> DDRB_SMA[0..15]
DM0 DQS0 DDRB_SDQS0 <6> DDRB_SMA[0..15] <6>
13 14
DDRB_SDQ2 15 VSS5 VSS6 16 DDRB_SDQ6
DDRB_SDQ3 17 DQ2 DQ6 18 DDRB_SDQ7
19 DQ3 DQ7 20
1 DDRB_SDQ8 21 VSS7 VSS8 22 DDRB_SDQ12 +VREF_DQ 1
DDRB_SDQ9 23 DQ8 DQ12 24 DDRB_SDQ13 +VREF_CA
25 DQ9 DQ13 26
DDRB_SDQS1# 27 VSS9 VSS10 28 DDRB_SDM1
15mil 15mil
<6> DDRB_SDQS1# 29 DQS#1 DM1 30
DDRB_SDQS1 MEM_MB_RST# +VREF_DQ +VREF_CA
<6> DDRB_SDQS1 31 DQS1 RESET# 32 MEM_MB_RST# <6>
VSS11 VSS12
1000P_0402_50V7K
1000P_0402_50V7K
DDRB_SDQ10 33 34 DDRB_SDQ14
DQ10 DQ14
0.1U_0402_16V4Z
0.1U_0402_16V4Z
DDRB_SDQ11 35 36 DDRB_SDQ15
37 DQ11 DQ15 38
VSS13 VSS14 1 1 1 1
C133
C134
C135
DDRB_SDQ16 39 40 DDRB_SDQ20 C136
43 DQ17 DQ21 44
DDRB_SDQS2# 45 VSS15 VSS16 46 DDRB_SDM2 2 2 2 2
<6> DDRB_SDQS2# DDRB_SDQS2 47 DQS#2 DM2 48
<6> DDRB_SDQS2 49 DQS2 VSS17 50 DDRB_SDQ22
DDRB_SDQ18 51 VSS18 DQ22 52 DDRB_SDQ23
DDRB_SDQ19 53 DQ18 DQ23 54
55 DQ19 VSS19 56 DDRB_SDQ28
DDRB_SDQ25 59 DQ24 DQ29 60
61 DQ25 VSS21 62 DDRB_SDQS3#
DDRB_SDM3 63 VSS22 DQS#3 64 DDRB_SDQS3 DDRB_SDQS3# <6>
65 DM3 DQS3 66 DDRB_SDQS3 <6>
71 DQ27 DQ31 72
VSS25 VSS26
DDRB_CKE0 73 74 DDRB_CKE1
Place near DIMM2
<6> DDRB_CKE0 75 CKE0 CKE1 76 DDRB_CKE1 <6>
+1.5V
77 VDD1 VDD2 78 DDRB_SMA15
2 DDRB_SBS2# 79 NC1 A15 80 DDRB_SMA14 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2
<6> DDRB_SBS2# 81 BA2 A14 82
VDD3 VDD4 2 2 2 2 2 2
DDRB_SMA12 83 84 DDRB_SMA11
DDRB_SMA9 85 A12/BC# A11 86 DDRB_SMA7 C137 C138 C139 C140 C141 C142
87 A9 A7 88
DDRB_SMA8 89 VDD5 VDD6 90 DDRB_SMA6 1 1 1 1 1 1
DDRB_SMA5 91 A8 A6 92 DDRB_SMA4 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
93 A5 A4 94
DDRB_SMA3 95 VDD7 VDD8 96 DDRB_SMA2
DDRB_SMA1 97 A3 A2 98 DDRB_SMA0
99 A1 A0 100
DDRB_CLK0 101 VDD9 VDD10 102 DDRB_CLK1
<6> DDRB_CLK0 DDRB_CLK0# 103 CK0 CK1 104 DDRB_CLK1# DDRB_CLK1 <6>
<6> DDRB_CLK0# 105 CK0# CK1# 106 DDRB_CLK1# <6>
DDRB_SMA10 107 VDD11 VDD12 108 DDRB_SBS1#
DDRB_SBS0# 109 A10/AP BA1 110 DDRB_SRAS# DDRB_SBS1# <6>
<6> DDRB_SBS0# 111 BA0 RAS# 112 DDRB_SRAS# <6>
+0.75VS
DDRB_SWE# 113 VDD13 VDD14 114 DDRB_SCS0# +1.5V
<6> DDRB_SWE# 115 WE# S0# 116 DDRB_SCS0# <6>
DDRB_SCAS# DDRB_ODT0
<6> DDRB_SCAS# 117 CAS# ODT0 118 DDRB_ODT0 <6>
DDRB_SMA13 119 VDD15 VDD16 120 DDRB_ODT1
A13 ODT1 DDRB_ODT1 <6> 2 1
DDRB_SCS1# 121 122 1
<6> DDRB_SCS1# 123 S1# NC2 124 C143 C144
125 VDD17 VDD18 126 0.1U_0402_16V4Z 4.7U_0603_6.3V6K + C145
NCTEST VREF_CA +VREF_CA 1 2
127 128 @
DDRB_SDQ32 129 VSS27 VSS28 130 DDRB_SDQ36 220U_D2_2VY_R15M
DDRB_SDQ33 131 DQ32 DQ36 132 DDRB_SDQ37 2
133 DQ33 DQ37 134 SGA00004L00
3 DDRB_SDQ35 143 DQ34 DQ39 144 3
DDRB_SDQ41 149 DQ40 DQ45 150 SIT:1/26 change to POLY
161 DQ43 DQ47 162
167 DQ49 DQ53 168
DDRB_SDQ51 177 DQ50 DQ55 178
DDRB_SDQ57 183 DQ56 DQ61 184
R71 10K_0402_5% 195 DQ59 DQ63 196
1 2 DDRB_SA0 197 VSS51 VSS52 198 MEM_MB_EVENT#
SA0 EVENT# MEM_MB_EVENT# <6>
199 200
+3VS 201 VDDSPD SDA 202 FCH_SDATA0 <13,30,9>
203 SA1 SCL 204 FCH_SCLK0 <13,30,9>
VTT1 VTT2 +0.75VS
4 205 206 4
G1 G2
FOX_AS0A626-U4SN-7F
ME@

2012/11/13 2013/11/12 Title
Standard H:4mm Issued Date Deciphered Date
DDRIII SO-DIMM 2
<Address: 01> AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
VALGD MB L
A B C D E
A B C D E
R74/ C146 close to FCH
<16,30,31> APU_PCIE_RST# U1A
SHORT PAD@
2 10_0402_1% HUDSON-2
R92 AE2 AF3
1 R74 2 33_0402_5% A_RST# AD5 PCIE_RST# PCICLK0 AF1 1 2 SHORT PAD@
PCI CLKS
<36>
1 PLT_RST#
2 A_RST# PCICLK1/GPO36 AF5 PCI_CLK1 <15>
RF1 0_0402_1%
150P_0402_50V8J C146 C153 1 2 0.1U_0402_16V7K UMI_RXP0_C AE30 PCICLK2/GPO37 AG2 1 2 SHORT PAD@
<5> UMI_RXP0 1 2 UMI_RXN0_C AE32 UMI_TX0P PCICLK3/GPO38 AF6 1 2 PCI_CLK3 <15>
C147 0.1U_0402_16V7K RF2 0_0402_1% SHORT PAD@
<5> UMI_RXN0 1 2 UMI_RXP1_C AD33 UMI_TX0N PCICLK4/14M_OSC/GPO39 PCI_CLK4 <15>
C148 0.1U_0402_16V7K RF3 0_0402_1%
<5> UMI_RXP1 1 2 UMI_RXN1_C AD31 UMI_TX1P AB5
C154 0.1U_0402_16V7K
<5> UMI_RXN1 1 2 UMI_RXP2_C AD28 UMI_TX1N PCIRST#
C149 0.1U_0402_16V7K
<5> UMI_RXP2 1 2 UMI_RXN2_C AD29 UMI_TX2P
C150 0.1U_0402_16V7K
<5> UMI_RXN2 1 2 AC30 UMI_TX2N AJ3
C151 0.1U_0402_16V7K UMI_RXP3_C
<5> UMI_RXP3 1 2 UMI_RXN3_C AC32 UMI_TX3P AD0/GPIO0 AL5
C152 0.1U_0402_16V7K
1 <5> UMI_RXN3 UMI_TX3N AD1/GPIO1 AG4 1
AB33 AD2/GPIO2 AL6
<5> UMI_TXP0 AB31 UMI_RX0P AD3/GPIO3 AH3
<5> UMI_TXN0 UMI_RX0N AD4/GPIO4
PCI EXPRESS INTERFACES

AB28 AJ5
<5> UMI_TXP1 AB29 UMI_RX1P AD5/GPIO5 AL1
<5> UMI_TXN1 Y33 UMI_RX1N AD6/GPIO6 AN5
<5> UMI_TXP2 Y31 UMI_RX2P AD7/GPIO7 AN6
<5> UMI_TXN2 Y28 UMI_RX2N AD8/GPIO8 AJ1
<5> UMI_TXP3 Y29 UMI_RX3P AD9/GPIO9 AL8
<5> UMI_TXN3 UMI_RX3N AD10/GPIO10 AL3
R75 1 2 590_0402_1% PCIE_CALRP AF29 AD11/GPIO11 AM7
R76 1 2 2K_0402_1% PCIE_CALRN AF31 PCIE_CALRP AD12/GPIO12 AJ6
+VDDAN_11_PCIE PCIE_CALRN AD13/GPIO13 AK7
V33 AD14/GPIO14 AN8
V31 GPP_TX0P AD15/GPIO15 AG9
W30 GPP_TX0N AD16/GPIO16 AM11
W32 GPP_TX1P AD17/GPIO17 AJ10
AB26 GPP_TX1N AD18/GPIO18 AL12
AB27 GPP_TX2P AD19/GPIO19 AK11
AA24 GPP_TX2N AD20/GPIO20 AN12
AA23 GPP_TX3P AD21/GPIO21 AG12
GPP_TX3N AD22/GPIO22 AE12
AA27 AD23/GPIO23 AC12 PCI_AD23 <15>
AA26 GPP_RX0P AD24/GPIO24 AE13 PCI_AD24 <15>
W27 GPP_RX0N AD25/GPIO25 AF13 PCI_AD25 <15>
V27 GPP_RX1P AD26/GPIO26 AH13 PCI_AD26 <15>
PCI INTERFACE
V26 GPP_RX1N AD27/GPIO27 AH14 PCI_AD27 <15>
W26 GPP_RX2P AD28/GPIO28 AD15
W24 GPP_RX2N AD29/GPIO29 AC15
W23 GPP_RX3P AD30/GPIO30 AE16
GPP_RX3N AD31/GPIO31 AN3
CBE0# AJ8
2 R77 CBE1# AN10 2
1 2 2K_0402_1% CLK_CALRN F27 CBE2# AD12
+1.1VS_CKVDD CLK_CALRN CBE3# AG10
FRAME# AK9
DEVSEL# AL10
G30 IRDY# AF10
G28 PCIE_RCLKP TRDY# AE10
PCIE_RCLKN PAR AH1
R26 STOP# AM9
<7> APU_DISP_CLK T26 DISP_CLKP PERR# AH8
APU <7> APU_DISP_CLK# DISP_CLKN SERR# AG15
H33 REQ0# AG13
H31 DISP2_CLKP REQ1#/GPIO40 AF15
DISP2_CLKN REQ2#/CLK_REQ8#/GPIO41 AM17
REQ3#/CLK_REQ5#/GPIO42 T26 TEST POINT@
T24 AD16
<7> APU_CLK T23 APU_CLKP GNT0# AD13
APU <7> APU_CLK# APU_CLKN GNT1#/GPO44 AD21
J30 GNT2#/SD_LED/GPO45 AK17
VGA <16> CLK_PCIE_VGA SLT_GFX_CLKP GNT3#/CLK_REQ7#/GPIO46 T27 TEST POINT@
K29 AD19
<16> CLK_PCIE_VGA# SLT_GFX_CLKN CLKRUN# AH9
H27 LOCK#
H28 GPP_CLK0P AF18
GPP_CLK0N INTE#/GPIO32 AE18 SVT: For EMI Request
J27 INTF#/GPIO33 AC16
K26 GPP_CLK1P INTG#/GPIO34 AD18 SIT: For EMI Request
GPP_CLK1N INTH#/GPIO35 EMI@
F33 C1631 210P_0402_50V8J
<30> CLK_PCIE_WLAN1 F31 GPP_CLK2P EMI@
WLAN
CLOCK GENERATOR
<30> CLK_PCIE_WLAN1# GPP_CLK2N B25 1 2

E33 LPCCLK0 CLK_PCI_EC <15,36>
R85 33_0402_5%
<31> CLK_PCIE_LAN E31 GPP_CLK3P D25
LAN <31> CLK_PCIE_LAN# GPP_CLK3N LPCCLK1 D27 LPC_CLK1 <15>
3 M23 LAD0 C28 LPC_AD0 <36> 3
M24 GPP_CLK4P LAD1 A26 LPC_AD1 <36>
GPP_CLK4N LAD2 LPC_AD2 <36>
A29 LPC_AD3 <36>
M27 LAD3 A31
LPC
M26 GPP_CLK5P LFRAME# B27 LPC_FRAME# <36>

GPP_CLK5N LDRQ0# AE27
N25 LDRQ1#/CLK_REQ6#/GPIO49 AE19 GCLK@
GPP_CLK6P SERIRQ/GPIO48 SERIRQ <36>
N26 32K_X1 R207 1 2 0_0402_5% GCLK_32K
GPP_CLK6N GCLK_32K <38>
R23
Remove 0 ohm on PVT R24 GPP_CLK7P G25
GPP_CLK7N DMA_ACTIVE# E28 APU_PROCHOT#_R 1DEBUG@ 2 0_0402_5% ALLOW_STOP <7>
R86
N27 PROCHOT# E26 APU_PWRGD_R 1 2 SHORT PAD@ APU_PROCHOT# <7>
GPP_CLK8P APU_PG APU_PWRGD <48,7> DVT change
R27 G26 R73 0_0402_1%
GPP_CLK8N LDT_STP# F26
APU
APU_RST# APU_RST# <7>

J26 100P_0402_50V8J 1 2C530
14M_25M_48M_OSC H7 +RTCBATT
S5_CORE_EN F1 C155
@ESD@
RTCCLK F3 RTC_CLK <15,36> 32K_X1 NOGCLK@
GCLK_PCH_25MHZR801 1 2 0_0402_5% 25M_X1 C31 INTRUDER_ALERT# E6 +RTCBATT_R W=20mils 1 2
<38> GCLK_PCH_25MHZ 25M_X1 VDDBT_RTC_G
GCLK@ R88 510_0402_5%
1
G2 1U_0402_6.3V6K
NOGCLK@
NOGCLK@
32K_X1 20P_0402_50V8J
S5 PLUS
32K_X1 1
1
25M_X2 C33 C158 CLRP1 DEBUG@32.768KHZ_12.5PF_CM31532768DZFT R78
25M_X2 SHORT PADS Y1 20M_0402_5%
C157
2
NOGCLK@ G4 32K_X2 2
Need OPEN C156
2
1 2 25M_X1 32K_X2
32K_X2 NOGCLK@
10P_0402_50V8J 21807-A13-HUDSON-M3_FCBGA656
1
4
NOGCLK@ Close to HUDSON-M2/3 20P_0402_50V8J
4
SA000066K70 for Clear CMOS
OSC
NC
X1
R89
A76M Bolton M3
1M_0402_5%
OSC
NC
25MHZ_10PF_X3G025000DC1H
NOGCLK@
2
1
C160
2
NOGCLK@
25M_X2
FCH PCIE/CLK/PCI/LPC/RTC
10P_0402_50V8J Size Document Number Rev
Custom
VALGD MB L 0.1

A B C D E
A B C D E
4
M
B
S
P
I
R
O
M
+3VALW
SPI_CLK_FCH
RP5
8 1 SPI_WP#
1
7 2 SPI_HOLD#
6 3 R94
5 4 GBE_PHY_INTR 33_0402_5%
@EMI@
10K_0804_8P4R_5%
Share with EC
2
U1B
need pop R245 +3VALW
R245 1 2 SPI_SB_CS0# C162
1 HUDSON-2 ShareROM@ 10K_0402_5% 1
22P_0402_50V8J
AK19 AL14 C165 @EMI@
<34> SATA_ITX_C_DRX_P0 AM19 SATA_TX0P SD_CLK/SCLK_2/GPIO73 AN14 1 2
<34> SATA_ITX_C_DRX_N0 SATA_TX0N SD_CMD/SLOAD_2/GPIO74 AJ12
HDD SD_CD/GPIO75
AL20 AH12 SHORT PAD@ U3 0.1U_0402_16V4Z
<34> SATA_DTX_C_IRX_N0 AN20 SATA_RX0N SD_WP/GPIO76 AK13 SPI_SB_CS0#_R R97 1 2 0_0402_1% SPI_SB_CS0# 1 8
<34> SATA_DTX_C_IRX_P0 SATA_RX0P SD_DATA0/SDATI_2/GPIO77 /CS VCC
SD CARD
AM13 SPI_SO_R R98 1 2 0_0402_1% SPI_SO_L 2 7 SPI_HOLD# EMI@
AN22 SD_DATA1/SDATO_2/GPIO78 AH15 SPI_WP# 3 DO/IO1 /HOLD/IO3 6 1
SPI_CLK_FCH R100 20_0402_5% SPI_CLK_FCH_R
<34> SATA_ITX_C_DRX_P1 AL22 SATA_TX1P SD_DATA2/GPIO79 AJ14 4 /WP/IO2 CLK 5 SPI_SI 1 2 0_0402_1% SPI_SI_R
SHORT PAD@
<34> SATA_ITX_C_DRX_N1 SATA_TX1N SD_DATA3/GPIO80 GND DI/IO0
ODD R99
AH20 AC4 W25Q32FVSSIQ_SO8 SHORT PAD@
<34> SATA_DTX_C_IRX_N1 AJ20 SATA_RX1N GBE_COL AD3
<34> SATA_DTX_C_IRX_P1 SATA_RX1P GBE_CRS AD9
AJ22 GBE_MDCK W10
AH22 SATA_TX2P GBE_MDIO AB8
SATA_TX2N GBE_RXCLK AH7
AM23 GBE_RXD3 AF7 ShareROM@
AK23 SATA_RX2N GBE_RXD2 AE7 SPI_SO_L R125 1 2 0_0402_5% FRD#SPI_SO
SATA_RX2P GBE_RXD1 AD7 FRD#SPI_SO <36>
ShareROM@
AH24 GBE_RXD0 AG8 SPI_SI R128 1 2 0_0402_5% FWR#SPI_SI
AJ24 SATA_TX3P GBE_RXCTL/RXDV AD1 FWR#SPI_SI <36>
ShareROM@
SATA_TX3N GBE_RXERR AB7 SPI_CLK_FCH R233 1 2 0_0402_5% SPI_CLK
AN24 GBE_TXCLK AF9 SPI_CLK <36>
ShareROM@
GBE LAN
AL24 SATA_RX3N GBE_TXD3 AG6 SPI_SB_CS0# R238 1 2 0_0402_5% FSEL#SPICS#
SATA_RX3P GBE_TXD2 AE8 FSEL#SPICS# <36>
AL26 GBE_TXD1 AD8
AN26 SATA_TX4P GBE_TXD0 AB9 Co-lay EC share ROM
SATA_TX4N GBE_TXCTL/TXEN AC2
SERIAL ATA
AJ26 GBE_PHY_PD AA7
AH26 SATA_RX4N GBE_PHY_RST# W9 GBE_PHY_INTR
SATA_RX4P GBE_PHY_INTR
AN29
2 AL28 SATA_TX5P V6 SPI_SO_R 2
SATA_TX5N SPI_DI/GPIO164 V5 SPI_SI_R
AK27 SPI_DO/GPIO163 V3 SPI_CLK_FCH_R
SATA_RX5N SPI_CLK/GPIO162
SPI ROM
AM27 T6 SPI_SB_CS0#_R
SATA_RX5P SPI_CS1#/GPIO165 V1 SPI_WP#
AL29 ROM_RST#/SPI_WP#/GPIO161
AN31 NC6
NC7 L30 RP23
AL31 VGA_RED DAC_RED <28> DAC_RED 1 8
AL33 NC8 DAC_GRN 2 7
NC9 L32 DAC_BLU 3 6
AH33 VGA_GREEN DAC_GRN <28> 4 5
AH31 NC10
NC11 M29 150_0804_8P4R_1%
AJ33 VGA_BLUE DAC_BLU <28>
AJ31 NC12
Max = 800 mils
VGA DAC
NC13 M28
VGA_HSYNC/GPO68 N30 CRT_HSYNC <28>
VGA_VSYNC/GPO69 CRT_VSYNC <28>
M33
VGA_DDC_SDA/GPO70 CRT_DDC_DATA <28>
1K_0402_1% 2 1 R105 SATA_CALRP AF28 N32
SATA_CALRP VGA_DDC_SCL/GPO71 CRT_DDC_CLK <28>
+AVDD_SATA 931_0402_1%2 1 R106 SATA_CALRN AF27

SATA_CALRN K31 R107 1 2 715_0402_1%
VGA_DAC_RSET
+3VS R108 1 2 10K_0402_5% AD22

SATA_ACT#/GPIO67 V28
AUX_VGA_CH_P V29 ML_VGA_AUXP_C <7>
AF21 AUX_VGA_CH_N ML_VGA_AUXN_C <7>
VGA MAINLINK
SATA_X1 U28 AUXCAL R109 1 2 100_0402_1%
AUXCAL +VDDAN_11_ML
T31
3 ML_VGA_L0P T33 ML_VGA_TXP0 <7> 3
AG21 ML_VGA_L0N T29 ML_VGA_TXN0 <7>
SATA_X2 ML_VGA_L1P T28 ML_VGA_TXP1 <7>
ML_VGA_L1N R32 ML_VGA_TXN1 <7>
ML_VGA_L2P ML_VGA_TXP2 <7> Module design FCH_CRT_HPD pull up 110K now 10 K
2 1 BT_DISABLE# R30
+3VS ML_VGA_L2N ML_VGA_TXN2 <7>
R36 10K_0402_5% P29
ML_VGA_L3P P28 ML_VGA_TXP3 <7> +FCH_VDDAN_33_DAC
ML_VGA_L3N ML_VGA_TXN3 <7> 2 1
10K_0402_5% R110
C29
ML_VGA_HPD/GPIO229 FCH_CRT_HPD <7>
TEST POINT@
10K_0804_8P4R_5%
AH16 N2 5 4
T12 FANOUT0/GPIO52 VIN0/GPIO175
AM15 6 3
AJ16 FANOUT1/GPIO53 HW MONITOR M3 7 2
FANOUT2/GPIO54 VIN1/GPIO176 GPIO174 8 1
BT_DISABLE# AK15 L2 GPIO177
<30> BT_DISABLE# WL_OFF# AN16 FANIN0/GPIO56 VIN2/SDATI_1/GPIO177 RP6
<30> WL_OFF# AL16 FANIN1/GPIO57 N4 RP8
FANIN2/GPIO58 VIN3/SDATO_1/GPIO178 8 1
P1 GPIO182 7 2
ODD_EN K6 VIN4/SLOAD_1/GPIO179 6 3
<34> ODD_EN TEMPIN0/GPIO171 P3 5 4
RP4 VIN5/SCLK_1/GPIO180
8 1 K5 M1 1 2 DEBUG@ 10K_0804_8P4R_5%
7 2 GPIO177 TEMPIN1/GPIO172 VIN6/GBE_STAT3/GPIO181 R118 10K_0402_5%
6 3 M5 GPIO182
5 4 K3 VIN7/GBE_LED3/GPIO182
TEMPIN2/GPIO173
#11/7 without pull up/ down need to confirm
10K_0804_8P4R_5% AG16
or check chipset pin internal status GPIO174 M6 NC1 AH10
TEMPIN3/TALERT#/GPIO174 NC2 A28
4 NC3 G27 Need to enable internal 4
NC4 L4
NC5 pull down to leave
unconnected
21807-A13-HUDSON-M3_FCBGA656
SA000066K70
A76M Bolton M3
FCH SATA/SPI/VGA/HWM/SD
Custom 0.1
VALGD MB L
A B C D E
A B C D E
+3VALW
U1D
PCIE_RST2 : Reset PCIE device on Hudson2/3
HUDSON-2
2
TEST POINT@T13 AB6 G8
USB MISC
R127 R2 PCIE_RST2#/PCI_PME#/GEVENT4# USBCLK/14M_25M_48M_OSC
<36> EC_LID_OUT# W7 RI#/GEVENT22# B9
10K_0402_5% USB_RCOMP R122 1 2 11.8K_0402_1%
T3 SPI_CS3#/GBE_STAT1/GEVENT21# USB_RCOMP
DEBUG@ <36> PM_SLP_S3# SLP_S3#
W2 H1
<36> PM_SLP_S5#
1
J4 SLP_S5# USB_FSD1P/GPIO186 H3
SYS_RESET# <36> PBTN_OUT# FCH_PWRGD N7 PWR_BTN# USB_FSD1N
<36,48> FCH_PWRGD PWR_GOOD H6
USB 1.1
TEST0 T9 USB_FSD0P/GPIO185 H5
ACPI / WAKE UP EVENTS

TEST1 T10 TEST0 USB_FSD0N
1 TEST2 V9 TEST1/TMS H10 1
TEST2 USB_HSD13P G10
AE22 USB_HSD13N
<36> GATEA20 GA20IN/GEVENT0# K10
AG19 USB_HSD12P J12
<36> KBRST# R9 KBRST#/GEVENT1# USB_HSD12N
H_THERMTRIP# 1 <36> EC_SCI# C26 LPC_PME#/GEVENT3# G12
C439
ESD@
<36> EC_SMI# T5 LPC_SMI#/GEVENT23#
LPC_PD#/GEVENT5#
USB_HSD11P
USB_HSD11N
F12 USB20_P11
USB20_N11
<39>
<39> LP2 Root
1000P_0402_50V7K SYS_RESET# U4
2 K1 SYS_RESET#/GEVENT19# K12
<30> FCH_PCIE_WAKE# V7 WAKE#/GEVENT8# USB_HSD10P K13 USB20_P10 <39>
SVT: For ESD requirement
<7> H_THERMTRIP#
R10 IR_RX1/GEVENT20#
THRMTRIP#/SMBALERT#/GEVENT2#
USB_HSD10N USB20_N10 <39> LP1
WD_PWRGD AF19 B11
WD_PWRGD USB_HSD9P D11
U2 USB_HSD9N
<36> EC_RSMRST# RSMRST# E10
AG24 USB_HSD8P F10
+3VALW CLKREQ_LAN# AE24 CLK_REQ4#/SATA_IS0#/GPIO64 USB_HSD8N
For FCH internal debug use <31> CLKREQ_LAN# CLK_REQ3#/SATA_IS1#/GPIO63
AE26 C10
R129 1 2 2.2K_0402_5% TEST0 AF22 SMARTVOLT1/SATA_IS2#/GPIO50 USB_HSD7P A10
AH17 CLK_REQ0#/SATA_IS3#/GPIO60 USB_HSD7N Root
USB 2.0
DEBUG@
R130 1 2 2.2K_0402_5% TEST1 AG18 SATA_IS4#/FANOUT3/GPIO55 H9
DEBUG@
<35> HDA_SPKR
AF24 SATA_IS5#/FANIN3/GPIO59
SPKR/GPIO66
USB_HSD6P
USB_HSD6N
G9 USB20_P6
USB20_N6
<37>
<37>
Card Reader
R131 1 2 2.2K_0402_5% TEST2 FCH_SCLK0 AD26
GPIO
<10,30,9> FCH_SCLK0 FCH_SDATA0 AD25 SCL0/GPIO43 A8
DEBUG@
<10,30,9> FCH_SDATA0 FCH_SCLK1 T7 SDA0/GPIO47 USB_HSD5P C8
FCH_SDATA1 R7 SCL1/GPIO227 USB_HSD5N
CLKREQ_WLAN# AG25 SDA1/GPIO228 F8
<30> CLKREQ_WLAN# AG22 CLK_REQ2#/FANIN4/GPIO62
CLK_REQ1#/FANOUT4/GPIO61
USB_HSD4P
USB_HSD4N
E8 USB20_P4
USB20_N4
<39>
<39>
Touch Screen
J2
AG26 IR_LED#/LLB#/GPIO184 C6
2
<50> VGA_PWRGD V8 SMARTVOLT2/SHUTDOWN#/GPIO51
DDR3_RST#/GEVENT7#/VGA_PD
USB_HSD3P
USB_HSD3N
A6 USB20_P3
USB20_N3
<27>
<27>
CMOS 2
W8
Y6 GBE_LED0/GPIO183 C5
V10 SPI_HOLD#/GBE_LED1/GEVENT9#
GBE_LED2/GEVENT10#
USB_HSD2P
USB_HSD2N
A5 USB20_P2
USB20_N2
<30>
<30>
WLAN Root
AA8
R132 2 @ 1 0_0402_5% PEG_CLKREQ#_R AF25 GBE_STAT0/GEVENT11# C1
<17> CLK_REQ_VGA# CLK_REQG#/GPIO65/OSCIN/IDLEEXIT# USB_HSD1P C3
USB_HSD1N
Module design ODD_DETECT# without pull up need
M7 E1
+3VALW
check chipset pin internal status
<34> ODD_DA#_FCH
R8 BLINK/USB_OC7#/GEVENT18#
USB_OC6#/IR_TX1/GEVENT6#
USB_HSD0P
USB_HSD0N
E3 USB20_P0
USB20_N0
<37>
<37>
RP1
T1
USB OC
P6 USB_OC5#/IR_TX0/GEVENT17# C16 USBSS_CALRP R133 1 2 1K_0402_1%
<34> ODD_DETECT# F5 USB_OC4#/IR_RX0/GEVENT16# USBSS_CALRP A16
RP14 USBSS_CALRN R134 1 2 1K_0402_1%
+FCH_VDD_11_SSUSB_S
8 1 USB_OC0# P5 USB_OC3#/AC_PRES/TDO/GEVENT15# USBSS_CALRN
7 2 USB_OC1# For RIGHT USB2.0 Port USB_OC1# J7 USB_OC2#/TCK/GEVENT14# A14
6 3 ODD_DETECT# <37> USB_OC1# USB_OC0# T8 USB_OC1#/TDI/GEVENT13# USB_SS_TX3P C14
5 4 ODD_DA#_FCH For LEFT USB3.0 Port <39> USB_OC0# USB_OC0#/SPI_TPM_CS#/TRST#/GEVENT12# USB_SS_TX3N
C12
10K_0804_8P4R_5% USB_SS_RX3P A12
USB_SS_RX3N
R138 1 EMI@ 2 33_0402_5% HDA_BITCLK AB3 D15
<35> HDA_BITCLK_AUDIO AZ_BITCLK USB_SS_TX2P
R140 1 2 33_0402_5% HDA_SDOUT AB1 B15
<35> HDA_SDOUT_AUDIO AA2 AZ_SDOUT USB_SS_TX2N
HDA_SDIN0
HD AUDIO
+3VALW <35> HDA_SDIN0 Y5 AZ_SDIN0/GPIO167 E14
Y3 AZ_SDIN1/GPIO168 USB_SS_RX2P F14
USB 3.0
Y1 AZ_SDIN2/GPIO169 USB_SS_RX2N
R143 1 2 33_0402_5% HDA_SYNC AD6 AZ_SDIN3/GPIO170 F15 USB3_TX1_P
<35> HDA_SYNC_AUDIO AZ_SYNC USB_SS_TX1P USB3_TX1_P <39>
R144 1 2 33_0402_5% HDA_RST# AE4 G15 USB3_TX1_N
<35> HDA_RST_AUDIO# AZ_RST# USB_SS_TX1N USB3_TX1_N <39> LP2
H13 USB3_RX1_P
1 2 10K_0402_5% H_THERMTRIP# USB_SS_RX1P USB3_RX1_P <39>
R146 R364 1 X76@ 2 10K_0402_5% G13 USB3_RX1_N
DEBUG@
GPIO187 +3VALW USB_SS_RX1N USB3_RX1_N <39>
3
R147 1
DEBUG@
2 100K_0402_5% EC_LID_OUT# H: 2G Vram R365 1 X76@
R366 1
2 10K_0402_5%
2 10K_0402_5%
GPIO187
GPIO188
K19
J19 PS2_DAT/SDA4/GPIO187 USB_SS_TX0P
J16
H16
USB3_TX0_P
USB3_TX0_N USB3_TX0_P <39> 3
+3VALW USB3_TX0_N <39>
R148 1 2 10K_0402_5% FCH_PCIE_WAKE# L: 1G Vram J21 PS2_CLK/CEC/SCL4/GPIO188 USB_SS_TX0N
SPI_CS2#/GBE_STAT2/GPIO166 LP1
@
DEBUG@ J15 USB3_RX0_P

USB_SS_RX0P K15 USB3_RX0_N USB3_RX0_P <39>
USB_SS_RX0N USB3_RX0_N <39>
GPIO189 D21 RP7
SHORT PAD@ GPIO190 C20 PS2KB_DAT/GPIO189 H19 8 1
R150 2 1 0_0402_5% D23 PS2KB_CLK/GPIO190 SCL2/GPIO193 G19 7 2
<16> PXS_RST# PS2M_DAT/GPIO191 SDA2/GPIO194
#9/11 need to confirm, Intel using EC R152 2 1 0_0402_5% C22 EMBEDDED CTRL G22 6 3
+3VS <18,36,45,51,52> PXS_PWREN PS2M_CLK/GPIO192 SCL3_LV/GPIO195 G21 5 4 +3VALW
SHORT PAD@ SDA3_LV/GPIO196 E22
EC_PWM0/EC_TIMER0/GPIO197 H22 10K_0804_8P4R_5%
EC_PWM1/EC_TIMER1/GPIO198
1
D PX@ F21 J22 EC_PWM2

KSO_0/GPIO209 EC_PWM2/EC_TIMER2/WOL_EN/GPIO199 EC_PWM2 <15> strap pin Mars
1
R154 1 2 2.2K_0402_5% FCH_SCLK0 2 E20 H21
<36> VGA_GATE# F20 KSO_1/GPIO210 EC_PWM3/EC_TIMER3/GPIO200
G Q70 PX@
R156 1 2 2.2K_0402_5% FCH_SDATA0 A22 KSO_2/GPIO211 K21 GPU_SEL
S 2N7002K_SOT23-3 R234
3
R158 1 2 8.2K_0402_5% CLKREQ_WLAN# E18 KSO_3/GPIO212 KSI_0/GPIO201 K22 100K_0402_5%

R159 1 2 8.2K_0402_5% CLKREQ_LAN# A20 KSO_4/GPIO213 KSI_1/GPIO202 F22
2
J18 KSO_5/GPIO214 KSI_2/GPIO203 F24
H18 KSO_6/GPIO215 KSI_3/GPIO204 E24 GPU_SEL
RP10 G18 KSO_7/GPIO216 KSI_4/GPIO205 B23
KSO_8/GPIO217 KSI_5/GPIO206
1
8 1 WD_PWRGD B21 C24
7 2 FCH_SCLK1 K18 KSO_9/GPIO218 KSI_6/GPIO207 F18 @
6 3 FCH_SDATA1 +3VALW +3VALW D19 KSO_10/GPIO219 KSI_7/GPIO208 R235
5 4 GPIO188 A18 KSO_11/GPIO220 10K_0402_5%
C18 KSO_12/GPIO221
2
10K_0804_8P4R_5% B19 KSO_13/GPIO222
KSO_14/GPIO223
@ 1
@ 1
10K_0402_5%
10K_0402_5%
B17
A24 KSO_15/GPIO224
KSO_16/GPIO225
R160
R161
D17
KSO_17/GPIO226
2
4 4
21807-A13-HUDSON-M3_FCBGA656
GPIO189
GPIO190
A76M Bolton M3
BOARD SA000066K70
Config. GPIO189 GPIO190 Function
R164 1 2 2.2K_0402_5% EC_RSMRST#
PX@ 1
PX@ 1
10K_0402_5%
10K_0402_5%
0 0 PX5 Security Classification Compal Secret Data Compal Electronics, Inc.

R165 1 2 10K_0402_5% HDA_BITCLK
R166
R167
DEBUG@ 0 1 Reserved Issued Date 2012/11/13 Deciphered Date 2013/11/12 Title

R168 1 2 10K_0402_5% HDA_SDIN0
DEBUG@ 1 0 DIS FCH-ACPI/USB/HDA/GPIO
2
R169 1 2 10K_0402_5% PEG_CLKREQ#_R Size Document Number Rev
DEBUG@ 1 1 UMA DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom
VALGD MB L 0.1
A B C D E
A B C D E
+3VS +1.1VS
SHORT PAD@ U1C
1007mA
1 2 +VDDPL_33_SYS +VCC_VDDCR_11 1 2
L2 0_0603_5% 102mA HUDSON-2 R170 0_0805_5%
C166
2.2U_0402_6.3V6M
C167
0.1U_0402_16V7K
C179
0.1U_0402_16V7K
C168
0.1U_0402_16V7K
C180
1U_0402_6.3V6K
C169
1U_0402_6.3V6K
C170
10U_0603_6.3V6M
1 R171 2 +VDDIO_33_PCIGP AB17 T14
+3VS VDDIO_33_PCIGP_1 VDDCR_11_1
22U_0603_6.3V6M
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
220 ohm 1 1 AB18 T17 1 1 1 1 1
VDDIO_33_PCIGP_2 VDDCR_11_2
C171
C172
C173
C174
0_0603_5% AE9 T20
PCI/GPIO I/O
SHORT PAD@ AD10 VDDIO_33_PCIGP_3 VDDCR_11_3 U16
1 1 1 1 VDDIO_33_PCIGP_4 VDDCR_11_4
AG7 U18
2 2 AC13 VDDIO_33_PCIGP_5 VDDCR_11_5 V14 2 2 2 2 2
VDDIO_33_PCIGP_6 VDDCR_11_6
CORE S0
AB12 V17
2 2 2 2 AB13 VDDIO_33_PCIGP_7 VDDCR_11_7 V20
+FCH_VDDAN_33_DAC AB14 VDDIO_33_PCIGP_8 VDDCR_11_8 Y17
1 AB16 VDDIO_33_PCIGP_9 VDDCR_11_9 +1.1VS_CKVDD +1.1VS 1
SHORT PAD@ VDDIO_33_PCIGP_10 42ohm @ 100MHz
47mA 340mA
1 2 +VDDPL_33_MLDAC +VDDPL_33_SYS H24 H26 +1.1VS_CKVDD 1 2
+VDDPL_33_SYS VDDPL_33_SYS VDDAN_11_CLK_1
SHORT PAD@ 20mA J25 R176 0_0603_5%
VDDAN_11_CLK_2
C181
0.1U_0402_16V7K
C182
0.1U_0402_16V7K
C183
1U_0402_6.3V6K
C177
1U_0402_6.3V6K
C178
22U_0603_6.3V6M
R172 0_0402_5% R173 1 2 0_0402_5% +VDDPL_33_DAC V22 K24 SHORT PAD@
0.1U_0402_16V7K
0.1U_0402_16V7K
CLKGEN I/O
+VDDPL_33_MLDAC VDDPL_33_DAC VDDAN_11_CLK_3
C175
C176
12mA L22 1 1 1 1 1
R174 1 2 0_0402_5% +VDDPL_33_ML U22 VDDAN_11_CLK_4 M22
1 1 VDDPL_33_ML VDDAN_11_CLK_5
30mA N21
SHORT PAD@ +FCH_VDDAN_33_DAC T22 VDDAN_11_CLK_6 N22
VDDAN_33_DAC VDDAN_11_CLK_7 P22 2 2 2 2 2
2 2
11mA VDDAN_11_CLK_8
+VDDPL_33_SSUSB_S L18
VDDPL_33_SSUSB_S
14mA
+VDDPL_33_USB_S D7 1088mA +1.1VS
VDDPL_33_USB_S AB24 +VDDAN_11_PCIE 42ohm @ 100MHz
11mA VDDAN_11_PCIE_1
+VDDPL_33_PCIE AH29 Y21 +VDDAN_11_PCIE 1 2
VDDPL_33_PCIE VDDAN_11_PCIE_2 AE25 1 2
12mA VDDAN_11_PCIE_3
PCI EXPRESS
C185
0.1U_0402_16V7K
C186
1U_0402_6.3V6K
C187
22U_0603_6.3V6M
LDO_CAP: Internally generated 1.8V +VDDPL_33_SATA AG28 AD24 JUMP_43X39
VDDPL_33_SATA VDDAN_11_PCIE_4 AB23 J14 JUMP@
supply for the RGB outputs VDDAN_11_PCIE_5 1 1 1
DEBUG@ AA22
1 2 M31 VDDAN_11_PCIE_6 AF26
C184 2.2U_0603_6.3V6K LDO_CAP VDDAN_11_PCIE_7 AG27
+1.1VS L3 SHORT PAD@ VDDAN_11_PCIE_8 2 2 2
7mA
R178 1 2 0_0402_5% +VDDPL_11_DAC V21
BLM15AX221SN1D 0402 VDDPL_11_DAC +1.1VS
1337mA
SM01000MK00 +VDDAN_11_ML AA21 +AVDD_SATA 42ohm @ 100MHz
R179 1 2 0_0603_5% VDDAN_11_SATA_1 Y20 1 2
226mA VDDAN_11_SATA_4 1 2
+3VS +FCH_VDDAN_33_DAC 220 ohm/2A Y22 AB21
VDDAN_11_ML_1 VDDAN_11_SATA_2
C188
4.7U_0402_6.3V6M
C189
0.1U_0402_16V7K
C190
0.1U_0402_16V7K
C191
0.1U_0402_16V7K
C192
1U_0402_6.3V6K
C193
1U_0402_6.3V6K
C194
22U_0603_6.3V6M
L4 30mil SHORT PAD@ V23 AB22 JUMP_43X39
SERIAL ATA
MAIN LINK
1 2 V24 VDDAN_11_ML_2 VDDAN_11_SATA_3 AC22 J15 JUMP@
1 1 1 VDDAN_11_ML_3 VDDAN_11_SATA_5 1 1 1 1
FBMA-L11-201209-221LMA30T_0805 3/1 SIT downsize to 0402, BLM15AX221SN1D (Murata) V25 AC21
VDDAN_11_ML_4 VDDAN_11_SATA_6
C195
2.2U_0603_6.3V6K
C196
0.1U_0402_16V4Z
220 ohm AA20

VDDAN_11_SATA_7 AA18
1 1 2 2 2 VDDAN_11_SATA_8 2 2 2 2
2 AB20 2
VDDAN_11_SATA_9 AC19
AB10 VDDAN_11_SATA_10 +3VALW
2 2 VDDIO_33_GBE_S
59mA
AB11 N18 +VDDIO_33_S R181 1 2 0_0402_5%
AA11 VDDCR_11_GBE_S_1 VDDIO_33_S_1 L19
GBE LAN
VDDCR_11_GBE_S_2 VDDIO_33_S_2
C197
1U_0402_6.3V6K
C198
1U_0402_6.3V6K
C199
2.2U_0402_6.3V6M
M18 SHORT PAD@
R182 1 2 0_0402_5% AA9 VDDIO_33_S_3 V12
VDDIO_GBE_S_1 VDDIO_33_S_4 1 1 1
3.3V_S5 I/O
AA10 V13
3/1 SIT downsize to 0402, BLM15AX221SN1D (Murata) +3VALW SHORT PAD@ VDDIO_GBE_S_2 VDDIO_33_S_5 Y12
L5 VDDIO_33_S_6 Y13
470mA VDDIO_33_S_7 2 2 2
1 2 +VDDAN_33_USB G7 W11
VDDAN_33_USB_S_1 VDDIO_33_S_8
10U_0603_6.3V6M
10U_0603_6.3V6M
FBMA-L11-201209-221LMA30T_0805 H8
+3VALW VDDAN_33_USB_S_2 +3VALW
C200
C201
C202
1U_0402_6.3V6K
C203
1U_0402_6.3V6K
C204
0.1U_0402_16V7K
220 ohm/2A J8 +VDDXL_3.3V
L6 K8 VDDAN_33_USB_S_3
1 1 1 1 1 VDDAN_33_USB_S_4 5mA Tie to +3.3V_S5 rail if USB3 Wake
+VDDPL_33_SSUSB_S K9 G24 +VDDXL_3.3V 21 is supported; otherwise, tie to
BLM15AX221SN1D 0402 M9 VDDAN_33_USB_S_5 VDDXL_33_S L7 0_0603_5%
VDDAN_33_USB_S_6 +3.3V_S0 rail.
C205
2.2U_0402_6.3V6M
C206
0.1U_0402_16V7K
C207
2.2U_0402_6.3V6M
SM01000MK00 M10 SHORT PAD@ 220 ohm
2 2 2 2 2 N9 VDDAN_33_USB_S_7 Hudson-2 designs: Tie to +3.3V_S0
220 ohm 1 1 VDDAN_33_USB_S_8 1
N10 rail.
3/1 SIT downsize to 0402, BLM15AX221SN1D (Murata) M12 VDDAN_33_USB_S_9
N12 VDDAN_33_USB_S_10
2 2 M11 VDDAN_33_USB_S_11 2
+1.1VALW VDDAN_33_USB_S_12
L9 140mA +1.1VALW
+VDDAN_11_USB_S U12 187mA
USB
3/1 SIT downsize to 0402, BLM15AX221SN1D (Murata) BLM15AX221SN1D 0402 U13 VDDAN_11_USB_S_1 N20 +VDDCR_1.1V 1 2
VDDAN_11_USB_S_2 VDDCR_11_S_1
C208
2.2U_0402_6.3V6M
C209
0.1U_0402_16V7K
SM01000MK00 M20 R183 0_0603_5%

+VDDAN_33_USB VDDCR_11_S_2
C211
1U_0402_6.3V6K
C212
1U_0402_6.3V6K
220 ohm 1 1 SHORT PAD@
L77 1 1
+VDDPL_33_USB_S
BLM15AX221SN1D 0402
2 2
C213
2.2U_0402_6.3V6M
C214
0.1U_0402_16V7K
3 SM01000MK00 3/1 SIT downsize to 0402, BLM15AX221SN1D (Murata) 3

2 2
220 ohm 1 1
+1.1VALW
L11 42mA +1.1VALW
2 2 +VDDCR_11V_USB T12 SHORT PAD@
VDDCR_11_USB_S_1 70mA
BLM15AX221SN1D 0402 T13 J24 +VDDPL_11_SYS_S 1 2
VDDCR_11_USB_S_2 VDDPL_11_SYS_S
C215
10U_0603_6.3V6M
C216
0.1U_0402_16V7K
C217
0.1U_0402_16V7K
SM01000MK00 L12 0_0603_5%
0.1U_0402_16V7K
C218
2.2U_0402_6.3V6M
C219
220 ohm 1 1 1
1 1 220 ohm
+3VS
2 2 2
1 2 +VDDPL_33_PCIE 2 2
L13 0_0603_5%
SHORT PAD@ 220 ohm +3VALW
+FCH_VDD_11_SSUSB_S
C220
2.2U_0402_6.3V6M
282mA 12mA
1 SHORT PAD@ P16 M8 +VDDAN_33_HWM R184 1 2 0_0402_5%
1 2 +VDDAN_11_SSUSB M14 VDDAN_11_SSUSB_S_1 VDDAN_33_HWM_S AMD reply:
40mils VDDAN_11_SSUSB_S_2
C224
2.2U_0402_6.3V6M
C225
0.1U_0402_16V7K
N14 SHORT PAD@ VDDAN_33_HWM_S: Please connect
VDDAN_11_SSUSB_S_3
C221
1U_0402_6.3V6K
C222
0.1U_0402_16V7K
C223
0.1U_0402_16V7K
R185 0_0603_5% P13 1 1 it to +3.3V_S5 directly if HWM is not used.

2 P14 VDDAN_11_SSUSB_S_4
1 1 1 VDDAN_11_SSUSB_S_5
USB SS
@ @
2 2
2 2 2
424mA
N16
+3VS N17 VDDCR_11_SSUSB_S_1 +3VS
SHORT PAD@ P17 VDDCR_11_SSUSB_S_2 SHORT PAD@
VDDCR_11_SSUSB_S_3 26mA
1 2 +VDDPL_33_SATA M17 AA4 +VDDIO_AZ R186 1 2 0_0402_5% VDDIO_AZ_S should be tied to
L14 0_0603_5% VDDCR_11_SSUSB_S_4 VDDIO_AZ_S
+3.3/1.5V_S5 rail if Wake on Ring
C227
2.2U_0402_6.3V6M
220 ohm POWER C226 1 2 2.2U_0402_6.3V6M is supported

1 R187 0_0603_5%
4 2 L78 1 1 2 +VDDCR_11_SSUSB 4
+1.1VALW 21807-A13-HUDSON-M3_FCBGA656
C228
10U_0603_6.3V6M
C229
1U_0402_6.3V6K
C230
0.1U_0402_16V7K
C231
0.1U_0402_16V7K
FBMA-L11-201209-221LMA30T_0805
2
42 ohm/4A SHORT PAD@
A76M Bolton M3
SA000066K70
1 1 1 1
2 2 2 2
FCH PWR
Rev
Custom 0.1
VALGD MB L
A B C D E
A B C D E
1 1
U1E
HUDSON-2
DEBUG STRAPS
A3 T25
A33
B7
VSS
VSS
VSS
VSS
T27
U6
STRAP PINS FCH HAS 15K INTERNAL PU FOR PCI_AD[27:23]
B13 VSS VSS U14
D9 VSS VSS U17
D13 VSS VSS U20
VSS VSS PCI_CLK1 PCI_CLK3 PCI_CLK4 CLK_PCI_EC LPC_CLK1 EC_PWM2 RTC_CLK PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 PCI_AD23
E5 U21
E12 VSS VSS U30
E16 VSS VSS U32
VSS VSS PULL ALLOW USE NON_FUSION EC CLKGEN LPC ROM S5 PLUS USE PCI DISABLE USE FC USE DEFAULT DISABLE PCI
E29 V11 PULL
F7 VSS VSS V16 HIGH PCIE GEN2 DEBUG CLOCK MODE ENABLED ENABLED MODE PLL ILA PLL PCIE STRAPS MEM BOOT
F9 VSS VSS V18 STRAPS DISABLED HIGH AUTORUN
F11 VSS VSS W4 DEFAULT DEFAULT DEFAULT DEFAULT DEFAULT DEFAULT DEFAULT DEFAULT
F13 VSS VSS W6
F16 VSS VSS W25
F17 VSS VSS W28
VSS VSS PULL FORCE IGNORE FUSION EC CLKGEN SPI ROM S5 PLUS PULL BYPASS ENABLE BYPASS USE EEPROM ENABLE PCI
F19 Y14
F23 VSS VSS Y16 LOW PCIE GEN1 DEBUG CLOCK DISABLED DISABLE MODE LOW PCI PLL ILA FC PLL PCIE STRAPS MEM BOOT
F25 VSS VSS Y18 STRAP MODE ENABLED AUTORUN
F29 VSS VSS AA6 DEFAULT DEFAULT DEFAULT DEFAULT
G6 VSS VSS AA12
G16 VSS VSS AA13
G32 VSS VSS AA14 +3VS +3VALW
H12 VSS VSS AA16
H15 VSS VSS AA17
H29 VSS VSS AA25
GROUND
J6 VSS VSS AA28

J9 VSS VSS AA30
2 J10 VSS VSS AA32 2
J13 VSS VSS AB25
VSS VSS
1
2
3
4
J28 AC6
J32 VSS VSS AC18 <11> PCI_AD27
RP13
K7 VSS VSS AC28
VSS VSS 10K_0804_8P4R_5% <11> PCI_AD26
K16 AD27
K27 VSS VSS AE6
<11> PCI_AD25
8
7
6
5
K28 VSS VSS AE15
L6 VSS VSS AE21
L12 VSS VSS AE28 <11> PCI_AD24
L13 VSS VSS AF8
L15 VSS VSS AF12 <11> PCI_AD23
L16 VSS VSS AF16
L21 VSS VSS AF33
VSS VSS
R195 2.2K_0402_5%
R196 2.2K_0402_5%
R197 2.2K_0402_5%
R198 2.2K_0402_5%
R199 2.2K_0402_5%
M13 AG30
VSS VSS
1
M16 AG32 +3VS +3VS +3VALW
VSS VSS
Strap@
R189 10K_0402_5%
Strap@
R190 10K_0402_5%
Strap@
R191 10K_0402_5%
M21 AH5
VSS VSS
Strap@
Strap@
Strap@
Strap@
Strap@
M25 AH11
VSS VSS
1
1
N6 AH18
N11 VSS VSS AH19
2
N13 VSS VSS AH21
N23 VSS VSS AH23
N24 VSS VSS AH25 <11> PCI_CLK1
2
2
P12 VSS VSS AH27 +3VALW
VSS VSS <11> PCI_CLK3
R193 10K_0402_5%
P18 AJ18
P20 VSS VSS AJ28
VSS VSS <11> PCI_CLK4
1
Strap@
P21 AJ29
P31 VSS VSS AK21
P33 VSS VSS AK25 <11,36> CLK_PCI_EC
R4 VSS VSS AL18
R11 VSS VSS AM21 <11> LPC_CLK1
2
R25 VSS VSS AM25
3 R28 VSS VSS AN1 <13> EC_PWM2 3
T11 VSS VSS AN18
T16 VSS VSS AN28 <11,36> RTC_CLK
VSS VSS
R200 10K_0402_5%
R204 10K_0402_5%
R205 2.2K_0402_5%
R206 2.2K_0402_5%
T18 AN33
VSS VSS
1
1
Strap@
Strap@
Strap@
N8 T21
VSSAN_HWM VSSPL_DAC L28
VSSAN_DAC
1
2
3
4
K25 K33 RP12

VSSXL VSSANQ_DAC N28
H25 VSSIO_DAC
2
2
VSSPL_SYS R6
EFUSE
8
7
6
5
21807-A13-HUDSON-M3_FCBGA656 10K_0804_8P4R_5%
A76M Bolton M3
SA000066K70
4 4

FCH-VSS/Strap
Rev
Custom 0.1
VALGD MB L
A B C D E
A B C D E
PCIE_CTX_GRX_P[7..0] UV1A PCIE_CRX_GTX_P[7..0]

<5> PCIE_CTX_GRX_P[7..0] PCIE_CRX_GTX_P[7..0] <5>
<5> PCIE_CTX_GRX_N[7..0]
PCIE_CTX_GRX_N[7..0] PART 1 0F 9 PCIE_CRX_GTX_N[7..0]
PCIE_CRX_GTX_N[7..0] <5> LVDS Interface
UV1D
1 1
PCIE_CTX_GRX_P0 AA38 Y33 PCIE_CRX_C_GTX_P0 0.1U_0402_16V7K 1 2 CV1 PX@ PCIE_CRX_GTX_P0 PART 7 0F 9
PCIE_CTX_GRX_N0 Y37 PCIE_RX0P PCIE_TX0P Y32 PCIE_CRX_C_GTX_N0 1 2 CV2 PX@ PCIE_CRX_GTX_N0
0.1U_0402_16V7K
PCIE_RX0N PCIE_TX0N AK27
RSVD/VARY_BL AJ27
Y35 W33 PCIE_CRX_C_GTX_P1 1 2 CV3 PX@ RSVD/DIGON
PCIE_CTX_GRX_P1 0.1U_0402_16V7K PCIE_CRX_GTX_P1
PCIE_CTX_GRX_N1 W36 PCIE_RX1P PCIE_TX1P W32 PCIE_CRX_C_GTX_N1 1 2 CV4 PX@ PCIE_CRX_GTX_N1 LVDS CONTROL
0.1U_0402_16V7K
PCIE_RX1N PCIE_TX1N
PCIE_CTX_GRX_P2 W38 U33 PCIE_CRX_C_GTX_P2 0.1U_0402_16V7K 1 2 CV5 PX@ PCIE_CRX_GTX_P2 AK35

PCIE_CTX_GRX_N2 V37 PCIE_RX2P PCIE_TX2P U32 PCIE_CRX_C_GTX_N2 1 2 CV6 PX@ PCIE_CRX_GTX_N2 TXCBP_DPB3P AL36
0.1U_0402_16V7K
PCIE_RX2N PCIE_TX2N TXCBM_DPB3N
AJ38
PCIE_CTX_GRX_P3 V35 U30 PCIE_CRX_C_GTX_P3 1 2 CV7 PX@ PCIE_CRX_GTX_P3 TX3P_DPB2P AK37
0.1U_0402_16V7K
U36 PCIE_RX3P PCIE_TX3P U29 PCIE_CRX_C_GTX_N3 1 2 CV8 PX@ TX3M_DPB2N
PCIE_CTX_GRX_N3 0.1U_0402_16V7K PCIE_CRX_GTX_N3
PCIE_RX3N PCIE_TX3N AH35
TX4P_DPB1P AJ36
PCIE_CTX_GRX_P4 U38 T33 PCIE_CRX_C_GTX_P4 1 2 CV9 PX@ PCIE_CRX_GTX_P4 TX4M_DPB1N
0.1U_0402_16V7K
PCIE_CTX_GRX_N4 T37 PCIE_RX4P PCIE_TX4P T32 PCIE_CRX_C_GTX_N4 1 2 CV10 PX@ PCIE_CRX_GTX_N4 AG38
0.1U_0402_16V7K
PCIE_RX4N PCIE_TX4N TX5P_DPB0P AH37
TX5M_DPB0N
PCIE_CTX_GRX_P5 T35 T30 PCIE_CRX_C_GTX_P5 0.1U_0402_16V7K 1 2 CV11 PX@ PCIE_CRX_GTX_P5 AF35
PCIE_CTX_GRX_N5 R36 PCIE_RX5P PCIE_TX5P T29 PCIE_CRX_C_GTX_N5 1 2 CV12 PX@ PCIE_CRX_GTX_N5 NC#AF35 AG36
0.1U_0402_16V7K
PCIE_RX5N PCIE_TX5N NC#AG36
LVTMDP
PCIE_CTX_GRX_P6 R38 P33 PCIE_CRX_C_GTX_P6 0.1U_0402_16V7K 1 2 CV13 PX@ PCIE_CRX_GTX_P6
PCIE_CTX_GRX_N6 P37 PCIE_RX6P PCIE_TX6P P32 PCIE_CRX_C_GTX_N6 1 2 CV14 PX@ PCIE_CRX_GTX_N6
0.1U_0402_16V7K
PCIE_RX6N PCIE_TX6N AP34
TXCAP_DPA3P AR34
PCIE_CTX_GRX_P7 P35 P30 PCIE_CRX_C_GTX_P7 1 2 CV15 PX@ PCIE_CRX_GTX_P7 TXCAM_DPA3N
0.1U_0402_16V7K
N36 PCIE_RX7P PCIE_TX7P P29 1 2 CV16 PX@ AW37
PCIE_CTX_GRX_N7 PCIE_CRX_C_GTX_N7 0.1U_0402_16V7K PCIE_CRX_GTX_N7
PCIE_RX7N PCIE_TX7N TX0P_DPA2P AU35
2 TX0M_DPA2N 2
N38 N33 AR37
M37 NC NC N32 TX1P_DPA1P AU39
NC NC TX1M_DPA1N
PCI EXPRESS INTERFACE AP35
M35 N30 TX2P_DPA0P AR35
L36 NC NC N29 TX2M_DPA0N
NC NC AN36
NC AP37
L38 L33 NC
K37 NC NC L32
NC NC
K35 L30 PX@ MARS-XTX M2_FCBGA962

J36 NC NC L29
NC NC
J38 K33
H37 NC NC K32
NC NC
H35 J33
G36 NC NC J32
NC NC
G38 K30
F37 NC NC K29
NC NC
F35 H33
E37 NC NC H32
NC NC
3 3
CLOCK +3VGS
CLK_PCIE_VGA AB35
<11> CLK_PCIE_VGA AA36 PCIE_REFCLKP
CLK_PCIE_VGA#
<11> CLK_PCIE_VGA# PCIE_REFCLKN
5
2
P
CALIBRATION <13> PXS_RST# B 4 GPU_RST#
Y30 RV1 1 PX@ 2 1.69K_0402_1% 1 Y
PCIE_CALR_TX +0.95VGS <11,30,31> APU_PCIE_RST# A
G
PX@
2 PX@ 1 AH16 Y29 RV3 1 PX@ 2 1K_0402_1% UV2
TEST_PG PCIE_CALR_RX +0.95VGS
3
RV2 1K_0402_5% MC74VHC1G08DFT2G SC70 5P
GPU_RST# AA30
PERSTB
1
PX@ PX@ MARS-XTX M2_FCBGA962

RV4
100K_0402_5%
2
4 4

ATI_MarsXT_M2_PCIE/LVDS
Custom 0.1
VALGD MB L
A B C D E
A B C D E
UV1B CONFIGURATION STRAPS RECOMMENDED SETTINGS

PART 2 0F 9 ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE 0= DO NOT INSTALL RESISTOR
1 = INSTALL 10K RESISTOR
MUTI GFX GPIOS ARE USED, THEY MUST NOT CONFLICT DURING RESET X = DESIGN DEPENDANT
TEST POINT@ T31 GENLK_CLK AD29 GENLK_CLK AU24 NA = NOT APPLICABLE
AC29 NC AV23
TEST POINT@ T32 GENLK_VSYNC GENLK_VSYNC NC
AT25 STRAPS STRAPS MLPS DESCRIPTION OF DEFAULT SETTINGS Default Setting
AJ21 NC AR24
SWAPLOCKA DPA NC
AK21 SWAPLOCKB Transmitter Power Savings Enable
AU26 TX_PWRS_ENB PS_1[4] 0:50% Tx output swing X
NC
AV25 1:Full Tx output swing
NC
+3VGS
AR8 AT27 PCIE Transmitter De-emphasis Enable
NC NC
AU8 NC AR26 TX_DEEMPH_EN PS_1[5] 0:Tx de-emphasis disabled X
AP8 NC 2
DBG_CNTL0 GPU_GPIO5 RV5 Strap@ 100K_0402_5%
Strap@1 1:Tx de-emphasis enabled
AW8 NC AR30
1 NC 1
AR3 AT29 PCIE Gen3 Enable
NC NC
AR1 THM_ALERT# RV6 2 Strap@ 2.2K_0402_5%
Strap@1 BIF_GEN3_EN_A PS_1[1] (NOTE:RESERVED for Thames/Seymour and should 1
NC
AU1 DBG_DATA0 AV31 be strapped to 0)
AU3 NC AU30
DBG_DATA1 DPB NC
AW3 DBG_DATA2 0:GEN3 not support at power-on
AP6 AR32 1:GEN3 supported at power-on
DBG_DATA3 NC
AW5 AT31
DBG_DATA4 NC
AU5 DBG_DATA5 VGA control
AR6 AT33 BIF_VGA DIS PS_2[4] 0:VGA controller capacity enabled 0
DBG_DATA6 NC
AW6 DBG_DATA7 AU32 1:VGA controller capacity disabled (for multi-GPU)
NC +3VGS
AU6
DBG_DATA8
AT7 AU14 Serial ROM type or Memory Aperture Size Select
DBG_DATA9 NC
AV7 DBG_DATA10 AV13 JTAG_TRSTB RV7 2 Strap@1 10K_0402_5% ROMIDCFG[2:0] PS_0[3..1] If PS_2[3]=0, defines memory aperture size XXX
AN7 NC 2
DBG_DATA11 JTAG_TDI RV8 Strap@1 10K_0402_5% If PS_2[3]=1, defines ROM type
AV9 DBG_DATA12 AT15 JTAG_TMS RV9 2 Strap@1 10K_0402_5% 100 - 512Kbit M25P05A (ST)
NC
AT9 AR14 101 - 1Mbit M25P10A (ST)
DBG_DATA13 NC
AR10 JTAG_TCK RV10 2 Strap@1 10K_0402_5% 101 - 2Mbit M25P20 (ST)
DBG_DATA14 DPC
AW10 DBG_DATA15 AU16 101 - 4Mbit M25P40 (ST)
AU10 NC AV15
DBG_DATA16 NC 101 - 8Mbit M25P80 (ST)
AP10 DBG_DATA17 100 - 512Kbit Pm25LV010 (Chingis)
AV11 AT17 101 - 1Mbit Pm25LV010 (Chingis)
DBG_DATA18 NC
AT11 AR16
DBG_DATA19 NC
AR12 DBG_DATA20
AW12 AU20 Enable external BIOS ROM device
DBG_DATA21 NC
AU12 DBG_DATA22 AT19 BIOS_ROM_EN PS_2[3] 0:Disabled X
NC
AP12 1:Enabled
DBG_DATA23
AT21
NC
AR20 00 - No audio function
NC
AUD[1] NA 01 - Audio for DP only XX
VGA_SMB_CK2 AJ23 DPD AU22 10 - Audio for DP and HDMI if dongle is detected
SMBCLK SMBus NC
VGA_SMB_DA2 AH23 AV21 AUD[0] NA 11 - Audio for both DP and HDMI
SMBDATA NC
AT23 HDMI must only be enabled on systems that are
NC AR22 legally entitled. It isthe responsibility of the system
NC
AK26 SCL designer to ensure that the system is entitled to
AJ26 I2C support this feature.
SDA
2 AD39 VGA_R 2
R AD37
GENERAL PURPOSE I/O T24 TEST POINT@ CEC_DIS PS_0[4] Reserved for future ASIC 0
GPU_GPIO0 AH20 AVSSN
<50> GPU_GPIO0
AH18
GPIO_0
AE36 VGA_G
AVDD MarsCRB Design NOTE:ALLOW FOR PULLUP PADS FOR THE
GPIO_1 G
@ AN16
GPIO_2 AVSSN
AD35 T25 TEST POINT@ 120ohm 1 1 RESERVED STRAPS BUT DO NOT INSTALL
DV1 RESISTOR
RB751V_SOD323
B
AF37 VGA_B 0.1u 1 1 IF THESE GPIOS ARE USEED, THEY MUST KEEP
1 2 GPU_GPIO5 AH17 AE38 T46 TEST POINT@ LOW AND NOT CONFLICT DURING RESET
<36,43> ACIN
GPU_VID5 AJ17
GPIO_5_AC_BATT
GPIO_6_TACH
AVSSN 1u 1 1
<50> GPU_VID5 AK17 DAC1
AC36
GPIO_7_BLON HSYNC 10u 1 1 RESERVED PS_1[3] Reserved 0
AJ13 HSYNC AC38 VSYNC T34 TEST POINT@
GPIO_8_ROMSO VSYNC
AH15 T36 TEST POINT@ RESERVED PS_1[2] Reserved 0
GPIO_9_ROMSI
AJ16 GPIO_10_ROMSCK
AK16 AB34 RV11 1 PX@ 2 499_0402_1% +AVDD +1.8VGS RESERVED NA Reserved 0
GPIO_11 RSET
AL16
GPIO_12
AM16 GPIO_13 AD34 +AVDD (1.8V@70mA AVDD) 1 2 RESERVED NA Reserved (for Thames/Whistler/Seymour only) 0
AM14 AVDD AE34 LV1 PX@
GPIO_14_HPD2 AVSSQ
GPU_VID1 AM13 BLM15BD121SN1D_0402
CV17
CV18
CV19
GPIO_15_PWRCNTL_0
1U_0402_6.3V6K
10U_0603_6.3V6M
0.1U_0402_16V7K
<50> GPU_VID1 (1.8V@117mA VDD1DI)
AK14 AC33 +VDD1DI 1 1 1 STRAPS TO INDICATE THE NUMBER OF AUDIO
GPIO_16 VDD1DI
THM_ALERT# AG30 AC34 AUD_PORT_CONN_PINSTRAP[2] PS_3[5] CAPABLE DISPLAY OUTPUTS XXX
GPIO_17_THERMAL_INT VSS1DI
AN14 GPIO_18_HPD3 111 = 0 usable endpoints
@ RV12 1 2 10K_0402_5% AM17
GPIO_19_CTF AUD_PORT_CONN_PINSTRAP[1] PS_3[4] 110 = 1 usable endpoints
2 2 2
PX@
PX@
PX@
GPU_VID2 AL13 GPIO_20_PWRCNTL_1 V13 101 = 2 usable endpoints
<50> GPU_VID2 NC
AJ14 U13 AUD_PORT_CONN_PINSTRAP[0] PS_0[5] 100 = 3 usable endpoints
GPIO_21 NC
AK13 AF33 011 = 4 usable endpoints
GPIO_22_ROMCSB NC
CLK_REQ_VGA# AN13 CLKREQB AF32 010 = 5 usable endpoints
<13> CLK_REQ_VGA# NC AA29
NC 001 = 6 usable endpoints
AG21 +VDD1DI +1.8VGS 000 = all endpoints are usable
NC
GPU_VID3 AG32 AC32
<50> GPU_VID3 GPIO_29 NC
GPU_VID4 AG33 1 2
<50> GPU_VID4 GPIO_30
AC31 LV2 PX@
AJ19 NC_SVI2 AD30 BLM15BD121SN1D_0402
CV20
CV21
CV22
GENERICA
1U_0402_6.3V6K
10U_0603_6.3V6M
0.1U_0402_16V7K
NC_SVI2
AK19 GENERICB AD32 1 1 1
NC_SVI2
AJ20
GENERICC
AK20
AJ24
GENERICD VDD1DI MarsCRB Design
GENERICE_HPD4 2 2 2
120ohm 1 1
PX@
PX@
PX@
AH26
GENERICF_HPD5
AH24 GENERICG_HPD6
3
0.1u 1 1 3
PS_0
AM34 PS_0
1u 1 1 MLPS Strap
AC30 10u 1 1
CEC_1
0.60 V level, Please Bits[5:4] Bits[3:1] Capacitor R_pu R_pd
AK24 AD31 PS_1
VREFG Divider ans HPD1 MLPS PS_1
+1.8VGS +VREFG_GPU cap close to ASIC PS_0[5:1] 11 001 NC 8.45K 2K
PX@
2 RV13 1 499_0402_1% +VREFG_GPU AH13 DBG_VREFG PS_2 AG31 PS_2
PX@ PS_1[5:1] 11 000 NC NC 4.75K
2 RV14 1 249_0402_1%
T29
BACO
2 1 0.1U_0402_16V7K PX_EN AL21 AD33 PS_3 PS_2[5:1] 00 000 680 nF NC 4.75K
PX_EN PS_3
CV23 TEST POINT@
PX@ Mapping to VRAM type please refer to page 21
PS_3[5:1] 11 XXX NC X X
DEBUG@
DEBUG DDC/AUX +1.8VGS
1 2 TESTEN AM26 VGA_CLK TEST POINT@
+3VGS
RV18
1 PX@
5.11K_0402_5%
2 AD28
TESTEN
DDC1CLK
DDC1DATA
AN26 VGA_DAT T37
T28
TEST POINT@ DIS:+3VGS
RV19 1K_0402_5% AM27
AUX1P
UMA:+3VS
1
AL27
AUX1N
GPIO_28_FDO MLPS Strap@ Strap@
JTAG_TRSTB AM23 JTAG_TRSTB AM19 X76@ RV20 RV21 RV22 PX@RV23
PX@ RV23
DDC2CLK
H Disable JTAG_TDI AN23 AL19 8.45K_0402_1% 8.45K_0402_1% 8.45K_0402_1% 8.45K_0402_1%
JTAG_TDI DDC2DATA +3VGS
JTAG_TCK AK23
JTAG_TCK
2
L Enable JTAG_TMS AL24 JTAG_TMS AN20 PS_0
AM24 AUX2P AM20
TEST POINT@ T11 JTAG_TDO JTAG_TDO PS_1
AUX2N
PS_2
AL30 +3VGS PS_3
NC
1
AM30 @ @
NC
1
RV24 RV25 Strap@ 1 PX@ 1 Strap@ 1 Strap@ 1
THERMAL AL29 10K_0402_5% 10K_0402_5% CV26 CV27 CV29 CV28
NC
<33> REMOTE1+ REMOTE1+ AF29 DPLUS AM29 X76@ RV27 PX@RV28
PX@ RV28 PX@RV29
PX@ RV29 PX@RV30
PX@ RV30
NC
0.01U_0402_16V7K
0.68U_0402_10V6K
0.01U_0402_16V7K
0.01U_0402_16V7K
2
REMOTE1- AG29 4.75K_0402_1% 4.75K_0402_1% 4.75K_0402_1% 2K_0402_1%

<33> REMOTE1- DMINUS
2
1DEBUG@ 2 GPIO_28_FDO AN21 2 2 2 2

+3VGS NC
2
4 RV26 10K_0402_5% AM21 VGA_SMB_CK2 1 6 4
1 PX@ 2 AK32 NC EC_SMB_CK2 <33,36>
GPIO_28_FDO
5
RV31 10K_0402_5% AK30 @ QV3A

NC
AL31 AK29 DMN66D0LDW-7 2N_SOT363-6
+1.8VGS +TSVDD TS_A NC
(1.8V@13mA TSVDD) VGA_SMB_DA2 4 3
PX@ LV3
DDCVGACLK
AJ30
EC_SMB_DA2 <33,36> Place CLOSE VGA CHIP
1 2 +TSVDD AJ32 AJ31 @ QV3B
TSVDD DDCVGADATA
BLM15BD121SN1D_0402 AJ33 TSVSS DMN66D0LDW-7 2N_SOT363-6
1U_0402_6.3V6K
10U_0603_6.3V6M
0.1U_0402_16V4Z
CV30
CV31
CV32
1 1 1
1126A Blues Modify
PX@ MARS-XTX M2_FCBGA962
TSVDD MarsCRB Design Security Classification Compal Secret Data Compal Electronics, Inc.
2 2 2
120ohm 1 1 Issued Date 2012/11/13 Deciphered Date 2013/11/12 Title
PX@
PX@
PX@
0.1u 1 1 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ATI_MarsXT_M2_Main_MSIC
1u 1 1 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C 0.1
10u 1 1
VALGD MB L
A B C D E
A B C D E
UV1C
3/1 SIT downsize to 0402, BLM15AX221SN1D (Murata)
PART 9 0F 9
For EMI
GCLK_27MHZ <38>
+1.8VGS +MPV18
LV4 PX@ (MPLL_PVDD:1.8V@130mA ) GCLK@
MPLL_PVDD MarsCRB Design AV33 XTALIN RV40 1 2 0_0402_5% PXNOGCLK@ RV32 1 2 1M_0402_5%
XTALIN
220ohm 1 1 BLM15AX221SN1D 0402
10U_0603_6.3V6M
1U_0402_6.3V6K
CV33
CV34
CV35
0.1U_0402_16V7K
SM01000MK00
0.1u 1 1 1 1 1 YV1
4 3 XTALOUT
1u 1 1 NC OSC
1
10u 1 1 2 2 2
XTALIN 1
OSC NC
2 1
PX@
PX@
PX@
AU34 XTALOUT 2 2
XTALOUT
PXNOGCLK@ 27MHZ 10PF +-20PPM X3G027000DA1H PXNOGCLK@
CV36 PXNOGCLK@ CV37
15P_0402_50V8J 15P_0402_50V8J
+MPV18 H7 1 1
MPLL_PVDD
H8
MPLL_PVDD
+SPV18 AW34
SPLL_PVDD MarsCRB Design +1.8VGS
LV5 PX@
(SPLL_PVDD:1.8V@75mA ) XO_IN
120ohm 1 1 1 2 +SPV18 AM10 SPLL_PVDD
PLLS/XTAL
BLM15BD121SN1D_0402
0.1u 1 1
CV38
CV39
CV40
10U_0603_6.3V6M
1U_0402_6.3V6K
0.1U_0402_16V7K
1u 1 1 1 1 1
+SPLL_VDDC AN9 AW35
SPLL_VDDC XO_IN2
10u 1 1
2 2 2
PX@
PX@
PX@
AN10
SPLL_PVSS
+0.95VGS AK10
SPLL_VDDC MarsCRB Design LV6 PX@
+SPLL_VDDC
(SPLL_VDDC:0.95V@100mA ) AF30 CLKTESTA
AL10
NC_XTAL_PVDD CLKTESTB
120ohm 1 1 1 2 AF31 NC_XTAL_PVSS
1
BLM15BD121SN1D_0402 DEBUG@ DEBUG@
0.1u 1 1
CV43
CV44
CV45
10U_0603_6.3V6M
CV41 CV42
1U_0402_6.3V6K
0.1U_0402_16V7K
0.1U_0402_16V7K 0.1U_0402_16V7K
1u 1 1 1 1 1
2
10u 1 1
1
2 2 2
PX@
PX@
PX@
DEBUG@ DEBUG@
RV33 RV34
51.1_0402_1% 51.1_0402_1%
2
2 2
#9/11 need to confirm w/ Power team
+1.5V to +1.5VGS
+3VS to +3VGS
+1.5V +1.5VGS
+3VS +3VGS
300mil(7.2A) 3 1 10U_0603_6.3V6M 1U_0603_10V6K

PX@ 1
1
CV48 PX@ 1 1
4.7U_0603_6.3V6K QV8 CV46 CV47 @
AO4430: Rdson: 5.5mohm @ VGS=10V LP2301ALT1G_SOT23-3 RV36
2
2 PX@ PX@ 470_0603_5%
UV4 2 2
2
AO4304L_SO8 +5VALW
8 1
300mil(7.2A)
1
7 2 D
6 3 PX@ 2
2
5 1 PX@ 1@ RV37 RV38 G

CV49 CV50 RV39 @ 1 2 1 2 S @
3
SIT: Change to +5VALW for Eur lot 6. 4.7U_0603_6.3V6K 0.1U_0402_16V4Z 470_0603_5% QV7
4
PX@ 100K_0402_5% 0_0402_5% 2N7002K_SOT23-3

2 2 PX@
1
1 PX@
1
D PX@ PXS_PW REN#
+5VALW PXS_PW REN 2 QV6 CV52
PX@ 2N7002K_SOT23-3 0.1U_0402_16V4Z
G
47K_0402_5% 2
S
3
2 1
1
RV41 D
1 @ QV1 2 PXS_PW REN#
2
PX@ PX@ 2N7002_SOT23 G

3 QV2 RV42 @ CV53 S 3
3
2N7002_SOT23 0_0402_5% 0.1U_0402_25V6

1
D 2
PXS_PW REN# 2
1
G
S
3
#9/11 need to confirm w/ Power team
+1.8VS to +1.8VGS
+3VALW
1
PX@
RV35
100K_0402_5%
2
PXS_PW REN#
1
OUT
PX@
QV9
PXS_PW REN 2 DTC124EKAT146_SC59-3
<13,36,45,51,52> PXS_PW REN IN
GND
3
4 4

ATI_MarsXT_M2_BACO POWER
Custom 0.1
VALGD MB L
Date: Tuesday, April 16, 2013 Sheet 18 of 57
A B C D E
A B C D E
UV1G
PART 6 0F 9 UV1F
AB39 A3 PART 8 0F 9
E39 GND GND A37 +0.95VGS
GND GND DP_VDDR DP_VDDC
(DP_VDDC:0.95V@280mA/link )
F34 AA16
F39 GND GND AA18 AP31
G33 GND GND AA2 DP_VDDC AP32
G34 GND GND AA21 DP_VDDC AN33
H31 GND GND AA23 DP_VDDC AP33
H34 GND GND AA26 AN24 DP_VDDC AL33
H39 GND GND AA28 AP24 NC DP_VDDC AM33
J31 GND GND AA6 AP25 NC DP_VDDC AK33
1 J34 GND GND AB12 AP26 NC DP_VDDC AK34 1
K31 GND GND AB15 AU28 NC DP_VDDC AN31
K34 GND GND AB17 AV29 NC DP_VDDC
K39 GND GND AB20 NC
L31 GND GND AB22
L34 GND GND AB24 AP20 AP13
GND GND NC NC
M34 AB27 AP21 AT13
M39 GND GND AC11 AP22 NC NC AP14
N31 GND GND AC13 AP23 NC NC AP15
N34 GND GND AC16 AU18 NC NC
P31 GND GND AC18 AV19 NC
P34 GND GND AC2 +1.8VGS NC DP GND
+DP_VDDR (DP_VDDR:1.8V@237mA/link )
P39 GND GND AC21 AN27
R34 GND GND AC23 1 2 +DP_VDDR AH34 DP_VSSR AP27
T31 GND GND AC26 AJ34 DP_VDDR DP_VSSR AP28
RV43 0_0402_5%
T34 GND GND AC28 AF34 DP_VDDR DP_VSSR AW24
GND GND PX@ DP_VDDR DP_VSSR
T39 AC6 AG34 AW26
U31 GND GND AD15 AM37 DP_VDDR DP_VSSR AN29
U34 GND GND AD17 AL38 DP_VDDR DP_VSSR AP29
V34 GND GND AD20 AM32 DP_VDDR DP_VSSR AP30
V39 GND GND AD22 DP_VDDR DP_VSSR AW30
W31 GND GND AD24 DP_VSSR AW32
W34 GND GND AD27 DP_VSSR AN17
Y34 GND GND AD9 DP_VSSR AP16
Y39 GND GND AE2 DP_VSSR AP17
GND GND AE6 DP_VSSR AW14
GND AF10 DP_VSSR AW16
GND AF16 DP_VSSR AN19
GND AF18 DP_VSSR AP18
GND AF21 DP_VSSR AP19
GND GND DP_VSSR
AG17 AW20
F15 GND AG2 CALIBRATION DP_VSSR AW22
2 F17 GND GND AG20 DP_VSSR AN34 2
F19 GND GND DP_VSSR AP39
F21 GND AG6 AW28 DP_VSSR AR39
F23 GND GND AG9 NC DP_VSSR AU37
F25 GND GND AH21 DP_VSSR AF39
F27 GND GND AJ10 DP_VSSR AH39
F29 GND GND AJ11 AW18 DP_VSSR AK39
F31 GND GND AJ2 NC DP_VSSR AL34
F33 GND GND AJ28 DP_VSSR AV27
F7 GND GND AJ6 DP_VSSR AR28
F9 GND GND AK11 DP_VSSR
RV44 2 PX@ 1 150_0402_1% AM39 AV17
G2 GND GND AK31 DP_CALR DP_VSSR AR18
G6 GND GND AK7 DP_VSSR AN38
H9 GND GND AL11 DP_VSSR AM35
J2 GND GND AL14 DP_VSSR AN32
J27 GND GND AL17 DP_VSSR
J6 GND GND AL2
J8 GND GND AL20
K14 GND GND
K7 GND AL23
L11 GND AL26
L17 GND GND AL32 PX@ MARS-XTX M2_FCBGA962
L2 GND GND AL6
L22 GND GND AL8
L24 GND GND AM11
L6 GND GND AM31
M17 GND GND AM9
M22 GND GND AN11
M24 GND GND AN2
N16 GND GND AN30
N18 GND GND AN6
N2 GND GND AN8
3 N21 GND GND AP11 3
N23 GND GND AP7
N26 GND GND AP9
N6 GND GND AR5
R15 GND GND B11
R17 GND GND B13
R2 GND GND B15
R20 GND GND B17
R22 GND GND B19
R24 GND GND B21
R27 GND GND B23
R6 GND GND B25
T11 GND GND B27
T13 GND GND B29
T16 GND GND B31
T18 GND GND B33
T21 GND GND B7
T23 GND GND B9
T26 GND GND C1
U15 GND GND C39
U17 GND GND E35
U2 GND GND E5
U20 GND GND F11
U22 GND GND F13
U24 GND GND
U27 GND GND
U6 GND
V11 GND AG22
V16 GND NC
V18 GND
V21 GND
V23 GND
4 V26 GND 4
W2 GND
W6 GND
Y15 GND
Y17 GND
Y20 GND
Y22 GND A39 MECH#1 TV12 PAD TEST POINT@
Y24 GND VSS_MECH AW1 MECH#2 TV13 PAD TEST POINT@
Y27 GND
GND
VSS_MECH
VSS_MECH
AW39 MECH#3 TV14 PAD TEST POINT@ Security Classification Compal Secret Data Compal Electronics, Inc.
ATI_MarsXT_M2_PWR_GND
PX@ MARS-XTX M2_FCBGA962 Size Document Number
Rev
Custom 0.1
VALGD MB L
A B C D E
A B C D E
SIT :220U 4V Y D2 ESR15M = SGA00000Y80

(PCIE_VDDR:1.8V@100mA ) +PCIE_VDDR +1.8VGS
+1.5VGS UV1E SHORT PAD@
For GDDR5, MVDDQ = 1.5V PART 5 0F 9 +PCIE_VDDR 1 2
PCIE_VDDR MarsCRB Design
LV7 0_0603_5% 0.1u 0 2
(VDDR1:1.5V@3A,GDDR5:1125MHz )
CV62
CV63
CV64
CV65
MEM I/O
10U_0603_6.3V6M
1U_0402_6.3V6K
0.1U_0402_16V7K
0.01U_0402_25V7K
+1.5VGS AC7
VDDR1 NC
AA31 1 1 1 1 1u 2 3
AD11 AA32
VDDR1 NC 10u 1 1
220U 4V Y D2 ESR15M
AF7 AA33
CV60
CV67
CV68
CV69
CV70
CV71
CV72
CV73
CV74
CV75
CV76
CV61
CV77
CV78
CV79
1 VDDR1
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
NC
PX@
SGA00000Y80 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 AG10 VDDR1 AA34
+ NC 2 2 2 2
PX@
PX@
PX@
AJ7 W30
CV66
VDDR1 NC
AK8 Y31
VDDR1 NC
AL9 VDDR1 V28
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 NC_BIF_VDDC
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
G11 W29
DEBUG@
DEBUG@
DEBUG@
VDDR1 NC_BIF_VDDC +0.95VGS
G14 AB37
1 VDDR1 PCIE_PVDD PCIE_VDDC MarsCRB Design 1
PCIE
G17 (PCIE_VDDC:0.95V@2.5A_GEN2.0 )
VDDR1
G20
G23
VDDR1 PCIE_VDDC
G30
G31
+0.95VGS 1u 7 5
VDDR1 PCIE_VDDC
G26 H29 10u 2 1
CV80
CV81
CV82
CV83
CV84
CV85
VDDR1
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0603_6.3V6M
PCIE_VDDC
G29 VDDR1 H30 1 1 1 1 1 1
PCIE_VDDC
H10 J29
VDDR1 MarsCRB Design J7
VDDR1 PCIE_VDDC J30
VDDR1 PCIE_VDDC
0.01u 5 0 J9 VDDR1 PCIE_VDDC
L28
2 2 2 2 2 2
PX@
PX@
PX@
PX@
PX@
K11 M28
DEBUG@
VDDR1 PCIE_VDDC
0.1u 5 5 K13 VDDR1 PCIE_VDDC
N28
K8 R28
1u 0 5 L12
VDDR1
VDDR1
PCIE_VDDC T28
PCIE_VDDC
2.2u 5 0 L16 VDDR1 U28
L21 PCIE_VDDC +0.95VGS
VDDR1
10u 3 5 L23 VDDR1 (BIF_VDDC:0.95V@1.4A)
L26 N27 +0.95VGS
220u 0 1 VDDR1 BACO BIF_VDDC
L7 T27
VDDR1 BIF_VDDC
10U_0603_6.3V6M
M11
CV86
CV87
CV88
VDDR1
1U_0402_6.3V6K
1U_0402_6.3V6K
N11 1 1 1
VDDR1
P7 VDDR1 AA15
CORE VDDC
R11 AA17
+1.8VGS +VDDC_CT VDDR1 VDDC
PX@
U11 AA20
VDDR1 VDDC 2 2 2
PX@
PX@
LV8 PX@ (VDD_CT:1.8V@13mA ) U7 AA22
VDD_CT MarsCRB Design 1 2 Y11
VDDR1 VDDC AA24
VDDR1 VDDC
120ohm 1 1 BLM15BD121SN1D_0402 Y7 VDDR1 VDDC
AA27
AB16
CV89
CV90
CV91
10U_0603_6.3V6M
1U_0402_6.3V6K
0.1U_0402_16V7K
0.1u 1 1 VDDC AB18
1 1 1 VDDC
AB21
1u 1 3 VDDC AB23 +VGA_CORE
VDDC
10u 1 1 LEVEL AB26
2 2 2 VDDC
PX@
PX@
AB28
DEBUG@
TRANSLATION VDDC
+VDDC_CT AF26 AC17
VDD_CT VDDC
AF27 VDD_CT AC20
AG26 VDDC AC22
VDD_CT VDDC
AG27 AC24
VDDR3 MarsCRB Design VDD_CT VDDC
AC27
VDDC
120ohm 1 0 +3VGS +VDDR3
VDDC
AD18
AD21
2 LV9 PX@ (VDDR3:3.3V@25mA) I/O 2
0.1u 1 0 1 2 AF23 VDDC AD23
+VDDR3 VDDR3 VDDC
BLM15BD121SN1D_0402 AF24 VDDR3 AD26
1u 2 3 AG23
VDDC
AF17
CV92
CV93
CV94
CV95
10U_0603_6.3V6M
VDDR3
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
AG24 VDDC AF20
10u 0 1 1 1 1 1 VDDR3 VDDC
AF22
VDDC AG16
DVP VDDC
AD12 VDDR4 AG18
2 2 2 2 VDDC
PX@
PX@
PX@
AF11
VGA_CORE Cap in power side sheet
DEBUG@
VDDR4
AF12 AH22
VDDR4 VDDC
AF13 VDDR4 AH27
VDDC AH28
VDDC
M26
VDDC
AF15 N24
+1.8VGS +VDDR4 VDDR4 VDDC
AG11 R18
VDDR4 VDDC
LV10 PX@ ( VDDR4:1.8V@300mA) AG13 VDDR4 R21
VDDR4 MarsCRB Design +VDDR4 AG15 VDDC R23
VDDR4 VDDC
220ohm 1 1 BLM15AX221SN1D 0402
VDDC
R26
T17
SM01000MK00
0.1u 1 1 VDDC T20
VDDC
T22
1u 1 1 VDDC T24
VDDC
10u 1 0 U16
VDDC
U18
3/1 SIT downsize to 0402, BLM15AX221SN1D (Murata) VDDC U21
VDDC
U23
VDDC U26
VDDC
V17
VDDC
V20
VDDC V22
VDDC
V24
VDDC V27
VDDC
Y16
VDDC
Y18
VDDC Y21
VDDC
Y23
VDDC Y26
VDDC +VGA_CORE
Y28
3 VDDC 3
(VDDCI:0.9~1.15V@8.8A)
AA13
VDDCI
AB13
VDDCI AC12
VDDCI
AC15
VDDCI
AD13
VDDCI AD16
VDDCI
M15
VDDCI M16
VDDCI
M18
Route as differential pair VOLTAGE VDDCI
M23
CORE I/O
SENESE VDDCI
ISOLATED
N13
VDDCI
AF28 FB_VDDC N15
<50> VGA_CORE_SEN VDDCI N17
VDDCI
N20
VDDCI
AG28 N22
FB_VDDCI VDDCI
TEST POINT@ TV15 R12
VDDCI
R13
AH29 VDDCI R16
<50> VGA_VSS_SEN FB_GND VDDCI
T12
VDDCI
T15
VDDCI V15
VDDCI
Y13
VDDCI
4 4

ATI_MarsXT_M2_Power
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.1
VALGD MB L
A B C D E
A B C D E
UV1H
UV1I
PART 3 0F 9
MDB[0..63] PART 4 0F 9
GDDR5/DDR3 <24,25> MDB[0..63]
MDA0 C37 G24 MAA0 MDA[0..63]
DQA0_0 MAA0_0/MAA_0 <22,23> MDA[0..63] GDDR5/DDR3
MDA1 C35 DQA0_1 MAA0_1/MAA_1 J23 MAA1 MDB0 C5 MAB0_0/MAB_0 P8 MAB0
A35 H24 MAB[15..0] C3 DQB0_0 T9
MDA2 DQA0_2 MAA0_2/MAA_2 MAA2 MDB1 MAB0_1/MAB_1 MAB1
MAA[15..0] MAB[15..0] <24,25> DQB0_1
MDA3 E34 DQA0_3 MAA0_3/MAA_3 J24 MAA3 MDB2 E3 MAB0_2/MAB_2 P9 MAB2
MAA[15..0] <22,23> B_BA[2..0] DQB0_2
MDA4 G32 H26 MAA4 MDB3 E1 N7 MAB3
DQA0_4 MAA0_4/MAA_4 A_BA[2..0] B_BA[2..0] <24,25> DQB0_3 MAB0_3/MAB_3
MDA5 D33 J26 MAA5 MDB4 F1 N8 MAB4
DQA0_5 MAA0_5/MAA_5 A_BA[2..0] <22,23> DQB0_4 MAB0_4/MAB_4
MDA6 F32 DQA0_6 MAA0_6/MAA_6 H21 MAA6 MDB5 F3 MAB0_5/MAB_5 N9 MAB5
E32 G21 F5 DQB0_5 U9
MDA7 MAA7 MDB6 MAB6
MEMORY INTERFACE A
DQA0_7 MAA0_7/MAA_7 DQB0_6 MAB0_6/MAB_6
MDA8 D31 DQA0_8 MAA1_0/MAA_8 H19 MAA8 MDB7 G4 MAB0_7/MAB_7 U8 MAB7
DQB0_7
MDA9 F30 H20 MAA9 MDB8 H5 Y9 MAB8
MDA10 C30 L13 MAA10 MDB9 H6 W9 MAB9
MDA11 A30 DQA0_11 MAA1_3/MAA_11 G16 MAA11 MDB10 J4 MAB1_2/MAB_10 AC8 MAB10
F28 J16 K6 DQB0_10 AC9
MDA12 DQA0_12 MAA1_4/MAA_12 MAA12 MDB11 MAB1_3/MAB_11 MAB11
DQB0_11
MDA13 C28 DQA0_13 MAA1_5/MAA_BA2 H16 A_BA2 MDB12 K5 MAB1_4/MAB_12 AA7 MAB12
1 DQB0_12 1
MDA14 A28 J17 A_BA0 MDB13 L4 AA8 B_BA2
DQA0_14 MAA1_6/MAA_BA0 DQB0_13 MAB1_5/BA2
MDA15 E28 H17 A_BA1 MDB14 M6 Y8 B_BA0
DQA0_15 MAA1_7/MAA_BA1 DQB0_14 MAB1_6/BA0
MDA16 D27 DQA0_16 MDB15 M1 MAB1_7/BA1 AA9 B_BA1
DQB0_15
MEMORY INTERFACE B
MDA17 F26 A32 DQMA0 MDB16 M3
DQA0_17 WCKA0_0/DQMA_0 DQMA0 <22> DQB0_16
MDA18 C26 DQA0_18 WCKA0B_0/DQMA_1 C32 DQMA1 MDB17 M5 H3 DQMB0
DQMA1 <22> DQB0_17 WCKB0_0/DQMB_0 DQMB0 <24>
MDA19 A26 D23 DQMA2 MDB18 N4 H1 DQMB1
DQA0_19 WCKA0_1/DQMA_2 DQMA2 <22> DQB0_18 WCKB0B_0/DQMB_1 DQMB1 <24>
MDA20 F24 E22 DQMA3 MDB19 P6 T3 DQMB2
DQA0_20 WCKA0B_1/DQMA_3 DQMA3 <22> DQB0_19 WCKB0_1/DQMB_2 DQMB2 <24>
MDA21 C24 DQA0_21 WCKA1_0/DQMA_4 C14 DQMA4 MDB20 P5 T5 DQMB3
A24 A14 DQMA4 <23> R4 DQB0_20 WCKB0B_1/DQMB_3 AE4 DQMB3 <24>
MDA22 DQA0_22 WCKA1B_0/DQMA_5 DQMA5 MDB21 DQMB4
DQMA5 <23> DQB0_21 WCKB1_0/DQMB_4 DQMB4 <25>
MDA23 E24 DQA0_23 WCKA1_1/DQMA_6 E10 DQMA6 MDB22 T6 AF5 DQMB5
DQMA6 <23> DQB0_22 WCKB1B_0/DQMB_5 DQMB5 <25>
MDA24 C22 D9 DQMA7 MDB23 T1 AK6 DQMB6
DQA0_24 WCKA1B_1/DQMA_7 DQMA7 <23> DQB0_23 WCKB1_1/DQMB_6 DQMB6 <25>
MDA25 A22 MDB24 U4 AK5 DQMB7
DQA0_25 DQB0_24 WCKB1B_1/DQMB_7 DQMB7 <25>
MDA26 F22 DQA0_26 C34 QSA0 MDB25 V6
D21 EDCA0_0/QSA_0 D29 QSA0 <22> V1 DQB0_25 F6
MDA27 DQA0_27 QSA1 MDB26 QSB0
EDCA0_1/QSA_1 QSA1 <22> DQB0_26 EDCB0_0/QSB_0 QSB0 <24>
MDA28 A20 DQA0_28 D25 QSA2 MDB27 V3 K3 QSB1
MDA29 F20 E20 QSA3 MDB28 Y6 P3 QSB2
DQA0_29 EDCA0_3/QSA_3 QSA3 <22> DQB0_28 EDCB0_2/QSB_2 QSB2 <24>
MDA30 D19 E16 QSA4 MDB29 Y1 V5 QSB3
DQA0_30 EDCA1_0/QSA_4 QSA4 <23> DQB0_29 EDCB0_3/QSB_3 QSB3 <24>
MDA31 E18 DQA0_31 E12 QSA5 MDB30 Y3 AB5 QSB4
C18 EDCA1_1/QSA_5 J10 QSA5 <23> Y5 DQB0_30 EDCB1_0/QSB_4 AH1 QSB4 <25>
MDA32 DQA1_0 QSA6 MDB31 QSB5
MDA33 A18 DQA1_1 D7 QSA7 MDB32 AA4 AJ9 QSB6
MDA34 F18 MDB33 AB6 AM5 QSB7
DQA1_2 DQB1_1 EDCB1_3/QSB_7 QSB7 <25>
MDA35 D17 A34 QSA#0 MDB34 AB1
DQA1_3 DDBIA0_0/QSA_0B QSA#0 <22> DQB1_2
MDA36 A16 DQA1_4 E30 QSA#1 MDB35 AB3 G7 QSB#0
F16 DDBIA0_1/QSA_1B E26 QSA#1 <22> AD6 DQB1_3 DDBIB0_0/QSB_0B K1 QSB#0 <24>
MDA37 DQA1_5 QSA#2 MDB36 QSB#1
DDBIA0_2/QSA_2B QSA#2 <22> DQB1_4 DDBIB0_1/QSB_1B QSB#1 <24>
MDA38 D15 DQA1_6 C20 QSA#3 MDB37 AD1 P1 QSB#2
MDA39 E14 C16 QSA#4 MDB38 AD3 W4 QSB#3
DQA1_7 DDBIA1_0/QSA_4B QSA#4 <23> DQB1_6 DDBIB0_3/QSB_3B QSB#3 <24>
MDA40 F14 C12 QSA#5 MDB39 AD5 AC4 QSB#4
DQA1_8 DDBIA1_1/QSA_5B QSA#5 <23> DQB1_7 DDBIB1_0/QSB_4B QSB#4 <25>
MDA41 D13 DQA1_9 J11 QSA#6 MDB40 AF1 AH3 QSB#5
F12 DDBIA1_2/QSA_6B F8 QSA#6 <23> AF3 DQB1_8 DDBIB1_1/QSB_5B AJ8 QSB#5 <25>
MDA42 DQA1_10 QSA#7 MDB41 QSB#6
MDA43 A12 DQA1_11 MDB42 AF6 AM3 QSB#7
DQB1_10 DDBIB1_3/QSB_7B QSB#7 <25>
MDA44 D11 J21 ODTA0 MDB43 AG4
DQA1_12 ADBIA0/ODTA0 ODTA0 <22> DQB1_11
MDA45 F10 G19 ODTA1 MDB44 AH5 T7 ODTB0
DQA1_13 ADBIA1/ODTA1 ODTA1 <23> DQB1_12 ADBIB0/ODTB0 ODTB0 <24>
MDA46 A10 DQA1_14 MDB45 AH6 W7 ODTB1
C10 H27 CLKA0 AJ4 DQB1_13 ADBIB1/ODTB1 ODTB1 <25>
MDA47 DQA1_15 CLKA0 MDB46
CLKA0 <22> DQB1_14
MDA48 G13 DQA1_16 CLKA0B G27 CLKA0# MDB47 AK3 L9 CLKB0
CLKA0# <22> DQB1_15 CLKB0 CLKB0 <24>
MDA49 H13 MDB48 AF8 L8 CLKB0#
DQA1_17 DQB1_16 CLKB0B CLKB0# <24>
MDA50 J13 J14 CLKA1 MDB49 AF9
DQA1_18 CLKA1 CLKA1 <23> DQB1_17
2 MDA51 H11 DQA1_19 CLKA1B H14 CLKA1# MDB50 AG8 AD8 CLKB1 2
G10 CLKA1# <23> AG7 DQB1_18 CLKB1 AD7 CLKB1# CLKB1 <25>
MDA52 DQA1_20 MDB51
DQB1_19 CLKB1B CLKB1# <25>
MDA53 G8 DQA1_21 K23 RASA0# MDB52 AK9
RASA0B RASA0# <22> DQB1_20
MDA54 K9 K19 RASA1# MDB53 AL7 T10 RASB0#
DQA1_22 RASA1B RASA1# <23> DQB1_21 RASB0B RASB0# <24>
MDA55 K10 MDB54 AM8 Y10 RASB1#
DQA1_23 DQB1_22 RASB1B RASB1# <25>
MDA56 G9 DQA1_24 K20 CASA0# MDB55 AM7
A8 CASA0B K17 CASA1# CASA0# <22> AK1 DQB1_23 W10 CASB0#
MDA57 DQA1_25 MDB56
CASA1B CASA1# <23> DQB1_24 CASB0B CASB0# <24>
MDA58 C8 DQA1_26 MDB57 AL4 AA10 CASB1#
DQB1_25 CASB1B CASB1# <25>
MDA59 E8 CSA0B_0 K24 CSA0#_0 MDB58 AM6
DQA1_27 CSA0#_0 <22> DQB1_26
MDA60 A6 CSA0B_1 K27 MDB59 AM1 P10 CSB0#_0
DQA1_28 DQB1_27 CSB0B_0 CSB0#_0 <24>
MDA61 C6 DQA1_29 MDB60 AN4 L10
E6 M13 CSA1#_0 AP3 DQB1_28 CSB0B_1
MDA62 DQA1_30 CSA1B_0 MDB61
CSA1#_0 <23> DQB1_29
MDA63 A5 DQA1_31 CSA1B_1 K16 MDB62 AP1 AD10 CSB1#_0
DQB1_30 CSB1B_0 CSB1#_0 <25>
MDB63 AP5 AC10
L18 K21 CKEA0 DQB1_31 CSB1B_1
+VDD_MEM15_REFDA MVREFDA CKEA0 CKEA0 <22>
+VDD_MEM15_REFSA L20 MVREFSA CKEA1 J20 CKEA1 U10 CKEB0
CKEA1 <23> CKEB0 CKEB0 <24>
+VDD_MEM15_REFDB Y12 AA11 CKEB1
MVREFDB CKEB1 CKEB1 <25>
L27 NC WEA0B K26 WEA0# +VDD_MEM15_REFSB AA12
WEA0# <22> MVREFSB
N12 WEA1B L15 WEA1# N10 WEB0#
NC WEA1# <23> WEB0B WEB0# <24>
AG12 AB11 WEB1#
NC WEB1B WEB1# <25>
H23 MAA13
MAA0_8/MAA_13
1 PX@ 2 M27 MEM_CALRP0 MAA1_8/MAA_14 J19 MAA14 MAB0_8/MAB_13 T8 MAB13
RV47 120_0402_1% M21 MAA15 W8 MAB14
MAA0_9/MAA_15 MAB1_8/MAB_14
M12 M20 U12 MAB15
NC MAA1_9/RSVD MAB0_9/MAB_15
AH12 NC MAB1_9/RSVD V12
DRAM_RST AH11 DRAM_RST#_R
PX@ MARS-XTX M2_FCBGA962 PX@ MARS-XTX M2_FCBGA962
3 3
Ball to RV57 < 1"

CV100 to RV57 < 200 mil +1.5VGS
+1.5VGS +1.5VGS CV100 to RV53 < 1" +1.5VGS +1.5VGS
1
RV48
1
1
4.7K_0402_5%
RV49 RV50 @
40.2_0402_1% 40.2_0402_1% RV51 RV52
2
PX@ PX@ 40.2_0402_1% 40.2_0402_1%

PX@ PX@
2
2
+VDD_MEM15_REFDA +VDD_MEM15_REFSA 1 PX@ 2 1 PX@ 2 DRAM_RST#_R +VDD_MEM15_REFDB +VDD_MEM15_REFSB
<22,23,24,25> DRAM_RST# RV53 51.1_0402_1% RV54 10_0402_5%
1
1
1 1 1 1
1
2
RV56
RV55 CV98 100_0402_1% CV99 CV100 RV58 CV101 RV59 CV102
100_0402_1% 1U_0402_6.3V6K PX@ 1U_0402_6.3V6K 120P_0402_50V9 RV57 100_0402_1% 1U_0402_6.3V6K 100_0402_1% 1U_0402_6.3V6K
2
PX@ 2 PX@ 2 PX@ PX@ 4.99K_0402_1% PX@ 2 PX@ PX@ 2 PX@

2
2
PX@
1
DRAM_RST# is a daisy-chain net that connects to all VRAM

This basic topology should be used for DRAM_RST for DDR3/GDDR5.These
Capacitors and Resistor values are an example only. The Series R and
|| Cap values will depend on the DRAM load and will have to be
4 4
calculated for different Memory ,DRAM Load and board to pass Reset
Signal Spec.
Place all these components very close to GPU (Within
25mm) and keep all component close to each Other (within
5mm) except Rser2

ATI_MarsXT_M2_MEM IF
C 0.1
VALGD MB L
A B C D E
5 4 3 2 1
UV6
UV5 +VREFC_A1 M8 E3 MDA24

H1 VREFCA DQL0 F7 MDA30
+VREFC_A0 M8 E3 MDA23 VREFDQ DQL1 F2 MDA27
H1 VREFCA DQL0 F7 MDA19 MAA0 N3 DQL2 F8 MDA29
VREFDQ DQL1 F2 MDA22 MAA1 P7 A0 DQL3 H3 MDA25
MAA0 N3 DQL2 F8 MDA18 MAA2 P3 A1 DQL4 H8 MDA28
MAA1 P7 A0 DQL3 H3 MDA21 MAA3 N2 A2 DQL5 G2 MDA26
MAA2 P3 A1 DQL4 H8 MDA17 MAA4 P8 A3 DQL6 H7 MDA31
MAA3 N2 A2 DQL5 G2 MDA20 MAA5 P2 A4 DQL7
MAA4 P8 A3 DQL6 H7 MDA16 MAA6 R8 A5
MAA5 P2 A4 DQL7 MAA7 R2 A6 D7 MDA12
D
MAA6 R8 A5 MAA8 T8 A7 DQU0 C3 MDA10 D
MDA[0..31] MAA7 R2 A6 D7 MDA0 MAA9 R3 A8 DQU1 C8 MDA14
<21> MDA[0..31] MAA8 T8 A7 DQU0 C3 MDA5 MAA10 L7 A9 DQU2 C2 MDA11
MAA9 R3 A8 DQU1 C8 MDA1 MAA11 R7 A10/AP DQU3 A7 MDA13
MAA10 L7 A9 DQU2 C2 MDA6 MAA12 N7 A11 DQU4 A2 MDA9
MAA11 R7 A10/AP DQU3 A7 MDA3 MAA13 T3 A12 DQU5 B8 MDA15
MAA12 N7 A11 DQU4 A2 MDA4 MAA14 T7 A13 DQU6 A3 MDA8
MAA[15..0] MAA13 T3 A12 DQU5 B8 MDA2 MAA15 M7 A14 DQU7
<21,23> MAA[15..0] T7 A13 DQU6 A3 A15/BA3 +1.5VGS
MAA14 MDA7
MAA15 M7 A14 DQU7
A15/BA3 +1.5VGS A_BA0 M2 B2
A_BA1 N8 BA0 VDD D9
M2 B2 A_BA2 M3 BA1 VDD G7
<21,23> A_BA0 N8 BA0 VDD D9 BA2 VDD K2
<21,23> A_BA1 BA1 VDD VDD
M3 G7 K8
<21,23> A_BA2 BA2 VDD VDD
K2 N1
VDD K8 CLKA0 J7 VDD N9
VDD N1 CLKA0# K7 CK VDD R1
J7 VDD N9 CKEA0 K9 CK VDD R9
<21> CLKA0 CK VDD CKE/CKE0 VDD +1.5VGS
K7 R1
<21> CLKA0# CK VDD
K9 R9
<21> CKEA0 CKE/CKE0 VDD +1.5VGS K1 A1
ODTA0
CSA0#_0 L2 ODT/ODT0 VDDQ A8
K1 A1 RASA0# J3 CS/CS0 VDDQ C1
<21> ODTA0 ODT/ODT0 VDDQ RAS VDDQ
L2 A8 CASA0# K3 C9
<21> CSA0#_0 CS/CS0 VDDQ CAS VDDQ
J3 C1 WEA0# L3 D2
<21> RASA0# K3 RAS VDDQ C9 WE VDDQ E9
<21> CASA0# CAS VDDQ VDDQ
L3 D2 F1
<21> WEA0# WE VDDQ E9 F3 VDDQ H2
QSA3
VDDQ <21> QSA3 DQSL VDDQ
F1 QSA1 C7 H9
VDDQ <21> QSA1 DQSU VDDQ
QSA2 F3 H2
<21> QSA2 C7 DQSL VDDQ H9
QSA0
<21> QSA0 DQSU VDDQ DQMA3 E7 A9
<21> DQMA3 D3 DML VSS B3
DQMA1
<21> DQMA1 DMU VSS
DQMA2 E7 A9 E1
<21> DQMA2 DML VSS VSS
DQMA0 D3 B3 G8
<21> DQMA0 DMU VSS E1 G3 VSS J2
QSA#3
VSS <21> QSA#3 DQSL VSS
C G8 QSA#1 B7 J8 C
G3 VSS J2 <21> QSA#1 DQSU VSS M1
QSA#2
<21> QSA#2 DQSL VSS VSS
QSA#0 B7 J8 M9
<21> QSA#0 DQSU VSS VSS
M1 P1
VSS M9 DRAM_RST# T2 VSS P9
VSS P1 RESET VSS T1
T2 VSS P9 L8 VSS T9
<21,23,24,25> DRAM_RST# RESET VSS ZQ/ZQ0 VSS
T1
L8 VSS T9
ZQ/ZQ0 VSS
1
J1 B1
RV85 L1 NC/ODT1 VSSQ B9
NC/CS1 VSSQ
1
J1 B1 240_0402_1% J9 D1
RV84 L1 NC/ODT1 VSSQ B9 MARS@ L9 NC/CE1 VSSQ D8
J9 NC/CS1 VSSQ D1 NCZQ1 VSSQ E2
240_0402_1%
2
L9 NC/CE1 VSSQ D8 VSSQ E8
MARS@ NCZQ1 VSSQ E2 VSSQ F9
2
VSSQ E8 VSSQ G1
VSSQ F9 VSSQ G9
VSSQ G1 VSSQ
VSSQ G9 96-BALL
VSSQ SDRAM DDR3
96-BALL K4W1G1646E-HC12_FBGA96
SDRAM DDR3 X76@
K4W1G1646E-HC12_FBGA96
CLKA0 1 2
MARS@ X76@
RV60 40.2_0402_1%
CLKA0# 1 2
MARS@
RV61 40.2_0402_1%
1
CV195 +1.5VGS
0.01U_0402_16V7K +1.5VGS
MARS@
2
1
MARS@
1
MARS@ RV63
RV62 4.99K_0402_1%
4.99K_0402_1%
B B
15mil
2
15mil
2
+VREFC_A1
+VREFC_A0
0.1U_0402_16V7K
CV104
MARS@
1
1
0.1U_0402_16V7K
CV103
MARS@ RV65
1
RV64 4.99K_0402_1%
4.99K_0402_1% MARS@
2
MARS@
2
2
2
+1.5VGS
+1.5VGS +1.5VGS
10U_0603_6.3V6M
CV105
1U_0402_6.3V6K
CV106
1U_0402_6.3V6K
CV107
1U_0402_6.3V6K
CV108
1U_0402_6.3V6K
CV109
1U_0402_6.3V6K
CV110
0.1U_0402_16V7K
CV111
0.1U_0402_16V7K
CV112
0.1U_0402_16V7K
CV113
0.1U_0402_16V7K
CV114
10U_0603_6.3V6M
CV115
10U_0603_6.3V6M
CV116
1U_0402_6.3V6K
CV117
1U_0402_6.3V6K
CV118
1U_0402_6.3V6K
CV119
1U_0402_6.3V6K
CV120
1U_0402_6.3V6K
CV121
0.1U_0402_16V7K
CV122
0.1U_0402_16V7K
CV123
0.1U_0402_16V7K
CV124
0.1U_0402_16V7K
CV125
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
MARS@
MARS@
MARS@
MARS@
MARS@
MARS@
MARS@
MARS@
MARS@
MARS@
MARS@
MARS@
@
A
SIT: Placed close to the UV5 SIT: Placed close to the UV6 A

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ATI_Whistler_M2_VRAM_B0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C VALGD MB L 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5 4 3 2 1
5 4 3 2 1
UV7
UV8
+VREFC_A2 M8 E3 MDA38
H1 VREFCA DQL0 F7 MDA36 +VREFC_A3 M8 E3 MDA49
VREFDQ DQL1 F2 MDA39 H1 VREFCA DQL0 F7 MDA51
MAA0 N3 DQL2 F8 MDA34 VREFDQ DQL1 F2 MDA48
MAA1 P7 A0 DQL3 H3 MDA35 MAA0 N3 DQL2 F8 MDA52
D
MAA2 P3 A1 DQL4 H8 MDA33 MAA1 P7 A0 DQL3 H3 MDA50 D
MAA3 N2 A2 DQL5 G2 MDA37 MAA2 P3 A1 DQL4 H8 MDA53
MAA4 P8 A3 DQL6 H7 MDA32 MAA3 N2 A2 DQL5 G2 MDA55
MAA5 P2 A4 DQL7 MAA4 P8 A3 DQL6 H7 MDA54
MAA6 R8 A5 MAA5 P2 A4 DQL7
MAA7 R2 A6 D7 MDA42 MAA6 R8 A5
MAA8 T8 A7 DQU0 C3 MDA44 MAA7 R2 A6 D7 MDA60
MAA9 R3 A8 DQU1 C8 MDA40 MAA8 T8 A7 DQU0 C3 MDA57
MDA[32..63] MAA10 L7 A9 DQU2 C2 MDA46 MAA9 R3 A8 DQU1 C8 MDA63
<21> MDA[32..63] MAA11 R7 A10/AP DQU3 A7 MDA43 MAA10 L7 A9 DQU2 C2 MDA56
MAA12 N7 A11 DQU4 A2 MDA45 MAA11 R7 A10/AP DQU3 A7 MDA61
MAA13 T3 A12 DQU5 B8 MDA41 MAA12 N7 A11 DQU4 A2 MDA59
MAA14 T7 A13 DQU6 A3 MDA47 MAA13 T3 A12 DQU5 B8 MDA62
MAA15 M7 A14 DQU7 MAA14 T7 A13 DQU6 A3 MDA58
MAA[15..0] A15/BA3 +1.5VGS MAA15 M7 A14 DQU7
<21,22> MAA[15..0] A15/BA3 +1.5VGS
A_BA0 M2 B2
<21,22> A_BA0 BA0 VDD
A_BA1 N8 D9 A_BA0 M2 B2
<21,22> A_BA1 M3 BA1 VDD G7 N8 BA0 VDD D9
A_BA2 A_BA1
<21,22> A_BA2 BA2 VDD BA1 VDD
K2 A_BA2 M3 G7
VDD K8 BA2 VDD K2
VDD N1 VDD K8
J7 VDD N9 VDD N1
<21> CLKA1 K7 CK VDD R1 J7 VDD N9
CLKA1
<21> CLKA1# CK VDD CK VDD
K9 R9 CLKA1# K7 R1
<21> CKEA1 CKE/CKE0 VDD +1.5VGS CK VDD
CKEA1 K9 R9
CKE/CKE0 VDD +1.5VGS
K1 A1
<21> ODTA1 L2 ODT/ODT0 VDDQ A8 K1 A1
ODTA1
<21> CSA1#_0 CS/CS0 VDDQ ODT/ODT0 VDDQ
J3 C1 CSA1#_0 L2 A8
<21> RASA1# RAS VDDQ CS/CS0 VDDQ
K3 C9 RASA1# J3 C1
<21> CASA1# L3 CAS VDDQ D2 K3 RAS VDDQ C9
CASA1#
<21> WEA1# WE VDDQ CAS VDDQ
E9 WEA1# L3 D2
VDDQ F1 WE VDDQ E9
QSA4 F3 VDDQ H2 VDDQ F1
<21> QSA4 DQSL VDDQ VDDQ
QSA5 C7 H9 QSA6 F3 H2
<21> QSA5 DQSU VDDQ <21> QSA6 C7 DQSL VDDQ H9
QSA7
<21> QSA7 DQSU VDDQ
C C
DQMA4 E7 A9
<21> DQMA4 DML VSS
DQMA5 D3 B3 DQMA6 E7 A9
<21> DQMA5 DMU VSS <21> DQMA6 DML VSS
E1 DQMA7 D3 B3
VSS G8 <21> DQMA7 DMU VSS E1
QSA#4 G3 VSS J2 VSS G8
<21> QSA#4 B7 DQSL VSS J8 G3 VSS J2
QSA#5 QSA#6
<21> QSA#5 DQSU VSS <21> QSA#6 DQSL VSS
M1 QSA#7 B7 J8
VSS <21> QSA#7 DQSU VSS
M9 M1
VSS P1 VSS M9
DRAM_RST# T2 VSS P9 VSS P1
<21,22,24,25> DRAM_RST# RESET VSS T1 VSS
DRAM_RST# T2 P9
L8 VSS T9 RESET VSS T1
ZQ/ZQ0 VSS L8 VSS T9
ZQ/ZQ0 VSS
1
J1 B1
NC/ODT1 VSSQ
1
RV86 L1 B9 J1 B1
J9 NC/CS1 VSSQ D1 RV87 L1 NC/ODT1 VSSQ B9
240_0402_1% NC/CE1 VSSQ NC/CS1 VSSQ
L9 D8 240_0402_1% J9 D1
MARS@ NCZQ1 VSSQ E2 MARS@ L9 NC/CE1 VSSQ D8
2
VSSQ E8 NCZQ1 VSSQ E2
2
VSSQ F9 VSSQ E8
VSSQ G1 VSSQ F9
VSSQ G9 VSSQ G1
VSSQ VSSQ G9
96-BALL VSSQ
SDRAM DDR3 96-BALL
K4W1G1646E-HC12_FBGA96 SDRAM DDR3
X76@ K4W1G1646E-HC12_FBGA96
X76@
+1.5VGS
B B
+1.5VGS
1
MARS@
CLKA1 1 2
MARS@ RV67
1
RV66 40.2_0402_1% MARS@ 4.99K_0402_1%

RV68
4.99K_0402_1%
15mil
2
CLKA1# 1 2
MARS@
RV69 40.2_0402_1% +VREFC_A3
15mil
2
1
CV196
0.1U_0402_16V7K
CV126
0.01U_0402_16V7K +VREFC_A2 MARS@
1
MARS@ RV70
2
0.1U_0402_16V7K
CV127
MARS@ 4.99K_0402_1%
1
RV71 MARS@
2
4.99K_0402_1%
2
MARS@
2
2
+1.5VGS
+1.5VGS +1.5VGS
10U_0603_6.3V6M
CV128
1U_0402_6.3V6K
CV129
1U_0402_6.3V6K
CV130
1U_0402_6.3V6K
CV131
1U_0402_6.3V6K
CV132
1U_0402_6.3V6K
CV133
0.1U_0402_16V7K
CV134
0.1U_0402_16V7K
CV135
0.1U_0402_16V7K
CV136
0.1U_0402_16V7K
CV137
10U_0603_6.3V6M
CV138
10U_0603_6.3V6M
CV139
1U_0402_6.3V6K
CV140
1U_0402_6.3V6K
CV141
1U_0402_6.3V6K
CV142
1U_0402_6.3V6K
CV143
1U_0402_6.3V6K
CV144
0.1U_0402_16V7K
CV145
0.1U_0402_16V7K
CV146
0.1U_0402_16V7K
CV147
0.1U_0402_16V7K
CV148
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
MARS@
MARS@
MARS@
MARS@
MARS@
MARS@
MARS@
MARS@
MARS@
MARS@
MARS@
MARS@
@
A A
SIT: Placed close to the UV8


ATI_Whistler_M2_VRAM_B1
5 4 3 2 1
5 4 3 2 1
UV9 UV10
+VREFC_B0 M8 E3 MDB19 +VREFC_B1 M8 E3 MDB26

H1 VREFCA DQL0 F7 MDB20 H1 VREFCA DQL0 F7 MDB30
VREFDQ DQL1 F2 MDB22 VREFDQ DQL1 F2 MDB24
MAB0 N3 DQL2 F8 MDB16 MAB0 N3 DQL2 F8 MDB29
MAB1 P7 A0 DQL3 H3 MDB23 MAB1 P7 A0 DQL3 H3 MDB27
MAB3 N2 A2 DQL5 G2 MDB21 MAB3 N2 A2 DQL5 G2 MDB25
MAB5 P2 A4 DQL7 MAB5 P2 A4 DQL7
D
MAB6 R8 A5 MAB6 R8 A5 D
MAB7 R2 A6 D7 MDB0 MAB7 R2 A6 D7 MDB15
MDB[0..31] MAB8 T8 A7 DQU0 C3 MDB4 MAB8 T8 A7 DQU0 C3 MDB10
<21> MDB[0..31] MAB9 R3 A8 DQU1 C8 MDB1 MAB9 R3 A8 DQU1 C8 MDB14
MAB10 L7 A9 DQU2 C2 MDB6 MAB10 L7 A9 DQU2 C2 MDB11
MAB11 R7 A10/AP DQU3 A7 MDB3 MAB11 R7 A10/AP DQU3 A7 MDB12
MAB12 N7 A11 DQU4 A2 MDB7 MAB12 N7 A11 DQU4 A2 MDB9
MAB13 T3 A12 DQU5 B8 MDB2 MAB13 T3 A12 DQU5 B8 MDB13
MAB[15..0] MAB14 T7 A13 DQU6 A3 MDB5 MAB14 T7 A13 DQU6 A3 MDB8
<21,25> MAB[15..0] A14 DQU7 A14 DQU7
MAB15 M7 MAB15 M7
A15/BA3 +1.5VGS A15/BA3 +1.5VGS
M2 B2 B_BA0 M2 B2
<21,25> B_BA0 N8 BA0 VDD D9 N8 BA0 VDD D9
B_BA1
<21,25> B_BA1 BA1 VDD BA1 VDD
M3 G7 B_BA2 M3 G7
K2 K2
VDD K8 VDD K8
VDD N1 VDD N1
J7 VDD N9 CLKB0 J7 VDD N9
<21> CLKB0 CK VDD CK VDD
K7 R1 CLKB0# K7 R1
<21> CLKB0# CK VDD CK VDD
K9 R9 CKEB0 K9 R9
<21> CKEB0 CKE/CKE0 VDD +1.5VGS CKE/CKE0 VDD +1.5VGS
K1 A1 ODTB0 K1 A1
<21> ODTB0 ODT/ODT0 VDDQ ODT/ODT0 VDDQ
L2 A8 CSB0#_0 L2 A8
<21> CSB0#_0 CS/CS0 VDDQ CS/CS0 VDDQ
J3 C1 RASB0# J3 C1
<21> RASB0# K3 RAS VDDQ C9 K3 RAS VDDQ C9
CASB0#
<21> CASB0# CAS VDDQ CAS VDDQ
L3 D2 WEB0# L3 D2
<21> WEB0# WE VDDQ E9 WE VDDQ E9
VDDQ F1 VDDQ F1
QSB2 F3 VDDQ H2 QSB3 F3 VDDQ H2
<21> QSB2 C7 DQSL VDDQ H9 <21> QSB3 C7 DQSL VDDQ H9
QSB0 QSB1
<21> QSB0 DQSU VDDQ <21> QSB1 DQSU VDDQ
DQMB2 E7 A9 DQMB3 E7 A9
<21> DQMB2 DML VSS <21> DQMB3 DML VSS
DQMB0 D3 B3 DQMB1 D3 B3
<21> DQMB0 DMU VSS E1 <21> DQMB1 DMU VSS E1
VSS G8 VSS G8
C C
QSB#2 G3 VSS J2 QSB#3 G3 VSS J2
<21> QSB#2 DQSL VSS <21> QSB#3 DQSL VSS
QSB#0 B7 J8 QSB#1 B7 J8
<21> QSB#0 DQSU VSS <21> QSB#1 DQSU VSS
CLKB0 1 PX@ 2 M1 M1
RV72 40.2_0402_1% VSS M9 VSS M9
VSS P1 VSS P1
T2 VSS P9 DRAM_RST# T2 VSS P9
<21,22,23,25> DRAM_RST# RESET VSS RESET VSS
CLKB0# 1 PX@ 2 T1 T1
RV73 40.2_0402_1% L8 VSS T9 L8 VSS T9
ZQ/ZQ0 VSS ZQ/ZQ0 VSS
1
CV197
1
0.01U_0402_16V7K J1 B1 J1 B1
PX@ RV88 L1 NC/ODT1 VSSQ B9 RV89 L1 NC/ODT1 VSSQ B9
2
J9 NC/CS1 VSSQ D1 J9 NC/CS1 VSSQ D1

240_0402_1% NC/CE1 VSSQ 240_0402_1% NC/CE1 VSSQ
L9 D8 L9 D8
PX@ NCZQ1 VSSQ E2 PX@ NCZQ1 VSSQ E2
2
2
VSSQ E8 VSSQ E8
VSSQ F9 VSSQ F9
VSSQ G1 VSSQ G1
VSSQ G9 VSSQ G9
VSSQ VSSQ
96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3
K4W1G1646E-HC12_FBGA96 K4W1G1646E-HC12_FBGA96
X76@ X76@
+1.5VGS
+1.5VGS
1
PX@
1
PX@ RV75
RV74 4.99K_0402_1%
4.99K_0402_1%
15mil
2
B B
15mil
2
+VREFC_B1
+VREFC_B0
0.1U_0402_16V7K
CV150
PX@
1
1
0.1U_0402_16V7K
CV149
PX@ RV77
1
RV76 4.99K_0402_1%
4.99K_0402_1% PX@
2
PX@
2
2
2
+1.5VGS
+1.5VGS +1.5VGS
10U_0603_6.3V6M
CV151
1U_0402_6.3V6K
CV152
1U_0402_6.3V6K
CV153
1U_0402_6.3V6K
CV154
1U_0402_6.3V6K
CV155
1U_0402_6.3V6K
CV156
0.1U_0402_16V7K
CV157
0.1U_0402_16V7K
CV158
10U_0603_6.3V6M
CV161
10U_0603_6.3V6M
CV162
1U_0402_6.3V6K
CV163
1U_0402_6.3V6K
CV164
1U_0402_6.3V6K
CV165
1U_0402_6.3V6K
CV166
1U_0402_6.3V6K
CV167
0.1U_0402_16V7K
CV169
0.1U_0402_16V7K
CV170
0.1U_0402_16V7K
CV171
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
A A


ATI_Whistler_M2_VRAM_A0
5 4 3 2 1
5 4 3 2 1
UV11 UV12
+VREFC_B2 M8 E3 MDB33 +VREFC_B3 M8 E3 MDB55

H1 VREFCA DQL0 F7 MDB37 H1 VREFCA DQL0 F7 MDB50
VREFDQ DQL1 F2 MDB35 VREFDQ DQL1 F2 MDB54
MAB0 N3 DQL2 F8 MDB39 MAB0 N3 DQL2 F8 MDB51
MAB3 N2 A2 DQL5 G2 MDB34 MAB3 N2 A2 DQL5 G2 MDB52
MDB[32..63] MAB5 P2 A4 DQL7 MAB5 P2 A4 DQL7
<21> MDB[32..63] MAB6 R8 A5 MAB6 R8 A5
MAB7 R2 A6 D7 MDB44 MAB7 R2 A6 D7 MDB56
D
MAB8 T8 A7 DQU0 C3 MDB41 MAB8 T8 A7 DQU0 C3 MDB59 D
MAB9 R3 A8 DQU1 C8 MDB47 MAB9 R3 A8 DQU1 C8 MDB63
MAB10 L7 A9 DQU2 C2 MDB43 MAB10 L7 A9 DQU2 C2 MDB62
MAB[15..0] MAB11 R7 A10/AP DQU3 A7 MDB45 MAB11 R7 A10/AP DQU3 A7 MDB57
<21,24> MAB[15..0] A11 DQU4 A11 DQU4
MAB12 N7 A2 MDB40 MAB12 N7 A2 MDB61
MAB13 T3 A12 DQU5 B8 MDB46 MAB13 T3 A12 DQU5 B8 MDB58
MAB14 T7 A13 DQU6 A3 MDB42 MAB14 T7 A13 DQU6 A3 MDB60
MAB15 M7 A14 DQU7 MAB15 M7 A14 DQU7
A15/BA3 +1.5VGS A15/BA3 +1.5VGS
B_BA0 M2 B2 B_BA0 M2 B2
<21,24> B_BA0 N8 BA0 VDD D9 N8 BA0 VDD D9
B_BA1 B_BA1
B_BA2 M3 G7 B_BA2 M3 G7
<21,24> B_BA2 BA2 VDD K2 BA2 VDD K2
VDD K8 VDD K8
VDD N1 VDD N1
J7 VDD N9 CLKB1 J7 VDD N9
<21> CLKB1 CK VDD CK VDD
K7 R1 CLKB1# K7 R1
<21> CLKB1# K9 CK VDD R9 K9 CK VDD R9
CKEB1
<21> CKEB1 CKE/CKE0 VDD +1.5VGS CKE/CKE0 VDD +1.5VGS
K1 A1 ODTB1 K1 A1
<21> ODTB1 ODT/ODT0 VDDQ ODT/ODT0 VDDQ
L2 A8 CSB1#_0 L2 A8
<21> CSB1#_0 J3 CS/CS0 VDDQ C1 J3 CS/CS0 VDDQ C1
RASB1#
<21> RASB1# RAS VDDQ RAS VDDQ
K3 C9 CASB1# K3 C9
<21> CASB1# CAS VDDQ CAS VDDQ
L3 D2 WEB1# L3 D2
<21> WEB1# WE VDDQ E9 WE VDDQ E9
VDDQ F1 VDDQ F1
QSB4 F3 VDDQ H2 QSB6 F3 VDDQ H2
<21> QSB4 DQSL VDDQ <21> QSB6 DQSL VDDQ
QSB5 C7 H9 QSB7 C7 H9
<21> QSB5 DQSU VDDQ <21> QSB7 DQSU VDDQ
DQMB4 E7 A9 DQMB6 E7 A9
<21> DQMB4 D3 DML VSS B3 <21> DQMB6 D3 DML VSS B3
DQMB5 DQMB7
<21> DQMB5 DMU VSS <21> DQMB7 DMU VSS
E1 E1
VSS G8 VSS G8
QSB#4 G3 VSS J2 QSB#6 G3 VSS J2
<21> QSB#4 DQSL VSS <21> QSB#6 DQSL VSS
C QSB#5 B7 J8 QSB#7 B7 J8 C
<21> QSB#5 DQSU VSS M1 <21> QSB#7 DQSU VSS M1
VSS M9 VSS M9
VSS P1 VSS P1
DRAM_RST# T2 VSS P9 DRAM_RST# T2 VSS P9
<21,22,23,24> DRAM_RST# RESET VSS RESET VSS
T1 T1
L8 VSS T9 L8 VSS T9
ZQ/ZQ0 VSS ZQ/ZQ0 VSS
1
1
J1 B1 J1 B1
RV90 L1 NC/ODT1 VSSQ B9 RV91 L1 NC/ODT1 VSSQ B9
J9 NC/CS1 VSSQ D1 J9 NC/CS1 VSSQ D1
240_0402_1% NC/CE1 VSSQ 240_0402_1% NC/CE1 VSSQ
L9 D8 L9 D8
PX@ NCZQ1 VSSQ E2 PX@ NCZQ1 VSSQ E2
2
2
VSSQ E8 VSSQ E8
VSSQ F9 VSSQ F9
VSSQ G1 VSSQ G1
VSSQ G9 VSSQ G9
VSSQ VSSQ
96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3
K4W1G1646E-HC12_FBGA96 K4W1G1646E-HC12_FBGA96
X76@ X76@
+1.5VGS
+1.5VGS
1
PX@
RV78
1
CLKB1 1 PX@ 2 PX@ 4.99K_0402_1%

RV79 40.2_0402_1% RV80
4.99K_0402_1%
15mil
2
CLKB1# 1 PX@ 2
RV81 40.2_0402_1% +VREFC_B3
15mil
2
1
1
B B
0.1U_0402_16V7K
CV172
CV198 +VREFC_B2 PX@
1
0.01U_0402_16V7K RV82
1
0.1U_0402_16V7K
CV173
PX@ PX@ 4.99K_0402_1%

2
RV83 PX@
2
4.99K_0402_1%
2
PX@
2
2
+1.5VGS
+1.5VGS +1.5VGS
10U_0603_6.3V6M
CV174
1U_0402_6.3V6K
CV175
1U_0402_6.3V6K
CV176
1U_0402_6.3V6K
CV177
1U_0402_6.3V6K
CV178
1U_0402_6.3V6K
CV179
0.1U_0402_16V7K
CV180
0.1U_0402_16V7K
CV181
0.1U_0402_16V7K
CV182
0.1U_0402_16V7K
CV183
10U_0603_6.3V6M
CV184
10U_0603_6.3V6M
CV185
1U_0402_6.3V6K
CV186
1U_0402_6.3V6K
CV187
1U_0402_6.3V6K
CV188
1U_0402_6.3V6K
CV189
1U_0402_6.3V6K
CV190
0.1U_0402_16V7K
CV191
0.1U_0402_16V7K
CV193
0.1U_0402_16V7K
CV194
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
@
A A


ATI_Whistler_M2_VRAM_A1
5 4 3 2 1
A B C D E
+3VS +3VS_PS
R289
30mil 1 2
30mil
SHORT PAD@
0_0603_5% +3VS_PS
Close to Pin3 U9 2132R@
LVDS@ 19
TXEC+ LVDS_ACLK <27>
+DP_V33 L28 2 1 +DP_V33 40mil 3 20
LVDS_ACLK# <27>
FBMA-L11-201209-221LMA30T_0805 DP_V33 TXEC-
10U_0603_6.3V6M
0.1U_0402_16V4Z
0.1U_0402_16V4Z 60mil 13
LVDS@ 21
SWR_VDD TXE2+ LVDS_A2 <27>
Power
1 L87 2 1 +SWR_VDD 18 22 1
1 1 1
LVDS
PVCC TXE2- LVDS_A2# <27>
FBMA-L11-201209-221LMA30T_0805
C411
C410
C412
+SWR_V12 L29 1 2 +SWR_LX 60mil 12 23
LVDS_A1 <27>
SWR_LX TXE1+
2 2 2
4.7UH_PG031B-4R7MS_1.1A_20% 60mil 11 SWR_VCCK TXE1-
24
LVDS_A1# <27>
@ 27
7 VCCK 25
DP_V12 TXE0+ LVDS_A0 <27>
26
TXE0- LVDS_A0# <27>
2
RTD2132S
<7> DP0_AUXP_C AUX_P
DP-IN
1 14 TL_INVT_PWM
GPIO
<7> DP0_AUXN_C AUX_N GPIO(PWM OUT) 15 TL_INVT_PWM <27>
Close to Pin18 Close to Pin18 GPIO(Panel_VCC) TL_ENVDD <27>
5 16 APU_INVT_PWM
<7> DP0_TXP0_C LANE0P GPIO(PWM IN)
1
+SWR_VDD 6 17
<7> DP0_TXN0_C LANE0N GPIO(BL_EN) ENBKL <36>
R826
10U_0603_6.3V6M
0.1U_0402_16V4Z
22U_0603_6.3V6M
0.1U_0402_16V4Z
0.1U_0402_16V4Z
100K_0402_5%
1 1 1 1 1 Reserved for EC programming ROM CSCL 9 LVDS 29
CIICSCL1 MIICSCL1 EDID_CLK <27>
CSDA 10 28
Need EC confirm EDID EDID_DATA <27>
2
CIICSDA1 MIICDA1
C413
C414
C415
C416
C417
Other
R123
2 2 2 2 2 1 2 1K_0402_5% DP0_HPD_R 32 ROM 31 MIIC_SCL
<7> DP0_HPD HPD MIICSCL0 30 MIIC_SDA
LVDS@ 8 MIICSDA0
DP_REXT
1
4 33 +3VS_PS
DP_GND GND
2
Close to Pin13 R294
100K_0402_5% R295 LVDS@ RTD2132S-VE-CG_QFN32_5X5
12K_0402_1%
2
SA000069200
1
Close to L29 +1.2VS 4.7K_0804_8P4R_5%
2 SHORT PAD@ EDID_DATA 1 8 2
Vendor advise reserve
DEBUG@
DEBUG@1
DEBUG@
DEBUG@1
+SWR_V12 1 2 EDID_CLK 2 7
R375 0_0805_5% Change to 12Kohm 1% (DG ref.) MIIC_SDA 3 6
22U_0603_6.3V6M
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
20101114 MIIC_SCL 4 5
1 1 20110124 Modify 0:RevE W/O EEPROM
RP16
C418
C419
C420
C421
LVDS@
2 2 2 2
MIIC_SDA RA24 1 2 0_0402_5%

DEBUG@ T14 TEST POINT@
MIIC_SCL RA15 1 2 0_0402_5%
DEBUG@ T15
Close to EDID_DATA RA11 1 2 0_0402_5%
DEBUG@ TEST POINT@
EDID_CLK RA10 1 2 0_0402_5%
DEBUG@
Pin27
Close to Pin7
Vendor advise reserve
+3VS
SHORT PAD@
CSDA R357 1 2 0_0402_5%
CSCL 1 2 TL_DATA <36>
R340 0_0402_5%
TL_CLK <36>
SHORT PAD@
1
1
ő
Ţů
Ŧŭ
ġő
Ř
Ŏ
3 R59 R1458 3
47K_0402_5% 4.7K_0402_5%
2
APU_INVT_PWM
2132S@ 2132S@
1
D
2
G Q7
S 2N7002K_SOT23-3
3
1
Q8 C
1 2 2
<7> DP_INT_PWM
R62 2.2K_0402_5% B 2132S@
E MMBT3904_NL_SOT23-3
2132S@
3
1
3/1: SIT
R63 2132S@
4.7K_0402_5% Config. SDA/Pin#30 SCL/Pin#31 Function
2
0 0 Reserved
0 1 Internal mode
2132R
1 0 EP mode
2132S
R54 1 2 0_0402_5% 1 1 Reserved
SHORT PAD@
4 4

LVDS Translator - RTD2132S
Custom 0.1
VALGD MB L
A B C D E
5 4 3 2 1
LCD POWER CIRCUIT CMOS Camera

+3VS
JCMOS1
1 2
1 2
W=60mils @ JUMP_43X39
(20 MIL)
+3VS +LCDVDD_CONN CMOS@ +3VS_CMOS
W=60mils U72 Q83
D 1 +LCDVDD_CONN PMV65XP_SOT23-3~D D
5 VOUT
(20 MIL)
4.7U_0603_6.3V6K
VIN
D
3 1
C516
2 1 1 1
2 @ 1 4 GND CMOS@
R685 0_0402_5% SS C518 C519 @
G
2
3 0.1U_0402_16V4Z R02 10U_0603_6.3V6M
EN 2 R435CMOS@ 2 2
APL3512ABI-TRG_SOT23-5 150K_0402_5%
4.7V
<36> CMOS_ON#
1 R296 for CMOS shake issue reserve

<26> TL_ENVDD
C520 CMOS@
0.1U_0402_16V4Z
2
C
VGA LCD/PANEL BD. Conn. C
+LEDVDD B+
EMI@
R813
BKOFF# 1 2
<36> BKOFF#
1 1 FBMA-L11-201209-221LMA30T_0805
1
C539
R716 680P_0402_50V7K C541
10K_0402_5% EMI@ 4.7U_0805_25V6-K
2 2 @
For EMI
2
JLVDS1
1 2
1 2 TL_INVT_PWM <26>
3 4
5 3 4 6 USB20_N3_R
B B
BKOFF# 7 5 6 8 USB20_P3_R
9 7 8 10
11 9 10 12
<26> LVDS_ACLK 11 12 LVDS_A1 <26>
13 14
<26> LVDS_ACLK# 13 14 LVDS_A1# <26>
15 16
17 15 16 18
<26> LVDS_A2 17 18 LVDS_A0 <26>
19 20
<26> LVDS_A2# 19 20 LVDS_A0# <26>
21 22
23 21 22 24
<26> EDID_DATA 25 23 24 26 (60 MIL)
<26> EDID_CLK 25 26 +LCDVDD_CONN
27 28 +3VS
1/21 SIT change PN to SM070001N00 for action plan 29 27 28 30
+3VS 29 30 +3VS_CMOS
L58 EMI@ 31 32
USB20_P3 1 2 USB20_P3_R GNDGND
<13> USB20_P3 1 2 ACES_87142-3041-BS
ME@
<13> USB20_N3 USB20_N3 4 3 USB20_N3_R
4 3
WCM-2012-900T_4P
SM070001N00
A A

LVDS/CAMERA
Custom 0.1
VALGD MB L
5 4 3 2 1
A B C D E
1 1
1/21 SIT downsize to 0402, BLM15BB121SN1D 0402 (Murata)
BLM15BB121SN1D 0402 SM010005X00

RED
<12> DAC_RED
EMI@ L30
BLM15BB121SN1D 0402 SM010005X00
GREEN
<12> DAC_GRN
EMI@ L31
BLM15BB121SN1D 0402 SM010005X00
BLUE
<12> DAC_BLU
10P_0402_50V8J
10P_0402_50V8J
10P_0402_50V8J
10P_0402_50V8J
10P_0402_50V8J
10P_0402_50V8J
C522
C523
C524
C525
C526
C527
EMI@ L32
1 1 1 1 1 1
2 2 2 2 2 2 +5V_DISPLAY
150_0402_1%
150_0402_1%
150_0402_1%
RV194
RV195
RV196
JCRT1
6
TEST POINT@ PAD T66 NC11 11
RED 1
7
CRT_DDC_DAT_CONN 12
GREEN 2
8 G 16
2 JVGA_HS_R 13 17 2
3 G
BLUE
9
JVGA_VS_R 14
4
10
CRT_DDC_CLK_CONN 15
5
SUYIN_070546FR015S251ZR
ME@
+5VS
1 1
C529 C531
U10
0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 1 8 1 2
VCC_SYNC BYP C6 0.22U_0402_10V6K +5V_DISPLAY
2 3 RED
+3VS VCC_VIDEO VIDEO1
1
7 4 GREEN
VCC_DDC VIDEO2 R31 R3333
1 4.7K_0402_5% 4.7K_0402_5%
<12> CRT_DDC_DATA 10 5 BLUE
C537 DDC_IN1 VIDEO3
2
0.1U_0402_16V4Z
3 2 11 9 CRT_DDC_DAT_CONN 3
<12> CRT_DDC_CLK DDC_IN2 DDC_OUT1
13 12 CRT_DDC_CLK_CONN
<12> CRT_VSYNC SYNC_IN1 DDC_OUT2
15 14 JVGA_VS 1 R3334 2 JVGA_VS_R

<12> CRT_HSYNC SYNC_IN2 SYNC_OUT1 22_0402_5%
R3335
6 16 JVGA_HS 1 2 JVGA_HS_R
GND SYNC_OUT2 22_0402_5%
TPD7S019-15DBQR_SSOP16
4 4

CRT Connector
Custom 0.1
VALGD MB L
A B C D E
5 4 3 2 1
+5V_DISPLAY
1/21 SIT change PN to SM070003K00 for action plan U73
+5VS 3
W=40mils
L35 EMI@ SM070003K00 OUT
1
HDMI_CLK+_CK 1 2 HDMI_CLK+_CONN 1
<7> HDMI_CLK+_CK 1 2 +3VS IN
1 C543
2
HDMI_CLK-_CK 4 3 HDMI_CLK-_CONN C544 GND 0.1U_0402_16V4Z 2
<7> HDMI_CLK-_CK 4 3 0.1U_0402_16V4Z
2
WCM-2012HS-900T 2 AP2330W-7_SC59-3
D R485 ZZZ3 45@ D
L36 EMI@ SM070003K00 1M_0402_5%
HDMI_TX0+_CK 1 2 HDMI_TX0+_CONN
<7> HDMI_TX0+_CK 1 2
2
1
<7> HDMI_TX0-_CK HDMI_TX0-_CK 4 3 HDMI_TX0-_CONN TMDS_B_HPD# 1 6
4 3 <7> TMDS_B_HPD#
HDMI Logo
WCM-2012HS-900T
Q93A RO0000003HM
2
L37 EMI@ SM070003K00 DMN66D0LDW-7_SOT363-6
<7> HDMI_TX1+_CK HDMI_TX1+_CK 1 2 HDMI_TX1+_CONN R488
1 2
20K_0402_5%
<7> HDMI_TX1-_CK HDMI_TX1-_CK 4 3 HDMI_TX1-_CONN JHDMI1
1
4 3 HDMI_DET 19
WCM-2012HS-900T 18 HP_DET
+5V_DISPLAY +5V
17
L38 EMI@ SM070003K00 HDMIDAT_R 16 DDC/CEC_GND
HDMI_TX2+_CK 1 2 HDMI_TX2+_CONN HDMICLK_R 15 SDA
<7> HDMI_TX2+_CK 1 2 SCL
14
13 Reserved
HDMI_TX2-_CK 4 3 HDMI_TX2-_CONN HDMI_CLK-_CONN 12 CEC 20
<7> HDMI_TX2-_CK 4 3 CK- GND
11 21
WCM-2012HS-900T HDMI_CLK+_CONN 10 CK_shield GND 22
C CK+ GND C
HDMI_TX0-_CONN 9 23
8 D0- GND For LAN
HDMI_TX0+_CONN 7 D0_shield CHASSIS1_GND
+3VS HDMI_TX1-_CONN 6 D0+
5 D1-
HDMI_TX1+_CONN 4 D1_shield
HDMI_TX2-_CONN 3 D1+
2 D2-
HDMI_TX2+_CONN 1 D2_shield
D2+
CONCR_099ATAC19NBLCNF
ME@
+3VS Q63A
2
+5V_DISPLAY RP21 2N7002DW-T/R7_SOT363-6
8 1 HDMIDAT_NB
7 2 HDMIDAT_R <7> HDMICLK_NB 1 6 HDMICLK_R
6 3 HDMICLK_NB
5
5 4 HDMICLK_R
2.2K_0804_8P4R_5% 4 3 HDMIDAT_R
<7> HDMIDAT_NB
Q63B
B
2N7002DW-T/R7_SOT363-6
#11/5 follow Design Guide#48890 B
HDMI_CLK-_CONN R784 1 2 604_0402_1%

HDMI_CLK+_CONN R786 1 2 604_0402_1%
HDMI_TX0-_CONN R788 1 2 604_0402_1%
ESD HDMI_TX0+_CONN R790 1 2 604_0402_1%
HDMI_TX1-_CONN R792 1 2 604_0402_1%
HDMI_TX1+_CONN R796 1 2 604_0402_1%
@ESD@ D32 @ESD@ D28 @ESD@ D33 HDMI_TX2+_CONN R807 1 2 604_0402_1%
HDMIDAT_R 9 10 1 1 HDMIDAT_R HDMI_CLK-_CONN 9 10 1 1 HDMI_CLK-_CONN HDMI_TX0-_CONN 9 10 1 1 HDMI_TX0-_CONN HDMI_TX2-_CONN R800 1 2 HDMI_GND
604_0402_1%
3
HDMICLK_R 8 9 2 2 HDMICLK_R HDMI_CLK+_CONN 8 9 2 2 HDMI_CLK+_CONN HDMI_TX0+_CONN 8 9 2 2 HDMI_TX0+_CONN +3VS
Q93B
HDMI_DET 7 7 4 4 HDMI_DET HDMI_TX1-_CONN 7 7 4 4 HDMI_TX1-_CONN HDMI_TX2-_CONN 7 7 4 4 HDMI_TX2-_CONN
5
6 6 5 5 HDMI_TX1+_CONN 6 6 5 5 HDMI_TX1+_CONN HDMI_TX2+_CONN 6 6 5 5 HDMI_TX2+_CONN
DMN66D0LDW-7_SOT363-6
4
3 3 3 3 3 3
8 8 8
YSCLAMP0524P_SLP2510P8-10-9 YSCLAMP0524P_SLP2510P8-10-9 YSCLAMP0524P_SLP2510P8-10-9

A A

HDMI CONN
B 0.1
VALGD MB L
5 4 3 2 1
A B C D E
Mini-Express Card for WLAN/WiMAX(Half)
1 1
+3VS_WLAN
JUMP@
+3VS 80mil +3VS_WLAN
@ 1 1@
J6
C548 C547
1 2 4.7U_0603_6.3V6K 0.1U_0402_16V4Z
1 2 +1.5VS
2 2
JUMP_43X79
JWLN1
1 2
<13> FCH_PCIE_WAKE# 1 2
3 4
5 3 4 6
<12> BT_DISABLE# 5 6
<13> CLKREQ_WLAN# 7 8
9 7 8 10
11 9 10 12
<11> CLK_PCIE_WLAN1# 11 12
13 14
<11> CLK_PCIE_WLAN1 15 13 14 16
17 15 16 18
19 17 18 20
21 19 20 22 WL_OFF# <12>
21 22 APU_PCIE_RST# <11,16,31>
23 24 +3VS_WLAN
2 <5> PCIE_PRX_DTX_N1 25 23 24 26
2
<5> PCIE_PRX_DTX_P1 25 26
27 28
29 27 28 30 1 R501 2 @ 0_0402_5%
29 30 FCH_SCLK0 <10,13,9>
31 32 1 R502 2 @ 0_0402_5%
<5> PCIE_PTX_C_DRX_N1 31 32 FCH_SDATA0 <10,13,9>
33 34
<5> PCIE_PTX_C_DRX_P1 35 33 34 36
+3VS_WLAN 35 36 USB20_N2 <13>
37 38
39 37 38 40 USB20_P2 <13>
41 39 40 42
43 41 42 44
100_0402_1% 45 43 44 46
R505 47 45 46 48
1 2 49 47 48 50
<36,37> EC_TX 1 2 EC_RX_R 51 49 50 52
<36,37> EC_RX 51 52
R506
100_0402_1% 53 54
GND1 GND2
LOTES_AAA-PCI-046-K01
2
For EC to detect ME@
R507
debug card insert. 100K_0402_5%
3 3
Reserve for SW mini-pcie debug card.

Series resistors closed to KBC side.
4 4

Mini-Card/NEW Card/SIM
0.1
VALGD MB L
A B C D E
5 4 3 2 1
For LAN +3VALW +3V_LAN

+LX
JUMP@ Close together
J12
LL2 LL3 SWR@
1 2 LL1 SWR@
1 2 +LX_R 1 2 +LX FBMA-L11160808601LMA10T_2P FBMA-L11160808601LMA10T_2P
1000P_0402_50V7K
+1.1_AVDDL_L 1 2 +1.1_AVDDL 1 2 +LX_R
10U_0603_6.3V6M
4.7UH_SIA4012-4R7M_20%
0.1U_0402_16V4Z
JUMP_43X79
CL1
CL2
0.1U_0402_16V4Z
1U_0402_6.3V4Z
4.7U_0603_6.3V6K
1 1
CL4
CL5
CL6
D
Note: Place Close to LAN chip 1 1 1 D
3 1
D
2 2 LL1 DCR< 0.15 ohm
CL3
Rate current > 1A
RL3 2 2 2
QL1
G
2
LAN_PWR_ON# 2 1 PMV65XP_SOT23-3~D
<36> LAN_PWR_ON# 10U
2
10K_0402_5% CL7 SWR@SWR@SWR@
1
0.1U_0402_16V7K Place close to Pin34
Close to
Pin40
Vendor recommand reseve the

PU resistor close LAN chip
RL4 1 2 4.7K_0402_5% UL1 8172@ +3V_LAN

+3V_LAN
DEBUG@
APU_PCIE_RST#
<11,16,30> APU_PCIE_RST#
8172
0.1U_0402_16V4Z
1U_0402_6.3V4Z
CL10
CL8
1 1
C
Place Close to Chip UL1 C
DEBUG@ 2 2
CL9 1 2 0.1U_0402_16V7K PCIE_PRX_C_DTX_N0 29 38 RL12 10K_0402_5%
<5> PCIE_PRX_DTX_N0 TX_N LED_0 39 2 LDO@ 1 mount RL12 if use LDO modue
CL11 1 2 0.1U_0402_16V7K PCIE_PRX_C_DTX_P0 30
Atheros LED_1 23
<5> PCIE_PRX_DTX_P0 TX_P LED_2
AR8151/AR8161 Place close to Pin16
36
<5> PCIE_PTX_C_DRX_N0 RX_N 12 MDI0-
35 TRXN0 11 MDI0+ MDI0- <32>
<5> PCIE_PTX_C_DRX_P0 RX_P TRXP0 MDI0+ <32>
15 MDI1-
32 TRXN1 14 MDI1- <32>
MDI1+
<11> CLK_PCIE_LAN# 33 REFCLK_N TRXP1 18 MDI1+ <32>
<11> CLK_PCIE_LAN REFCLK_P TRXN2 17
APU_PCIE_RST# 2 TRXP2 21
PERST# TRXN3 20
PCIE_WAKE#_R 3 TRXP3 Place Close to PIN1
RL7 1 2 0_0402_5% W AKE#
<36> LAN_WAKE# +3V_LAN
25 10 LAN_RBIAS 1 2
RL9 1 2 4.7K_0402_5% 26 SMCLK RBIAS RL8 2.37K_0402_1%
+3V_LAN SMDATA
DEBUG@ Place Close to PIN1
28 1 +3V_LAN
NC VDD33
CL12
CL13
CL14
CL15
CL16
27
1000P_0402_50V7K
Vendor recommand reseve the
10U_0603_6.3V6M
10U_0603_6.3V6M
1U_0402_6.3V4Z
0.1U_0402_16V4Z
TESTMODE 1 1 1 1
2
PU resistor close LAN chip 40 +LX
LX +LX
LAN_XTALO 7 @ don't @ (could be B C cost done)
1
DEBUG@ LAN_XTALI 8 XTLO RL10 30K_0402_5% 2 2 2 2
RL11 1 2 4.7K_0402_5% XTLI 5 +1.7_VDDCT 1 2
+3V_LAN VDDCT/ISOLAN +3V_LAN
4
<13> CLKREQ_LAN# CLKREQ# 24 DEBUG@ DEBUG@
B DVDDL/PPS 37 +LX_R B
+1.1_AVDDL 13 DVDDL_REG/DVDDL
+1.1_AVDDL 19 AVDDL +2.7_AVDDH
+1.1_AVDDL 31 AVDDL 16 +3V_LAN
+1.1_AVDDL_L 34 AVDDL AVDDH/AVDD33 22 +2.7_AVDDH
+1.1_AVDDL 6 AVDDL AVDDH 9 +2.7_AVDDH
AVDDL_REG/AVDDL AVDDH_REG
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
CL17
CL18
CL19
CL20
CL21
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1 1 1 1 1
CL22
CL23
CL24
CL25
CL26
41 1 1 1 1 1
GND
AR8162-BL3A-R_QFN40_5X5 DEBUG@ DEBUG@
2 2 2 Near 2 2 8162@
2 2 2 2 2
Pin6
DEBUG@
Near
Near Near Near Pin9 Near Near
GCLK@
Pin13 Pin19 Pin31 RL13 1 2 0_0402_5% Pin22 Pin37
<38> GCLK_LAN_25MHZ
1
CL27
value shoud be discuss 5P_0402_50V8C
2 GCLK@
ORB 5P LAN_XTALI
A YL1 NOGCLK@ LAN_XTALO A

4 3
NC OSC
1 2
OSC NC
1 25MHZ_10PF_7V25000014 1
CL28 CL29
15P_0402_50V8J 15P_0402_50V8J Security Classification Compal Secret Data Compal Electronics, Inc.
NOGCLK@ NOGCLK@ 2012/11/13 2013/11/12 Title
2 2 Issued Date Deciphered Date
LAN-AR8162/8172
Custom 0.1
VALGD MB L
5 4 3 2 1
5 4 3 2 1
ESD
@ESD@
DL1
Place Close to TL1 AZC099-04S.R7G_SOT23-6 Reserve gas tube for EMI go rural solution
MDI1+ 1 4 MDI0+
I/O1 I/O3
D D
DL1 2
GND VDD
5
1'S PN:SC300001G00
2'S PN:SC300002E00 MDI0- 3
I/O2 I/O4
6 MDI1-
RL14 EMI@ CL30 EMI@

1 2 1 2
CHASSIS1_GND
75_0805_5% 1000P_1206_2KV7K
2 1
TL1
DLL1
MDI0+ 1 16 MDO0+ BS4200N-C-LV_SMB-F2
<31> MDI0+ 2 TD+ TX+ 15
MDI0- MDO0- EMI@
<31> MDI0- TD- TX-
3 14 MCT
4 CT CT 13
5 NC NC 12
NC NC Place Close to TL1
6 11 MCT
C CT CT C
1 MDI1+ 7 10 MDO1+
<31> MDI1+ RD+ RX+
MDI1- 8 9 MDO1-
<31> MDI1- RD- RX-
EMI@ CL31
0.01U_0402_16V7K
2 MHPC_NS681612A
@EMI@ CL63 1 2 0.1U_0603_50V7K
@EMI@ CL61 1 2 0.1U_0603_50V7K
ESD@ CL32 1 2 0.1U_0402_16V7K
ESD@ CL33 1 2 0.1U_0402_16V7K
SIT: For ESD request

JLAN1
MCT 8 CHASSIS1_GND
PR4-
MCT 7
PR4+
B B
MDO1- 6
PR2-
MCT 5
PR3-
MCT 4
PR3+
MDO1+ 3
PR2+
MDO0- 2
PR1-
MDO0+ 1
PR1+
10
SHLD1
9
SHLD2
PS_HPKR0125-08A1A0R
ME@
CHASSIS1_GND
A A

LAN_Transformer
B 0.1
VALGD MB L
5 4 3 2 1
5 4 3 2 1
2 Channel
D D
SIT: Change power rial from +3VS to +3VGS. SMSC thermal sensor
placed near VRAM
+3VGS
SA00001Z710
<17> REMOTE1+ U99
1 1 8 EC_SMB_CK2
VDD SCLK EC_SMB_CK2 <17,36>
C587 REMOTE1+ 2 7 EC_SMB_DA2
D+ SDATA EC_SMB_DA2 <17,36>
2200P_0402_50V7K
2 REMOTE1- 3 6
<17> REMOTE1- D- ALERT#
C +3VGS 1 R335 2 4 5 C
THERM# GND
4.7K_0402_5%
@ ADM1032ARMZ-2REEL_MSOP8
SMBus address: 4D
SIT: Change power rial from +3VS to +3VGS. 1001101x
B B
MINI WLAN VGA CPU

H1 H2 H3 H4 H5 H6 H7
H_3P3 H_3P3 H_3P3 H_3P3 H_3P8 H_3P8 H_3P8 FD1 FD2 FD3 FD4
1
1
FAN1 Conn ME@ ME@ ME@ ME@
ME@ ME@ ME@ ME@ ME@ ME@ ME@
SIV: change to H=4p6
+5VS
ZZZ 14@
R581
JFAN1
2 1 SHORT PAD@ 1
2 1 H14 H15 H19 H20 H21 H22 H23
0_0603_5% <36>
<36> EC_TACH
EC_FAN_PWM
3 2
3
H_2P8 H_2P8 H_2P8 H_2P8 H_4P6 H_2P8 H_2P8 R
4 H16 H17 H24 H25
5 4 H_3P0X4P0N H_7P0N H_3P0N H_3P0N
2 G5 VALGC_DIS_PCB
6 DA6000YR100
1
1
C591 G6
10U_0603_6.3V6M ACES_85205-04001
1
1 ME@ ZZZ1 15@
ME@ ME@ ME@ ME@ ME@ ME@ ME@
SP020008X00
ME@ ME@ ME@ ME@
A
E A
VALGD_DIS_PCB M/B
DA6000YR000
M/B
⚻
⫼
㨊
⚻
⫼
Fintek-Thermal IC/FAN/screw
Custom 0.1
VALGD MB L
5 4 3 2 1
A B C D E F G H
SATA HDD Conn.

Near Connector
JHDD1
1
SATA_ITX_C_DRX_P0 C1184 2 1 0.01U_0402_25V7K SATA_ITX_DRX_P0 2 GND
<12> SATA_ITX_C_DRX_P0 RX+
<12> SATA_ITX_C_DRX_N0 SATA_ITX_C_DRX_N0 C1185 2 1 0.01U_0402_25V7K SATA_ITX_DRX_N0 3
4 RX-
SATA_DTX_C_IRX_N0 C596 1 2 0.01U_0402_25V7K SATA_DTX_IRX_N0 5 GND
<12> SATA_DTX_C_IRX_N0 SATA_DTX_C_IRX_P0 C597 1 2 0.01U_0402_25V7K SATA_DTX_IRX_P0 6 TX-
<12> SATA_DTX_C_IRX_P0 7 TX+
GND
1 1
8
9 3.3V 26
10 3.3V boss 25
11 3.3V boss
12 GND 24
13 GND GND 23
14 GND GND
J10 5V
JUMP@ 15
1 2 +5VS_HDD 16 5V
+5VS 1 2 5V
17
JUMP_43X39 18 GND
19 Rsv
20 GND
21 12V
+5VS_HDD 22 12V
12V
Near HDD LCN_ASF98-2231S10-0002
1 1 1 ME@
C598 C599 C602

1000P_0402_50V7K 0.1U_0402_16V4Z 10U_0603_6.3V6M
2 2 2
ODD Power Control

SIT: 3/1 Change footprint of JHDD1 from SANTA_191501-1_22P to
LCN_ASF98-2231S10-0002_22P (DC010005W00 toDC010009C00)
Per-MP: 4/3 un-pop ODD power control circuits
2 2
JUMP@
J9
1 2
1 2 +5V_ODD FOR 15"
+5VALW +5VS JUMP_43X79
SATA ODD FFC Conn.
Near Connector
S
3 1 JODD2
1 1
1
1
@ Q99 @ <12> SATA_ITX_C_DRX_P1 SATA_ITX_C_DRX_P1 15@C605

15@C605 1 2 0.01U_0402_25V7K SATA_ITX_DRX_P1_15 2
PMV65XP_SOT23-3~D C604 SATA_ITX_C_DRX_N1 15@C606
15@C606 1 2 0.01U_0402_25V7K SATA_ITX_DRX_N1_15 3 2
G
<12> SATA_ITX_C_DRX_N1
2
R568 @ 0.1U_0402_16V4Z 4 3
10K_0402_5% R675 2 SATA_DTX_C_IRX_N1 15@C618
15@C618 1 2 0.01U_0402_25V7K SATA_DTX_IRX_N1_15 5 4
100K_0402_5% <12> SATA_DTX_C_IRX_N1 SATA_DTX_C_IRX_P1 15@C617
15@C617 1 2 0.01U_0402_25V7K SATA_DTX_IRX_P1_15 6 5
1
2
1 2 <12> SATA_DTX_C_IRX_P1 1
SHORT PAD@ 2 ODD_DETECT#_R 7 6
C608 R710 0_0402_1% +5V_ODD 8 7
8
1
@ 1 10U_0603_6.3V6M R711 1 @ 2 0_0402_5% 9

@ 2 <13> ODD_DETECT# ODD_DA# 10 9
OUT
C607 <36> ODD_DA# 10 11

GND 12
0.01U_0402_25V7K GND
2 2 1 R555 2
<12> ODD_EN IN +3VS
@ 10K_0402_5% ACES_88058-100N
GND
ME@
Q100 SP010016C00
DTC124EKAT146_SC59-3
3
#11/9 follow QAWYA

Q96
3 2N7002K_SOT23-3 Co-lay 3
@ 1 3
S
<13> ODD_DA#_FCH
FOR 14"
G
2
+3VS
SATA ODD Conn.
Near Connector JODD1
1
SATA_ITX_C_DRX_P1 14@
14@C616
C616 1 2 0.01U_0402_25V7K SATA_ITX_DRX_P1_14 2 GND
SATA_ITX_C_DRX_N1 14@
14@C615
C615 1 2 0.01U_0402_25V7K SATA_ITX_DRX_N1_14 3 A+
4 A-
SATA_DTX_C_IRX_N1 14@
14@C614
C614 1 2 0.01U_0402_25V7K SATA_DTX_IRX_N1_14 5 GND
SATA_DTX_C_IRX_P1 14@
14@C613
C613 1 2 0.01U_0402_25V7K SATA_DTX_IRX_P1_14 6 B-
7 B+
GND
ODD_DETECT#_R 8
+5V_ODD 9 DP
10 +5V 14
ODD_DA# 11 +5V GND 15
12 MD GND 16
13 GND GND 17
GND GND
4 SANTA_202801-1 4
ME@

HDD/ODD/BT Connector
Custom 0.1
VALGD MB L
A B C D E F G H
5 4 3 2 1
CX20757 Sense resistors must be

connected same power
High Definition Audio Codec SoC that is used for VAUX_3.3
With Integrated Class-D Stereo
RA5 1 2 5.11K_0402_1%
Amplifier. +3VS
An integrated 5 V to 3.3 V Low-dropout RA6 10K_0402_1%

mount RA6 on the Jack Sense circuit
voltage regulator (LDO). 1 2 to configure Port-C for mono MIC.
An integrated 3.3 V to 1.8V Low-dropout JSENSE RA7 1 2 20K_0402_1%

voltage regulator (LDO). RA8 1 2 39.2K_0402_1% PLUG_IN
PLUG_IN <37>
+VREF_1V65 CA3 vendor suggest
SIT:For no Speaker Hum Noise feature
For Universal jack
D change to 2.2U Don't support LINE_IN function D
+LDO_OUT_3.3V
RA7 could be @
RA25 1 2 0_0402_5% +3V_AVDD_HP
1U_0603_10V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+3VLP
2.2U_0603_6.3V4Z
1 1 2 1 AVDD_3.3 pinis output of
1 2 0_0402_5%
CA1
CA2
CA4
RA26 @
internal LDO. NOT connect
0.1U_0402_16V4Z
4.7U_0603_6.3V6K
+3VS
CA3
1 1 to external supply.
CA5
CA6
2 2 1 2
2 @ 2
+3VS
+3VS
1U_0603_10V4Z
1U_0603_10V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1 1
CA8
CA9
1 1
CA15
CA10
@
Should be same supply rail as used for @
2 2 Layout Note:Path from +5VS to LPWR_5.0
PCH HDA bus controller section 2 2
RPWR_5.0 must be very low
resistance (<0.01 ohms)
+VDDIO_HDA
4.7U_0603_6.3V6K
0.1U_0402_16V4Z
+LDO_1.8V +5VS
+3VS 1 2 1 1
CA16
CA17
RA4 0_0402_1%
0.1U_0402_16V4Z
4.7U_0603_6.3V6K
+5VS
SHORT PAD@ 1 1
CA18
CA19
10 mils
0.1U_0402_16V4Z
0.1U_0402_16V4Z
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
@ 2 2
1 1 1 1
CA20
CA21
CA22
CA23
@
4.7U_0603_6.3V6K
0.1U_0402_16V4Z
2 2
1 1
@
CA24
CA25
2 2 2 2
0.1U_0402_16V4Z
@EMI@ 2 2 For Layout
18
29
27
28
24
C 1 C
3
7
2
CA26
CA7 @EMI@ UA1
1 RA21 2 For Layout
FILT_1.8
VDDO_3.3
DVDD_3.3
AVDD_3.3
VDD_IO
VREF_1.65V
AVDD_5V
AVDD_HP
Please bypass caps very close to device.
22P_0402_50V8J 33_0402_5% 13 2
LPWR_5.0 16
HDA_RST_AUDIO# 9 RPWR_5.0 11
<13> HDA_RST_AUDIO# RESET# CLASS-D_REF
HDA_BITCLK_AUDIO 5
<13> HDA_BITCLK_AUDIO BIT_CLK
HDA_SYNC_AUDIO 8 38 JSENSE
<13> HDA_SYNC_AUDIO SYNC JSENSE
RA9 1 2 33_0402_5% HDA_SDIN0_R 6
<13>
<13> HDA_SDIN0
HDA_SDOUT_AUDIO
HDA_SDOUT_AUDIO 4 SDATA_IN
SDATA_OUT MICBIASB
MICBIASC
34
35
+MICBIASB
+MICBIASC
For EMI HGNDA, HGNDB 80mils
SIV:For (Port-B) THD+N
PC_BEEP 10 32 MICB_L
39 PC_BEEP PORTB_L_LINE 33 MICB_R APPLE_MIC RA16 1 2 100_0402_1% CA28 1 22.2U_0402_6.3V6M HGNDB
<36> EC_MUTE# SPKR_MUTE# PORTB_R_LINE Universal Jack NOKIA_MIC RA12 1 2 100_0402_1% CA27 1 22.2U_0402_6.3V6M HGNDA
HGNDB <37>
HGNDA <37>
30 APPLE_MIC External MIC HP_L RA13 1 2 15_0402_5% HPOUT_L
PORTD_A_MIC HPOUT_L <37>
31 NOKIA_MIC HP_R RA14 1 2 15_0402_5% HPOUT_R
PORTD_B_MIC HPOUT_R <37>
1 25 HGNDA
40 DMIC_DAT/GPIO1 HGNDA 26 HGNDB
For EMI MIC_IN 36
DMIC_CLK / MUSIC_REQ/GPIO0 HGNDB
22 HP_L
Internal analog MIC 37 MUSIC_REQ/GPIO0/PORTC_L_MIC PORTA_L 23 HP_R
For Universal jack
EMI@ GPIO1/PORTC_R_MIC PORTA_R Headphone
CA64 1 2 0.1U_0402_16V7K
SIT:For (Port-B) THD+N
EMI@ SPK_L2+ 12
CA65 1 2 0.1U_0402_16V7K SPK_L1- 14 LEFT+ CA36
LEFT- MICB_L RA17 1 2 100_0402_1% 1 2 HP_L
EMI@ Internal SPEAKER 21 2.2U_0402_6.3V6M
CA66 1 2 0.1U_0402_16V7K SPK_R2+ 17 AVEE 19 CA46
SPK_R1- 15 RIGHT+ FLY_P 20 1 2 MICB_R RA18 1 2 100_0402_1% 1 2 HP_R
0.1U_0402_16V4Z
2.2U_0603_6.3V4Z
RIGHT- FLY_N CA29 1U_0603_10V4Z 2.2U_0402_6.3V6M
1 2
RA20 1 2 3K_0402_5%
CA35
CA30
GND
+MICBIASB RA19 1 2 3K_0402_5%

B 2 1 B
CX20751-11Z_QFN40
41
follow vendor suggest

& reserver default design
PC Beep JSPK1
EC Beep
wide 40MIL 6
5 GND2
GND1
<36> BEEP# 1 2 RA492
CA37 0.1U_0402_16V4Z 1 2 PC_BEEP SPK_R1- EMI@ LA1 1 2
FBMA-L11-160808-121LMT_0603 SPK_R1-_CONN 4
1 2 33_0402_5% SPK_R2+ EMI@ LA2 1 2
FBMA-L11-160808-121LMT_0603 SPK_R2+_CONN 3 4
<13> HDA_SPKR 3
CA45 0.1U_0402_16V4Z SPK_L1- EMI@ LA3 1 2
FBMA-L11-160808-121LMT_0603 SPK_L1-_CONN 2
ICH Beep Place colose to Codec chip SPK_L2+ EMI@ LA4 1 2
FBMA-L11-160808-121LMT_0603 SPK_L2+_CONN 1 2
1
1
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
SP02000H700
RA22 +MICBIASC +5VS ME@
1 1 1 1
10K_0402_5% ACES_88231-04001
CA38
CA39
CA40
CA43
ESD
DEBUG@
2
DA3
RA23 2 2 2 2 SPK_R1-_CONN 6 3 SPK_L2+_CONN
I/O4 I/O2
2.2K_0402_5%
2
MIC1 CA41 1U_0603_10V4Z EMI@ EMI@ EMI@ EMI@ 5 2

A 1 EXT_MIC 1 2 MIC_IN VDD GND A
2 GNDA
SIT:For EMI requriement
1
WM-64PCY_2P SPK_R2+_CONN 4 1 SPK_L1-_CONN
0.1U_0402_16V4Z
MIC@ I/O3 I/O1

AZC099-04S.R7G_SOT23-6
2
CA44
@ESD@
@
CX20757-11Z Codec
Custom 0.1
VALGD MB L
5 4 3 2 1
A B C D E
+3VALW
+3VLP
#9/11 follow LA-9901 R312
SHORT PAD@
2 1 +3VALW_EC 885N@ 4/11 SVT: change RP11 form 10K to 100K (8P4R) SD309100300
L3311 2 +5VALW
+3VALW +EC_AVCC
FBM-11-160808-601-T_0603 2 0_0603_5% C5351 2
100P_0402_50V8J
RP11 +3VS +3VALW
C428 USB_ON# 8 1
0.1U_0402_16V4Z 1 1 1 1
0.1U_0402_16V4Z
C423
0.1U_0402_16V4Z
C424
1000P_0402_50V7K
C429
1000P_0402_50V7K
C427
EC_TACH 7 2
1 2 1 ECAGND +EC_AVCC VGA_GATE# 6 3 BATT_TEMP 1 2
L332 FBM-11-160808-601-T_0603 @EMI@ @EMI@ EC_PME# 5 4 C432 100P_0402_50V8J
2 2 2 2 ACIN 1 2
111
125
U12 100K_0804_8P4R_5% C433 100P_0402_50V8J
22
33
96
67
9
ECAGND
EC_VDD0
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/AVCC
1 +3VS 1
1 21 ADP_65
<13> GATEA20 2 GATEA20/GPIO00 GPIO0F 23 BEEP# ADP_65 <42>
RP25
<13> KBRST# 3 KBRST#/GPIO01 BEEP#/GPIO10 26 BEEP# <35> 8 1
TL_CLK
<11> SERIRQ 4 SERIRQ GPIO12 27 EC_FAN_PWM <33> 7 2
ACOFF TL_DATA +3VALW
<11> LPC_FRAME# LPC_AD3 5 LPC_FRAME# ACOFF/GPIO13 ACOFF <43> TP_CLK 6 3
<11> LPC_AD3 LPC_AD3 Ra
LPC_AD2 7 PWM Output TP_DATA 5 4 @
<11> LPC_AD2 8 LPC_AD2 63
LPC_AD1 BATT_TEMP BRDID R310 1 2 100K_0402_5%
<11> LPC_AD1 10 LPC_AD1 BATT_TEMP/GPIO38 64 BATT_TEMP <42>
LPC_AD0 LPC & MISC VGA_IMVP_IMON 2.2K_0804_8P4R_5%
<11> LPC_AD0 LPC_AD0 GPIO39 65 VGA_IMVP_IMON <50>
R311 1 2 0_0402_5%
12 ADP_I/GPIO3A 66 ADP_ID ADP_I <42,43>
<11,15> CLK_PCI_EC CLK_PCI_EC AD Input GPIO3B ADP_ID <41>
PLT_RST# 13 75 BRDID Rb SHORT PAD@
1 2 <11> PLT_RST# EC_RST# 37 PCIRST#/GPIO05 GPIO42 76 ENBKL
+3VALW 20 EC_RST# IMON/GPIO43 ENBKL <26>
R306 47K_0402_5% EC_SCI#
<13> EC_SCI# 38 EC_SCII#/GPIO0E
2 <42> BATT_LEN# GPIO1D 68 ADP_90 ID BRD ID Ra Rb Vab
DAC_BRIG/GPIO3C 70 ADP_135 ADP_90 <42>
C434
EN_DFAN1/GPIO3D 71 ADP_135 <42>
0.1U_0402_16V4Z
1
DA Output IREF/GPIO3E
KSI0 55 72 4/11 SVT: Del 1V_ALW_EN +3VALW 0 R10 MP x 0 0V
KSI1 56 KSI0/GPIO30 CHGVADJ/GPIO3F
KSI2 57 KSI1/GPIO31 EC_MUTE# R308 1 2 10K_0402_5%
KSO[0..15] KSI3 58 KSI2/GPIO32 83
<37> KSO[0..15] KSI3/GPIO33 EC_MUTE#/GPIO4A EC_MUTE# <35> 1 R03 PVT 100K 8.2K 0.25V
KSI4 59 84 USB_ON#
KSI[0..7] KSI5 60 KSI4/GPIO34 USB_EN#/GPIO4B 85 TL_CLK USB_ON# <37,39>
<37> KSI[0..7] KSI6 61 KSI5/GPIO35 CAP_INT#/GPIO4C 86 TL_DATA TL_CLK <26>
KSI6/GPIO36 PS2 Interface EAPD/GPIO4D TL_DATA <26> 2 R02 DVT 100K 18K 0.5V
KSI7 62 87 TP_CLK
KSO0 39 KSI7/GPIO37 TP_CLK/GPIO4E 88 TP_DATA TP_CLK <37>
40 KSO0/GPIO20 TP_DATA/GPIO4F TP_DATA <37>
KSO1 3 R01 EVT 100K 33K 0.82V
KSO2 41 KSO1/GPIO21
KSO3 42 KSO2/GPIO22 97 EC_TS_ON#
KSO4 43 KSO3/GPIO23 CPU1.5V_S3_GATE/GPXIOA00 98 EC_TS_ON# <39>
2 KSO5 44 KSO4/GPIO24 WOL_EN/GPXIOA01 99 4/11 SVT: Del VLDT_EN 2
KSO6 45 KSO5/GPIO25 Int. K/B HDA_SDO/GPXIOA02 109
KSO7 46 KSO6/GPIO26 Matrix VCIN0_PH/GPXIOD00 NTC_V <42> 2/1 SIV: add PU resistor for LID_SW#
KSO7/GPIO27 SPI Device Interface
KSO8 47
KSO9 48 KSO8/GPIO28 119 FRD#SPI_SO
KSO10 49 KSO9/GPIO29 SPIDI/GPIO5B 120 FWR#SPI_SI FRD#SPI_SO <12> CO_LAY NUVOTON EC
KSO10/GPIO2A SPIDO/GPIO5C FWR#SPI_SI <12>
KSO11
KSO12
50
51 KSO11/GPIO2B SPI Flash ROM SPICLK/GPIO58
126
128
SPI_CLK
FSEL#SPICS#
SPI_CLK <12> Share FCH ROM +3VALW
KSO13 52 KSO12/GPIO2C SPICS#/GPIO5A FSEL#SPICS# <12>

R321
KSO14 53 KSO13/GPIO2D LID_SW# 2 1
KSO15 54 KSO14/GPIO2E 73 100K_0402_5%
KSO16 81 KSO15/GPIO2F ENBKL/GPIO40 74 APU_IMON <48>
<37> KSO16 KSO17 82 KSO16/GPIO48 PECI_KB930/GPIO41 89 VGATE <48>
<37> KSO17 KSO17/GPIO49 FSTCHG/GPIO50 90 LAN_PWR_ON# <31>
BATT_CHG_LED#/GPIO52 91 CAPS_LED# BATT_CHG_LED# <37>
EC_SMB_CK1 77 CAPS_LED#/GPIO53 92 CAPS_LED# <37>
<42,43> EC_SMB_CK1 EC_SMB_CK1/GPIO44 GPIO PWR_LED#/GPIO54 PWR_LED# <37>
EC_SMB_DA1 78 93
<42,43> EC_SMB_DA1 EC_SMB_CK2_SUS 79 EC_SMB_DA1/GPIO45 BATT_LOW_LED#/GPIO55 95 SYSON BATT_LOW_LED# <37>
<7> EC_SMB_CK2_SUS SM
EC_SMB_CK2/GPIO46 Bus SYSON/GPIO56 SYSON <40,45>
+3VS EC_SMB_DA2_SUS 80 121
<7> EC_SMB_DA2_SUS EC_SMB_DA2/GPIO47 VR_ON/GPIO57 127 VR_ON <48>
PM_SLP_S4#/GPIO59 R24 1 885N@2 10K_0402_5%
1
6 100
<13> PM_SLP_S3# 14 PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXIOA03 101 EC_RSMRST# <13>
885N@ R314 EC_LID_OUT#
<13> PM_SLP_S5# EC_SMI# 15 PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXIOA04 102 EC_LID_OUT# <13>
10K_0402_5%
<13> EC_SMI# 16 EC_SMI#/GPIO08 PROCHOT_IN/GPXIOA05 103 Turbo_V <42>
H_PROCHOT#_EC R372 2 885N@1 0_0402_5%
<27> CMOS_ON# PROCHOT <42>
2
EC_FAN_PWM 17 GPIO0A H_PROCHOT#_EC/GPXIOA06 104 MAINPWON_R R381 2 885N@1 0_0402_5%

18 GPIO0B VCOUT0_PH/GPXIOA07 105 BKOFF# MAINPWON <44>
<50> EC_VGA_EN GPIO0C GPO BKOFF#/GPXIOA08 BKOFF# <27>
19 GPIO 106 PBTN_OUT#
<34> ODD_DA# 25 GPIO0D PBTN_OUT#/GPXIOA09 107 PBTN_OUT# <13>
<41> ADP_ID_CLOSE 28 EC_INVT_PWM/GPIO11 PCH_APWROK/GPXIOA10 108 VGA_GATE# PXS_PWREN <13,18,45,51,52>
<33> EC_TACH EC_PME# 29 FAN_SPEED1/GPIO14 SA_PGOOD/GPXIOA11 VGA_GATE# <13>
3 EC_TX 30 EC_PME#/GPIO15 3
<30,37> EC_TX EC_RX 31 EC_TX/GPIO16 110 ACIN
<30,37> EC_RX 32 EC_RX/GPIO17 AC_IN/GPXIOD01 112 EC_ON ACIN <17,43>
<13,48> FCH_PWRGD 34 PCH_PWROK/GPIO18 EC_ON/GPXIOD02 114 EC_ON <44>
<37> NOVO# 36 SUSP_LED#/GPIO19
GPI
ON/OFF/GPXIOD03 115 LID_SW#
ON/OFF <37> NUVOTON EC need PD
<37> NUM_LED# NUM_LED#/GPIO1A LID_SW#/GPXIOD04 LID_SW# <37>
+3VALW SUSP#/GPXIOD05
116
117
SUSP#
SUSP# <40,45,47,52> in AMD platform, no use. SUSP#
NUVOTON EC use 1
R379 GPXIOD06 118 885N@
PECI_KB9012/GPXIOD07
1
AGND/AGND
1 885N@ 2 0_0402_5% XCLKI 122 C435

123 XCLKI/GPIO5D 124 +V18R R373 1000P_0402_50V7K
GND/GND
GND/GND
GND/GND
GND/GND
+3VS <11,15> RTC_CLK XCLKO/GPIO5E V18R 2

RP24 1 0_0402_5%
GND0
8 1 EC_SMB_DA1 R318 1 2 0_0402_5% XCLKO 885N@

7 2 EC_SMB_CK1 C436
2
6 3 EC_SMB_CK2 SHORT PAD@ 4.7U_0603_6.3V6K
2
5 4 EC_SMB_DA2 2
11
24
35
94
113
69
R320 C437
2.2K_0804_8P4R_5% 100K_0402_5% 20P_0402_50V8
2
KB9012QF-A2_LQFP128_14X14
ECAGND
1
POP for susclk implemented

+3VALW 20100810
R329 R330
4.7K_0402_5% 4.7K_0402_5%
+3VS
H_PROCHOT# <48,7>
EC_SMB_CK2_SUS
1
EC_SMB_DA2_SUS D
4 H_PROCHOT#_EC 2 4
2
G SHORT PAD@
Q142 S 1 2 0_0402_5% EC_PME#
3
EC_SMB_DA2_SUS 6 1 EC_SMB_DA2 2N7002K_SOT23-3 <31> LAN_WAKE# R324

EC_SMB_DA2 <17,33>
DMN66D0LDW-7 2N_SOT363-6
Q143A
5
EC_SMB_CK2_SUS 3 4 EC_SMB_CK2
EC_SMB_CK2 <17,33> Issued Date 2012/11/13 Deciphered Date 2013/11/12 Title
DMN66D0LDW-7 2N_SOT363-6
BIOS & EC I/O Port
Q143B Size Document Number Rev
Custom 0.1
VALGD MB L
A B C D E
KSI[0..7]
For EC Debug PWR Button Key Board Conn. KSO[0..17]
KSI[0..7]
KSO[0..17]
<36>
<36>
+3VALW
For 15" For 14"
2
+3VLP
R642 JKB2
100K_0402_5% JKB1 KSI1 1
1
2
KSI1 1 KSI7 2
KSI7 2 1 KSI6 3 2
1
R701 D26 KSI6 3 2 KSO9 4 3
100K_0402_5% NOVO# 2 KSO9 4 3 KSI4 5 4
<36> NOVO# 1 5 4 6 5
NOVO_BTN# KSI4 KSI5
1
JP3 ON/OFF 3 KSI5 6 5 KSO0 7 6
1 KSO0 7 6 KSI2 8 7
+3VALW 1 7 8
2 KSI2 8 KSI3 9
<30,36> EC_TX 2 J11 DAN202UT106_SC70-3 8 9
3 KSI3 9 KSO5 10
<30,36> EC_RX 4 3 1 2 10 9 11 10
DEBUG@ ON/OFF KSO5 KSO1
4 ON/OFF <36> 10 11
KSO1 11 KSI0 12
ACES_85205-0400 SHORT PADS KSI0 12 11 KSO2 13 12
ME@
TOP +3VS KSO2 13 12 KSO4 14 13
KSO4 14 13 KSO7 15 14
J13 15 14 16 15
KSO7 KSO8
1 2 DEBUG@ KSO8 16 15 KSO6 17 16
KSO6 17 16 KSO3 18 17
17 18
1
SHORT PADS KSO3 18 KSO12 19
BOT R745 R744 KSO12 19 18 KSO13 20 19
KSO13 20 19 KSO14 21 20
300_0402_5% 300_0402_5% 20 21
KSO14 21 KSO11 22
KSO11 22 21 KSO10 23 22
2
KSO10 23 22 KSO16 R747 1 15@ 2 0_0402_5% KSO15 24 23
KSO15 24 23 KB_LED_PWR R746 1 14@ 2 0_0402_5% KB1 25 24
KB1 25 24 KSO17 R748 1 15@ 2 0_0402_5% KB2 26 25
KB2 26 25 CAPS_LED# R749 1 14@ 2 0_0402_5% 26 27
KB_LED_PWR 27 26 GND2 28
28 27 GND1
<36> CAPS_LED# 28
KB_LED_PWR_2 29 31
30 29 GND 32 ACES_88514-02601-071
<36> NUM_LED# 30 GND ME@
ACES_88514-3001
ME@
SP010011A00
IO/B Conn.
Ext. USB2.0 1/21 SIT change PN to SM070001N00 for action plan
1/29 SIT: Del R806 & Q12 for change audio type
from normal close to normal open.
Card Reader
+3VS
JIO1
USB Right side 14 16
L66 USB20_N6 13 14 G2 15
4 3 <13> USB20_N6 12 13 G1
USB20_N0 USB20_N0_R USB20_P6
<13> USB20_N0 4 3 +USB_VCCB <13> USB20_P6 12
W=80mils 11
EMI@ USB20_N0_R 10 11
USB20_P0 1 2 USB20_P0_R USB20_P0_R 9 10
<13> USB20_P0 1 2 9
+USB_VCCB 8
+5VALW +USB_VCCB WCM-2012-900T_4P 7 8
1 7
C714 1 SIV: EMI request Audio Jack 6
6
2
U36 + C492 HPOUT_L 5
SM070001N00 <35> HPOUT_L 5
1 8 220U_6.3V_M EMI@ HPOUT_R 4
GND VOUT <35> HPOUT_R 4
2 7 330p_0402_25V HGNDA 3
3 VIN VOUT 6 2 2 <35> HGNDA 2 3
HGNDB
VIN VOUT <35> HGNDB 2
4 5 SE074331K80 PLUG_IN 1
<36,39> USB_ON# EN FLG USB_OC1# <13> 6.3Φ * 5.9 <35> PLUG_IN 1
G547I2P81U_MSOP8 SF000001500 ACES_85202-1405N
1/29 SIT:change to PLUG_IN ME@
D25 @ESD@
1
PJDLC05_SOT23-3
ESD
TP Switch & TP Conn. LED PWR/B Conn.

+5VS LED1 14@
JPWRB1
<36> PWR_LED# PWR_LED# 1 2 2 R623 1 +5VALW 1
300_0402_5% 2 1
NOVO_BTN# 3 2
14@ 3
JTP1 19-213A-T1D-CP2Q2HY-3T_WHITE ON/OFF 4
8 5 4
7 GND LED2 14@ 6 5
GND 6
2
6 BATT_LOW_LED# 1 2 2 R764 1 ESD@ 7
6 <36> BATT_LOW_LED# +3VALW GND
TP_CLK 5 470_0402_5% 8
<36> TP_CLK 4 5 GND
TP_DATA 14@ D24
<36> TP_DATA 4
TP_3 3 19-217-S2C-FM2P1VY-3T_ORANGE ME@
TP_2 2 3 PJSOT24C 3P C/A SOT-23 ACES_88058-060N
1
TP_1 1 2 LED5 14@
1 SP010010T00
ACES_88058-060N BATT_CHG_LED# 1 2 2 R765 1 SCA00001G00
<36> BATT_CHG_LED# +5VALW
300_0402_5%
C490
C491
ME@
0.1U_0402_10V6K
0.1U_0402_10V6K
1 1 SP010010T00 14@ SIT for ESD Request

15@ 19-213A-T1D-CP2Q2HY-3T_WHITE
2 R627 1 TP_3
0_0402_5% @ @
2 R619 1 14@ TP_1

0_0402_5%
2 2
Lid SW(For 14") +3VALW
L R LED/B Conn.
2
1
VDD
SW4 14@ SW5 14@ JLED1 14@
SMT1-05_4P SMT1-05_4P
15" 14" 1 C551
+3VALW 1
5
6
5
6
LID_SW# 2 LID_SW# 3 0.1U_0402_16V4Z

4 2 4 2 3 2 <36> LID_SW# OUTPUT 2
TP_3 TP_2
1 VCC 1 VCC PWR_LED# 4 3
GND
3 1 3 1 BATT_LOW_LED# 5 4
5 2
BATT_CHG_LED# 6 C550
2 CLK 2 CLK 6 14@
1
7 10P_0402_50V8J
8 GND 1
3 DAT 3 DAT GND
ACES_88058-060N
ME@ 14@ U40
SW6 15@ SW7 15@
4 GND 4 L AH1806-W-7 SC59 3P
SMT1-05_4P SMT1-05_4P
SP010010T00
For 15"
5
6
5
6
4 2 4 2
5 L 5 R
TP_2 TP_1
3 1 3 1
GND
6 R 6 2012/11/13 2013/11/12 Title
Issued Date Deciphered Date ROM/KBD/PWR/CR/LED/TP Conn.
C 0.1
VALGD MB L
A B C D E
For UMA
U71 GCLK238@
Every power trace need:

P/N:SA00005DO00 W=20mils
1 1
SLG3NB244VTR_TQFN16_2X3
For GreenCLK generate CLK:
+CHGRTC_R Mount: All parts in this page except
Swing Level RES (Marked "*")
1
+3VLP
SIT:Add CG5, CG6 & CG7 for Vender Request RG12
390_0402_5% NA: PD108,
GCLK@
Y1,R98,C180,C181,
2
+3VALW +3V_LAN +1.8VGS +3VALW
0.1U_0402_16V7K
1
CG3 GCLK@
Y2,R169,C196,C197,
Y6,C968,C969
0_0402_1%
RG8 0_0402_1%
22U_0805_6.3V6M
+GCLK_VBAT
1
SHORT PAD@
SHORT PAD@
1 1
1
2
GCLK@
RG11 CG2
1
For DIS
0.1U_0402_16V7K
0_0402_1% CG4
SHORT PAD@ 2.2U_0402_6.3V6M
2 U74 2 GCLK@
2
2
2
CG5
RG9
2
10 14 Typical CLK_32K_FCH trace <= 6"
2
VBAT VDD_RTC_OUT
For EMI Max. length <= 24" 2
0.1U_0402_16V7K
0.1U_0402_16V7K
15
+V3.3A
1 1
CG7 @
CG6 @
2 1 +3VS_GCLK 2 SHORT PAD@

CG1 VDD 9 GCLK_32K_R RG11 2 0_0402_1% GCLK_32K
2 2
0.1U_0402_16V7K 32kHz GCLK_32K <11> FCH_32.768K
VGA_GCLK 11
VDDIO_27M 27MHz
12 GCLK_27MHZ_R RG21 GCLK@ 210_0402_5% GCLK_27MHZ
GCLK_27MHZ <18> dGPU
<31> LAN
8 6 GCLK_LAN_25MHZ_R RG31 GCLK@ 233_0402_5%GCLK_LAN_25MHZ
VDDIO_25M_A 25MHz_A GCLK_LAN_25MHZ
<11> FCH_25M
PCH_GCLK 3 5 GCLK_PCH_25MHZ_R RG41 GCLK@ 233_0402_5%GCLK_PCH_25MHZ
VDDIO_25M_B 25MHz_B GCLK_PCH_25MHZ
GREENCLK_XTALI 1
Y8 GREENCLK_XTALO 16 XTAL_IN
XTAL_OUT
Close to GCLK
GND1
GND2
GND3
GND4
4 3 Typical CLK_25M_FCH trace <= 8"
NC OSC
1 2 Typical CLK_25M_LAN trace <= 8"
OSC NC
SLG3NB304VTR_TQFN16_2X3 Max. length <= 12"
4
7
13
17
GCLK@
GCLK@ CG8
1
25MHZ_10PF_7V25000014
1
GCLK302@ P/N:SA00006D500
15P_0402_50V8J CG9
12P_0402_50V8J
2 2 GCLK@
3 3
12pF for Vender Request

Reserved for Swing Level adjustment
( Close GCLK side )
GCLK_27MHZ RG5 1 2 0_0402_5% NOGCLK@
GCLK_LAN_25MHZ RG6 1 2 0_0402_5% NOGCLK@
GCLK_PCH_25MHZ RG7 1 2 0_0402_5% NOGCLK@
4 4

GCLK
B 0.1
VALGD MB L
A B C D E
5 4 3 2 1
Touch Screen
+3VS +3VS_TS
1 TS@ 2
R799 0_0402_5%
JTS1
D +3VS_TS 1 D
3 1 2 1
D
3 2
<13> USB20_N4 3
4
<13> USB20_P4 4
R798 TS@ Q156 5
G
2
100K_0402_5% PMV65XP_SOT23-3 EC_TS_ON# R726 1 TS@ 2 0_0402_5% TS_RST# 6 5
6
0.1U_0402_16V7K
1 2 @ 7
<36> EC_TS_ON# GND
1 2 8
GND
C669 TS@ C668 ACES_50208-00601-P01
0.1U_0402_16V7K TS@ ME@
2 1
USB3.0
2A/Active Low ESD
+5VALW +USB3_VCCA
D22 D31
@ @ESD@ D27 @ESD@ D30 @ESD@ @ESD@
C704 U35 W=80mils U3RXDN0 9 10 1 1U3RXDN0 U3RXDN1 9 10 1 1 U3RXDN1 U2DN10 3 6 U2DP11 3 6
.1U_0402_16V7K 1 8 I/O2 I/O4 I/O2 I/O4
GND VOUT 7
1 2 2 U3RXDP0 8 9 2 2U3RXDP0 U3RXDP1 8 9 2 2 U3RXDP1
3 VIN VOUT 6
VIN VOUT 5
<36,37> USB_ON#
4
USB_OC0# <13>
U3TXDN0 7 7 4 4U3TXDN0 U3TXDN1 7 7 4 4 U3TXDN1 2 5 +5VALW 2 5 +5VALW
EN FLG GND VDD GND VDD
C C
G547I2P81U_MSOP8 U3TXDP0 6 6 5 5U3TXDP0 U3TXDP1 6 6 5 5 U3TXDP1
3 3 3 3 1 4 U2DP10 1 4 U2DN11
I/O1 I/O3 I/O1 I/O3
1 1
@ C735 8 8
+ AZC099-04S.R7G_SOT23-6 AZC099-04S.R7G_SOT23-6
C737 470P_0402_50V7K
220U_6.3V_M 2 YSCLAMP0524P_SLP2510P8-10-9 YSCLAMP0524P_SLP2510P8-10-9
SF000002Y00 2
FCH_USB2.0 FCH_USB2.0
1/21 SIT change PN to SM070001N00 for action plan
B
1/21 SIT change PN to SM070001N00 for action plan B
WCM-2012-900T_4P WCM-2012-900T_4P
1 2 U2DN10 1 2 U2DN11
<13> USB20_N10 1 2 <13> USB20_N11 1 2
EMI@ EMI@
4 3 U2DP10 4 3 U2DP11
<13> USB20_P10 4 3 <13> USB20_P11 4 3
L51 L55
SM070001N00 SM070001N00
Left Ext.USB Conn. 1

FCH_USB3.0 Left Ext.USB Conn. 2
FCH_USB3.0 WCM-2012-900T_4P +USB3_VCCA WCM-2012-900T_4P
1 2 U3RXDN0 1 2 U3RXDN1 +USB3_VCCA
<13> USB3_RX0_N 1 2 <13> USB3_RX1_N 1 2
EMI@
W=80mils EMI@
4 3 U3RXDP0 JUSB1 4 3 U3RXDP1
W=80mils
<13> USB3_RX0_P 4 3 <13> USB3_RX1_P 4 3
U3TXDP0 9 JUSB2
L54 SM070003K00 1 SSTX+ L50 SM070003K00 U3TXDP1 9
U3TXDN0 8 VBUS 1 SSTX+
U2DP10 3 SSTX- U3TXDN1 8 VBUS
7 D+ U2DP11 3 SSTX-
U2DN10 2 GND_D 10 7 D+
U3RXDP0 6 D- GND1 11 U2DN11 2 GND_D 10
C850 4 SSRX+ GND2 12 C849 U3RXDP1 6 D- GND1 11
.1U_0402_16V7K WCM-2012-900T_4P U3RXDN0 5 GND GND3 13 .1U_0402_16V7K WCM-2012-900T_4P 4 SSRX+ GND2 12
1 2 U3TXDN0_L 1 2 U3TXDN0 SSRX- GND4 1 2 U3TXDN1_L 1 2 U3TXDN1 U3RXDN1 5 GND GND3 13
<13> USB3_TX0_N 1 2 <13> USB3_TX1_N 1 2 SSRX- GND4
OCTEK_USB-09EAAB
EMI@ ME@ EMI@ OCTEK_USB-09EAAB
1 2 U3TXDP0_L 4 3 U3TXDP0 1 2 U3TXDP1_L 4 3 U3TXDP1 ME@
<13> USB3_TX0_P 4 3 <13> USB3_TX1_P 4 3
C848 L53 SM070003K00 C847 L49 SM070003K00
.1U_0402_16V7K .1U_0402_16V7K 1/21 SIT change PN from SM070001S00 to SM070003K00 for action plan
1/21 SIT change PN from SM070001S00 to SM070003K00 for action plan
A A
Place TX AC coupling Cap (C843~C850). Close to connector

2012/11/13 2013/11/12 Title
Issued Date Deciphered Date
USB3.0/Left USB Ports
Custom 0.1
VALGD MB L
5 4 3 2 1
A B C D E
+5VALW to +5VS combine with +3VALW to +3VS
Ĭ
Ĳį
Ĳŗ
ł
ō
Ř
ġŕ
Ő
ġĬ
Ĳį
Ĳŗ
Ŕ
ġĩ
Ķį
ĲĶ
ł
Ī
+1.1VALW U41 +1.1VS
+5VALW Each 250pF on CAP_MOS1 (2) will make +5VS DMN3030LSS-13_SOP8L-8
Slew Rate(uS/V) increase of 100uS/V 8 1
U54 1 7 2 1 1
1
1 14 6 3
2 VIN1 VOUT1 13 C1448 5 C1447 C1449
1 VIN1 VOUT1 1
10U_0603_6.3V6M 10U_0603_6.3V6M 1U_0603_10V6K R1101
SUSP# 3 12 1 2 2 2 2 470_0603_5%
4
ON1 CT1
10U_0603_6.3V6M
CC41
C466 100P_0402_50V8J 1 @
2
4 11
VBIAS GND
6
SUSP# 5 10 1 2 +VSB
ON2 CT2 C540 680P_0402_50V7K +3VS 2
+3VALW 6 9 Q157A
VIN2 VOUT2
1
7 8 2 SUSP
VIN2 VOUT2 R1105
10U_0603_6.3V6M
CC39
15 1 270K_0402_5%
1
GPAD DMN66D0LDW-7_SOT363-6
TPS22966DPUR_SON14_2X3
2
1.1VS_GATE 1 R1106 2 1.1VS_GATE_R
2
1 1
3
82K_0402_5% @
Q157B C1034 C1451
0.1U_0402_25V6 0.1U_0603_25V7K
SUSP 5 2 2
DMN66D0LDW-7_SOT363-6
4
+1.5V to +1.5VS
+1.5V Q20 +1.5VS
2 2
3 1
1 1 1
1
@
C440 LP2301ALT1G_SOT23-3 C441 C442
10U_0603_6.3V6M 10U_0603_6.3V6M 1U_0603_10V6K R1454
2
2 2 2 470_0603_5%
@
2
1
+5VALW D
2 SUSP
G
1
S Q23
3
2N7002K_SOT23-3
100K_0402_5% @
R336 +1.5V
R339 +0.75VS
2
1.5VS_GATE 1 2 1.5VS_GATE_R
2
22K_0402_5% 1 1
1
2
D @ R1139
SUSP# 2 Q26 C451 C452 R1137 @ 470_0603_5%
G 2N7002K_SOT23-3 0.1U_0402_25V6 0.1U_0603_25V7K @ 470_0603_5%
S 2 2
3
6 1
31
3 @ 3
@ 5 SUSP 2 SYSON#
Q159B
DMN66D0LDW-7_SOT363-6 Q159A
1
+5VALW DMN66D0LDW-7_SOT363-6
+RTCBATT +5VALW
1
1
@
@ R1453
R1108 R1452 100K_0402_5%
100K_0402_5% 100K_0402_5%
2
SYSON#
2
SUSP SUSP
1
Q52
OUT
1
DTC124EKAT146_SC59-3
Q29
OUT
SYSON 2 DTC124EKAT146_SC59-3
<36,45> SYSON IN @
GND
2
<36,45,47,52> SUSP# IN
GND
3
3
4 4

DC Interface
Custom 0.1
VALGD MB L
A B C D E
5 4 3 2 1
ADP_ID
AC Adapter 90W 65W
R(K ohm) open 10
ADP_ID(V) 3.3 1.65
Detection voltage >2.64 1.32~1.98
D D
VIN
PL101
PF101 1 2
7A_24VDC_429007.WRML
JDCIN1 HCB2012KF-121T50 0805
1 APDIN 1 2 APDIN1
1 2
2 3 PL102
3
@1000P_0402_50V7K
1000P_0402_50V7K
@100P_0402_50V8J
100P_0402_50V8J
4 1 2
4 5
5 HCB2012KF-121T50 0805
1
PC101
PC102
PC103
PC104
ACES_50299-00501-003
CONN@
2
1
PR112
0_0402_5%
2
PQ102A
C PR102 2N7002KDW-2N_SOT363-6 C
1 2 6 1
+3VALW ADP_ID <36>
750_0402_1%
680P_0603_50V7K
0.1U_0402_16V7K
2
PR110
1
1
PC108
PC109
1 2
VIN
2
100K_0402_1%
3
2
2N7002KDW-2N_SOT363-6
PQ102B
PR111
100K_0402_1% 5
ADP_ID_CLOSE <36>
1
+CHGRTC
B PR103 B
1K_0603_5%
1 2
PD101
+3VLP
S SCH DIO BAS40CW SOT-323
2 +CHGRTC_R
+RTCBATT 1
3 PR101
1K_0603_5% JRTC1 @ JRTC2 @
1 2 1 1
2 1 2 1
3 2 3 2
4 GND 4 GND
GND GND
RTC Battery ACES_50271-0020N-001 ACES_50271-0020N-001
A A

PWR DCIN / RTC Battery
Custom 0.1
VALGD MB L
5 4 3 2 1
5 4 3 2 1
PL201
VMB2 VMB 1 2
CONN@ PF201
JBAT1 12A_65V_451012MRL HCB2012KF-121T50 0805
SUYIN_200082GR007M229ZR
1 1 2
1 2 BATT+
PL202
2 3 EC_SMCA 1 2
3 4 EC_SMDA
4 5 HCB2012KF-121T50 0805
5 6
6
1
7
7
1
100_0402_1%
100_0402_1%
D 8 D
GND 9 PC201 PC203
GND 1000P_0402_50V7K @0.01U_0402_25V7K
2
PR201
PR204
2
2
EC_SMB_CK1 <36,43>
EC_SMB_DA1 <36,43> 90W(DIS) : 6.65K 100W active 90W recovery

PH201 under CPU botten side :
1 2 65W(UMA): 1.65K 70W active 65W recovery
PR206
+3VLP CPU thermal protection at 93 +-3 degree C
6.49K_0402_1%
CONN@ Recovery at 56 +-3 degree C
JBAT2 1 2
SUYIN_200082GR007M229ZR
BATT_TEMP <36,42>
PR207
1 10K_0402_5%
1 2 A/D
2 3
3 4
4 5
5 6
6 7
7 8
GND 9
GND
+3VALW <36,43> ADP_I
<36> PROCHOT +3VLP
2
C
8.45K_0402_1%
C
VL
1
@100K_0402_1%
12.7K_0402_1%
PR221
PR229
PR226
2
1
VL PR214
2
<36> Turbo_V
2
PC202 PR211 100K_0402_1%
1
9.31K_0402_1%
5.9K_0402_1%
6 1
1
2
<36> NTC_V
25.5K_0402_1%
0.01U_0402_25V7K 100K_0402_1%
BATT_OUT <43>
PR227
PR228
PR202 PR210
2
1
2
1
PR225
75K_0402_1% 47K_0402_1%
PQ202A PH201
2
OR 2 2N7002KDW-2N_SOT363-6 100K_0402_1%_TSM0B104F4251RZ
2
1
3
2N7002KW_SOT323-3
2N7002KDW-2N_SOT363-6
2N7002KDW-2N_SOT363-6
PC208 PR222
1
2
8
<36,42> BATT_TEMP
PQ207
0.068U_0402_16V7K~N 100K_0402_1%
3
3 PQ202B
P
1
+
1
1 1 2 5 2N7002KDW-2N_SOT363-6 D
2 O 2
1N4148WS-7-F_SOD323-2
-
G
PQ206A
PQ206B
PU201A 4 2 5 G
2
AS393MTR-E1 SO 8P OP <36> ADP_65 S

4
3
2
PD201
4
PR213 PR205 OR
1
100K_0402_1%
PC207 1.5M_0402_5%
1
D
100P_0402_50V8J
1
2 PQ208 +3VLP ECAGND

G @2N7002KW_SOT323-3 ECAGND ECAGND ECAGND
S
3
2
<36> ADP_90
PR220 <36> ADP_135
B B
100K_0402_1%
VMB +3V_LDO VL
1
1
D
2 PQ205
<36> BATT_LEN#
G 2N7002KW_SOT323-3
@75K_0402_1%
3 S
2
1
@ PR208
@ PR218
@47K_0402_1%
8
1
5
P
+ 7 1 2 +5VALW
O
@22U_0603_6.3V6M
6
-
G
@1N4148WS-7-F_SOD323-2
@ PC210 @ PU202
2
1
@100K_0402_1%
@100P_0402_50V8J
@ PC212
@0.068U_0402_16V7K~N 1 5 PJ202
+3V_LDO
4
IN OUT
1
PU201B @ JUMP_43X39
@ PR217
PD203
AS393MTR-E1 SO 8P OP 2 1 2
B+ +VSB
2
GND 1 2
2
@ PC213
@
2
@ PR223 3 4 PC209
1
@1.5M_0402_5% @ SHDN# BYP

@4.7U_0402_6.3V6M
1
@G9191-330T1U_SOT23-5
1
@ PC211
2
@1U_0402_16V6K
A A

PWR-BATTERY CONN/OTP
Custom 0.1
VALGD MB L
5 4 3 2 1
5 4 3 2 1
P3
B+
P2
PQ301 PQ302
AO4407AL_SO8 SI4483ADY
8 1 1 8 PR301
VIN 7 2 2 7 0.01_1206_1% CHG_B+
6 3 3 6
5 5 1 4 1 2 PQ312
PL301 AO4407AL_SO8
2 3 1UH_PCMB042T-1R0MS_4.5A_20% 1 8
4
2 7
3 6
@2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
PQ304 5
D D
47K_0402_5%
PC315
PC316
1
PC319
200K_0402_1%
0.1U_0603_25V7K
4
1
PR302
DTA144EUA_SC70-3 DISCHG_G
PC302
PR304
2
1 2 PR322
200K_0402_1%
2
2
2 PC301 1 2
2
5600P_0402_25V7K ACN VIN
2ACOFF-1
1SS355_SOD323-2
2
1
ACP PR321
1DISCHG_G-1
47K_0402_1%
1
1
PD302
P2-1
0.1U_0402_25V6
1
2 200K_0402_1%
PQ303 PQ311 PR325
1
PC307 PC311 DTC115EUA_SC70-3
2
DTC115EUA_SC70-3
PR306 1 2 1 2
3
20K_0402_1%
1 2 2 1 2 PACIN_1
6
PQ306 0.1U_0402_25V6
1
D 2N7002KW _SOT323-3 PC308 PD303 PQ313

150K_0402_1%
2
PR305
PQ307A 1SS355_SOD323-2
2 BATT_OUT <42,43>
2N7002KDW -2N_SOT363-6 G 0.1U_0402_25V6 P2 2N7002KW _SOT323-3
1
D
0.1U_0402_25V6
S
3
1 2 2 PACIN
1
1
PC324
VIN G
S
3
ACPRN
392K_0402_1%
2
1
P2-2
5
C C
PR309
2N7002KDW-2N_SOT363-6
10_1206_5%
PQ309
PR319
3
PQ307B
ACOK
CMPIN
CMPOUT
ACP
ACN
PR303 PR308
2
47K_0402_1% 64.9K_0402_1% 21
2
PACIN 1 2 5 1 2 6 TP 1 2DH_CHG_14
<36,42> ADP_I ACDET PC314
PC303 20 BQ24737VCC 1 2 PR326
4
1 2 1 2 7 VCC 0_0402_5%
PR311 IOUT AON7408L_DFN8-5 PR324
3
2
1
1U_0603_25V6K
1
10K_0402_1% 0.1U_0402_25V6 PC304 100P_0402_50V8J 19 PL302 0.01_1206_1%

PHASE
<36> ACOFF
1 2ACOFF-1
<36,42> EC_SMB_DA1
8
SDA
PU301 4.7U 20% VMPI0703AR-4R7M-Z01 5.5A
1 2 CHG 1 4
BATT+
BQ24727RGRR_VQFN20_3P5X3P5 LX_CHG
18 DH_CHG
HIDRV
5
2 9 2 3
SCL
1
<36,42> EC_SMB_CK1 PR315 PR320 PC317
@4.7_1206_5%
MDV1527URH
PR323
PQ305 316K_0402_1% 2.2_0603_5% 0.047U_0603_16V7K
1 2 10 17 BST_CHG 1 2 1 2 SRP SRN
10U_0805_25V6K
10U_0805_25V6K
124737_SN
ILIM BTST
1
DTC115EUA_SC70-3 +3VALW PD301

3
PR316 4 @
LODRV
1
PQ310
16 2 1
PC322
PC323
100K_0402_1%
GND
SRN
SRP
REGN
BM
2
2
RB751V-40_SOD323-2
@680P_0603_50V7K
11
12
13
14
15
3
2
1
1
1
D
PC320
2
2 PC312
6.8_0402_5%
1 BQ24737VDD
10_0402_5%
G 1U_0603_25V6K
2
PR317
PR318
<42,43> BATT_OUT S PQ314 @
3
2N7002KW _SOT323-3
PC306 DL_CHG
2
2
B 0.1U_0402_25V6 B
1 2
1
PC305 1 PC309
0.1U_0402_25V6 0.1U_0402_25V6
2
BQ24737VDD
PR314
10K_0402_1%
1
1 2
ACIN <17,36>
PR310
PR307 10K_0402_1%
47K_0402_1%
PACIN
2
1 2
PR312
ACPRN 2
12K_0402_1%
2
PQ308
A DTC115EUA_SC70-3 A
3

CHARGER
0.1
VALGD MB L
5 4 3 2 1
A B C D E
03/06
PR412
3V5V_EN_R 1 2 3V5V_EN
10K_0402_5%
2
PC432
0.047U_0402_25V7K
1
PR402
1 PD401 1
499K_0402_1%
ENLDO_3V5V 2 1 2 1
B+
1
150K_0402_1%
@1U_0603_25V6K
GLZ5.1B_LL34
1
PR403
PC407
2
2
B+
PU401 03/06
PL401 7 1 3V5V_EN_R
HCB1608KF-121T30_0603 IN EN1 PC439 PR416
2200P_0402_50V7K
10U_0805_25V6K
@0.1U_0402_25V6
1 2 3V_VIN 8 3 FB_3V 1 2 2 1
IN EN2 PR401 PC402
PC403
6 BST_3V
1 2 1
BST_3V_1 2 0.1U_0402_25V6K 1K_0402_5%
BS
1
1
PC404
PC406
1_0603_5% 0.1U_0603_25V7K
@ PL402
2
10 LX_3V 1 2
LX +3VALWP
9 4 1.5UH_PCMC063T-1R5MN_9A_20%
GND OUT
@470P_0402_50V8J
@22U_0805_6.3V6M
470P_0402_50V8J
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
4.7_1206_5%
1
1
PC434
PC435
2 5
PG LDO +3VLP
PC408
PC409
PC410
PC411
PC412
1
PR404
SY8208BQNC_QFN10_3X3
2
PC414
13V_SN
4.7U_0603_6.3V6M
2
PR409
680P_0603_50V7K
1 2
+3VLP 100K_0402_1%
SPOK <46>
PC415
2 2
2
B+ PL403
HCB2012KF-121T50_0805
1 2 5V_VIN
03/06
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
@0.1U_0402_25V6
PU403 PC436 PR413

8 1 3V5V_EN FB_5V 1 2 2 1
IN EN1
1
1
PC420
PC427
PC417
PC418
3 PC421 6800P_0402_25V7K 1K_0402_5%

EN2 0.1U_0603_25V7K
6 1
BST_5V 2 1
BST_5V_1 2
2
@ BS PR405
1_0603_5% +5VALWP
PL404 @PJ401
@ PJ401
9 10 LX_5V 1 2 +3VALWP 1 2 +3VALW
GND LX 1 2
5V_VCC 5 4 1.5UH_PCMC063T-1R5MN_9A_20% JUMP_43X118
VCC OUT
1
@470P_0402_50V8J
@22U_0805_6.3V6M
470P_0402_50V8J
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
4.7_1206_5%
1
PC437
PC438
2 7
PG LDO VL
1
PC422
PR406
PC423
PC424
PC425
PC426
PC416
4.7U_0603_6.3V6M
SY8208CQNC_QFN10_3X3
2
1 5V_SN
@PJ402
@ PJ402
2
2
1
PC430
4.7U_0603_6.3V6M
+5VALWP 1 2 +5VALW
1 2
680P_0603_50V7K
3 3
JUMP_43X118
2
PC429
2
PR407
2.2K_0402_5%
1 2
<36> EC_ON
PR408
1 2
<36> MAINPWON
@0_0402_5%
3V5V_EN
1M_0402_1%
4.7U_0402_6.3V6M
1
1
PR410
PC431
2
2
4 4

3VALWP/5VALWP
Custom 0.1
VALGD MB L
A B C D E
A B C D
PL502
1.5V_B+ 1 2 B+
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
@0.1U_0402_25V6
HCB2012KF-121T50_0805
STATE S3 S5 1.5VP VTT_REFP 0.75VSP
1
PC501
PC520
PC509
PC513
S0 Hi Hi On On On
5
Off
2
@
S3 Lo Hi On On (Hi-Z) +1.5VP
UG_1.5V 4 PQ501
S4/S5 Lo Lo Off Off Off MDV1525URH_PDFN33-8-5
LX_1.5V
3
2
1
1
Note: S3 - sleep ; S5 - power off 1
PR501 PC512 PL501 Vo=1.518V

2.2_0603_5% 0.1U_0603_25V7K 1UH_PCMB104T-1R0MH_18A_20%
BST_1.5V 1 2 BST_1.5V-11 2 1 2
+0.75VSP +1.5VP
10U_0805_25V6K
10U_0805_25V6K
1
1
5
PC504
@
20
19
18
17
16
1
PC505
PU501 PR515
AON6554
@4.7_1206_5%
VTT
BOOT
UGATE
PHASE
VLDOIN
2
21 1
2
PAD
PQ502
220U 2V Y D2 ESR15M
+
PC521
1 15 LG_1.5V 4 SUB_+1.5VP
VTTGND LGATE
1
2 14 @ 2
VTTSNS PGND PR511 PC517
3
2
1
5.62K_0402_1% @680P_0603_50V7K
2
3 13 1 2
GND RT8207MZQW_WQFN20_3X3 CS
4 12
VTTREF VDDP
S
e
t
)
p
o
*
>
3
/
8
n
.
4
/
4
n
!
p
i
n
!
5 11 1 2
+1.5VP VDDQ VDD +5VALW
1
PGOOD
PR514
+1.5VP
1U_0603_10V6K
PC506 5.1_0603_5%
TON
0.033U_0402_16V7K OCP min 20A
FB
S3
S5
2
OVP min 1.65V
1
PC510
PC511
FB_1.5V 6
10
1U_0603_10V6K
S3_1.5V
2
PR502
S5_1.5V
2
0_0402_5% 2
36,40,47,52> SUSP# 1 2
PR505 PR509
0_0402_5% 887K_0402_1%
<36,40> SYSON 1 2 1 2 1.5V_B+
@
PJ504
1
@ PC508 PR507
PC507
1
PC503 @0.1U_0402_16V7K 10.2K_0402_1% 1 2

0.1U_0402_16V6K 1 2 remote_1.5V 1 2 1 2
2
2
@ JUMP_43X118
FB=Vref=0.75V 0.1U_0402_16V6K PJ505
1
PR508 +1.5VP 1 2 +1.5V

100_0402_1% 1 2
PR506 1 2 +1.5V
10K_0402_1% JUMP_43X118
UV4 1.5V
䘬
2
@
PJ506
+0.75VSP 1 2 +0.75VS
1 2
JUMP_43X39
1
@680P_0402_50V7K
PC528
2
3 3
SNUB_1.8V
@4.7_0402_1%
1
PR529
PU502
SY8032ABC_SOT23-6 PL505
2
PJ508 1UH_PCMB042T-1R0MS_4.5A_20%
+3VALW
1
1 2
2 IN_1.8V 4
IN LX
3 LX_1.8V 1 2
+1.8VSP PJ507
JUMP_43X118 @ 5 2 PR525 +1.8VSP 1 2 +1.8VGS
PG GND 1 2
200K_0402_1%
100K_0402_1%
1
PXS_PWREN <13,18,36,51,52>
22P_0402_50V8J
22U_0805_6.3V6M
22U_0805_6.3V6M
6 1 EN_1.8V 1 2 JUMP_43X118 @
FB EN
1
22U_0805_6.3V6M
PR527
1
0.22U_0402_10V6K
PC530
1
PC529
PC527
1M_0402_5%
2
1
PC532
PC531
1.8VSP max current=1.94A

PR530
2
2
FB_1.8V
1
PR526
100K_0402_1%
2
4 4
Security Classification Compal Secret Data

+1.5VP/+1.8VSP
Custom 0.1
VALGD MB L
A B C D
5 4 3 2 1
PL602
HCB2012KF-121T50_0805
+1.1VALWP_B+ 1 2
B+
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
5
6
7
8
D D
@0.1U_0402_25V6
1
1
PC603
PQ601
PC602
PC604
PC605
TPC8065-H_SO8
2
PC606
0.1U_0603_25V7K 4
1 PR602 2 1
BST_+1.1VALWP_1 2
2.2_0603_5%
PU601
1 10 BST_+1.1VALWP
3
2
1
PGOOD VBST
PR601
1 2 TRIP_+1.1VALWP 2 9 UG_+1.1VALWP PL601
TRIP DRVH 1UH_PCMC063T-1R0MN_11A_20%
38.3K_0402_1%
PR603 EN_+1.1VALWP 3 8 SW_+1.1VALWP 1 2
0_0402_5% EN SW +1.1VALWP
1 2 FB_+1.1VALWP 4 7
<44> SPOK VFB V5IN +5VALW
RF_+1.1VALWP 5 6 LG_+1.1VALWP
0.1U_0402_16V7K
220U 6.3V M F62 LESR15M

RF DRVL
5
6
7
8
1
PC601
@680P_0603_50V7K @4.7_1206_5%
1
PR605
11
MDS1521URH
C C
TP +
PQ602
PC608
2 PC607
1
TPS51212DSCR_SON10_3X3 1U_0603_6.3V6M
2
PR606 4 2
470K_0402_1% SUB_+1.1VALWP
1
2
PC610
3
2
1
2
+1.1VALWP PJP601 @ +1.1VALW
1 2
1 2
JUMP_43X118
PR607
5.76K_0402_1%
1 2
B B
1
10K_0402_1%
PR608
2
A A

PWR +1.1VALWP
Custom 0.4
VALGD MB L
5 4 3 2 1
5 4 3 2 1
PL604
HCB2012KF-121T50_0805
+1.2VSP_B+ 1 2
B+
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
@0.1U_0402_25V6
5
1
PC612
PC611
PC613
PC614
D PQ603 D
2
PC615
0.1U_0603_25V7K 4
PR609
1 2BST_+1.2VSP_11 2
2.2_0603_5% AON7408L
PU602
1 10 BST_+1.2VSP
3
2
1
PGOOD VBST
PR610
1 2 TRIP_+1.2VSP 2 9 UG_+1.2VSP PL605
TRIP DRVH 1.5UH +-20% PCMC063T-1R5MN
124K_0402_1%
PR611 EN_+1.2VSP 3 8 SW_+1.2VSP 1 2
300K_0402_1% EN SW
+1.2VSP
1 2 FB_+1.2VSP 4 7
<36,40,45,52> SUSP# VFB V5IN
+5VALW
RF_+1.2VSP 5 6 LG_+1.2VSP
0.1U_0402_16V7K
RF DRVL 1
1
1
PC616
@680P_0603_50V7K @4.7_1206_5%
220U 2V Y D2 ESR15M
1
11 +
PR614
PC618
PR612 2 TP PC617 PQ604
1
TPS51212DSCR_SON10_3X3 1U_0603_6.3V6M
2
@47K_0402_1% 2
2
2
PR613 4
AON7506
470K_0402_1% SUB_+1.2VSP
1
PC620
C
2 C
3
2
1
2
PR615
7.15K_0402_1%
1 2
1
+1.2VSP PJP602 @ +1.2VS

1 2
10K_0402_1% 1 2
PR616 JUMP_43X118
2
B B
PU702
APL5508-25DC-TRL_SOT89-3
PJ703
+3VS
1 2 IN_+2.5VSP 2 3 +2.5VSP
1 2 IN OUT
@ JUMP_43X39
GND
4.7U_0805_6.3V6K
1
1
PC708
PC707 1
1U_0603_10V6K
PJ704
2
2
+2.5VSP 1 2 +2.5VS
1 2
JUMP_43X39@
(0.38A,20mils ,Via NO.=1)
A A

PWR +1.2VSP/2.5VSP
Custom 0.4
VALGD MB L
5 4 3 2 1
Compal Electronics, Inc.

5 4 3 2 1
CPU_B+
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
PCZ1 PRZ1
1
330P_0402_50V7K2K_0402_1% PQG1 PQG3
PCG12
PCZ11
PCZ12
1 2 1 2
S TR MDU1516URH 1N S TR MDU1516URH 1N
2
5
5
PRZ2 PRZ3 PCZ2
2.94K_0402_1% 137K_0402_1% 390P_0402_50V7K
<7> APU_VDDNB_SEN_H
1 2 1 2 1 2 1 2
PRZ4
PRZ5 PCZ3 PCZ4 41.2K_0402_1% 1
UGATE_NB 2UGATE_NB1-1 4 UGATE_NB1-1 4
D D
10_0402_5% 1000P_0402_50V7KPRZ7 100P_0402_50V8J
1 2 1 2 1 2 1 2 PRG1
+APU_CORE_NB 0_0603_5%
301_0402_1%
3
2
1
3
2
1
@ PCZ6
@1000P_0402_50V7K PLG1
1
0.1U_0603_50V7K 2 1 0.22UH +-20% PCMB104T-R22MS 35A

PCZ5 PHASE_NB 1 4
+APU_CORE_NB
2
5
VSUMN_NB 1 2 1 2 2 3
BOOT_NB 1 2BOOT_NB_1 1 2
1
PRZ8 @ PCZ7 @
1
10K_0402_5%_ERTJ0ER103J @100_0402_1% @220P_0402_50V7K PRG2 PCG3
PHZ1 1 2 2.2_0603_5% 0.22U_0603_25V7K PRG3
0.047U_0402_16V7-K
LGATE_NB 4 LGATE_NB 4 4.7_1206_5%
0.1U_0402_25V6
1
PRZ9
11K_0402_1%
1 2
464 +-1% 0402
2
PCZ8
PCZ9
VSUMP_NB1
PRZ10
2.61K_0402_1% PQG2 PQG4

2
3
2
1
3
2
1
1
PRZ11 AON6554 AON6554
2
PCG4
680P_0603_50V7K
2
2
VSUMP_NB
PRG4
3.65K_0402_1%
UGATE_NB
PHASE_NB
ISUMN_NB
LGATE_NB
COMP_NB
BOOT_NB
VSUMP_NB 1 2
1
FB_NB
GND
18.2K_0402_1%
PRZ12 PRG5
PHZ2 1_0402_1% VSUMN_NB1
470K_0402_5%_TSM0B474J4702RE VSUMN_NB 1 2
41
40
39
38
37
36
35
34
33
32
31
2
1 2 PUZ1
TP
ISUMP_NB
ISUMN_NB
VSEN_NB
FB_NB
COMP_NB
PGOOD_NB
LGATE_NB
PHASE_NB
UGATE_NB
BOOT_NB
PRZ14
@27.4K_0402_1%
1 2
PLZ1
PRZ13 NTC_NB 1 30 BOOT2
C 127K_0402_1% NTC_NB BOOT2 HCB2012KF-121T50_0805 C
1 2 IMON_NB 2 29 UGATE2 1 2
IMON_NB UGATE2
CPU_B+ PLZ4
1 2 3 28 PHASE2
<7> APU_SVC SVC PHASE2 +5VS HCB2012KF-121T50_0805
PCZ10 4 27 LGATE2 PRZ18 1 2 B+
<36,7> H_PROCHOT# VR_HOT_L LGATE2
1000P_0402_25V6K 0_0402_5%
2200P_0402_50V7K
5 26 VDDP 1 2
680P_0402_50V7K
1 1
10U_0805_25V6K
10U_0805_25V6K
<7> APU_SVD SVD VDDP
ISL62771HRTZ-T_TQFN40_5X5
1
6 25 APU_VDD 1 2 PCG5 + + PCG6
PCG7
PCG1
PCG2
PCZ14
+1.5VS VDDIO VDD
5
68U 25V M 6.3X5.7
1 2 7 24 LGATE1 PRZ20 68U 25V M 6.3X5.7
<7> APU_SVT
2
SVT LGATE1 1_0603_5% 2 2
1U_0603_16V6K
1U_0603_16V6K
1
1
PCZ13 0_0402_5% PRZ22 ENABLE 8 23 PHASE1
1U_0603_16V6K 1 2 ENABLE PHASE1 PQZ1
PCZ15
PCZ16
<36> VR_ON
9 22 UGATE1 UGATE1 1 2 UGATE1-1 4
2
APU_IMON <36> PWROK UGATE1
10 21 BOOT1 PRZ23
<11,7> APU_PWRGD IMON BOOT1 2.2_0603_5% PLZ2
PGOOD
1 2 S TR MDU1516URH 1N POWERDFN56-8 0.22UH +-20% PCMB104T-R22MS 35A
ISUMN
ISUMP
<13,36> FCH_PWRGD
3
2
1
COMP
ISEN2
ISEN1
PRZ55 @0_0402_5% VSEN PHASE1 PRZ27 1 4

NTC
RTN
1 2 10K_0402_1% +APU_CORE
FB
+3VS ISEN1 1 2 2 3 1 2 ISEN2
1
PRZ25 1
BOOT1 2BOOT1_1
1 2
11
12
13
14
15
16
17
18
19
20
133K_0402_1% PRZ31 PRZ28
1
1 2 PRZ26 PCZ17 @ PRZ29 3.65K_0402_1% PLZ2_2 10K_0402_1%
ISUMN
PRZ32 PRZ30 2.2_0603_5% 0.22U_0603_25V7K @4.7_1206_5% VSUM+ 1 2

COMP
NTC
PCZ18 @27.4K_0402_1% 100K_0402_5% PLZ2_1

ISEN2
ISEN1
2
FB
1000P_0402_25V6K 1 2 LGATE1 4 PRZ33

1_0402_1%
1
PQZ2 VSUM- 1 2
1 2 PCZ20 VGATE <36> @ PCZ19
0.22U_0402_10V6K AON6554 @680P_0603_50V7K
3
2
1
2
PHZ3 1 2
1
470K_0402_5%_TSM0B474J4702RE
PCZ21
PRZ34 0.22U_0402_10V6K
18.2K_0402_1% VSUM- 1 2
B CPU_B+ B
2
VSUM+
PCZ22 PRZ36 PCZ23 PRZ37 @
1
1000P_0402_50V7K
301_0402_1% 100P_0402_50V8J @32.4K_0402_1%
PRZ35 1 2 1 2 1 2 1 2
10U_0805_25V6K
10U_0805_25V6K
2200P_0402_50V7K
0.01U_0402_16V7K
2.61K_0402_1%
11K_0402_1%
680P_0402_50V7K
1
5
PRZ38
PCZ24
1
1
PRZ39 PRZ40 PCZ29
PCG13
PCZ27
PCZ28
PCZ47
PCZ26
1 2
0.22U_0402_10V6K 2.32K +-1% 0402 137K_0402_1% 390P_0402_50V7K
MDU1516URH
PCZ25 1 2 1 2 1 2
PHZ4
2
2
PQZ3
10K_0402_5%_ERTJ0ER103J
2
UGATE2 1 2 UGATE2-1 4
330P_0402_50V7K
1 2 1 2
PRZ43 PRZ42
2
430_0402_1% PRZ41 PCZ30 2.2_0603_5%

VSUM- 1 2 2K_0402_1% 680P_0402_50V7K PLZ3
3
2
1
0.22UH +-20% PCMB104T-R22MS 35A
1
PHASE2 PRZ45 1 4
PCZ31 1 2 1 2 10K_0402_1% +APU_CORE
0.1U_0603_50V7K PRZ46 ISEN2 1 2 2 3 1 2 ISEN1
2
1
PRZ44 @ PCZ32 @ 10_0402_5% BOOT21 2BOOT2_11 2
@100_0402_1% @820P_0402_50V7K 1 2 +APU_CORE @ PRZ49 PRZ51 PRZ48
PRZ47 PCZ33 @4.7_1206_5% 3.65K_0402_1% 10K_0402_1%
2.2_0603_5% 0.22U_0603_25V7K VSUM+ 1 2 PLZ3_2
APU_VDD_SEN_H <7>
2
LGATE2 4 PRZ53 PLZ3_1
1_0402_1%
1
PQZ4 VSUM- 1 2
@ PCZ34
AON6554 @680P_0603_50V7K
3
2
1
2
APU_VDD_SEN_L <7>
1
1 2
0.01U_0402_25V7K
PCZ35 PRZ54
2
10_0402_5%
A A

CPU_CORE/CPU_CORE_NB
Custom 0.3
VALGD MB L
5 4 3 2 1
5 4 3 2 1
+APU_CORE_NB
D +APU_CORE D
+APU_CORE +APU_CORE_NB
330uF/9m 22uF/0805 0.22uF/0402 10uF/0603 0.01uF/0402 180pF/0402
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
@22U_0805_6.3V6M
1
1
PCG8
PCG9
PCG10
PCG11
PCG15
APU_CORE 4 10 2 3 2
PCZ36
PCZ37
PCZ38
PCZ39
PCZ40
PCZ41
2
2
APU_CORE_NB 2 2 2 1 3
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
10U_0603_6.3V6M
1
PCG14
PCZ42
PCZ43
PCZ44
PCZ45
PCZ46
2
2
C C
180P_0402_50V8J
180P_0402_50V8J
180P_0402_50V8J
22U_0805_6.3V6M
22U_0805_6.3V6M
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
1
1
PCG16
PCG17
PCG18
PCG19
PCG20
PCZ48
PCZ49
PCZ50
PCZ51
2
2
+APU_CORE_NB
Local
0.01U_0402_50V7K
0.01U_0402_50V7K
0.01U_0402_50V7K
180P_0402_50V8J
180P_0402_50V8J
@180P_0402_50V8J
1
1
PCZ53
PCZ54
PCZ55
PCZ56
PCZ57
PCZ58
1 1
330U_D2_2V_Y
390U 2.5V M C6 R10M

+ +
PCG22
PCG23
2
@
2 2
B B
+APU_CORE Local
1 1 1 1
330U_D2_2V_Y
330U_D2_2V_Y
330U_D2_2V_Y
330U_D2_2V_Y
+ + + +
PCZ59
PCZ60
PCZ61
PCZ62
2 2 2 2
A A

Issued Date 2011/07/29 Deciphered Date Title
PROCESSOR DECOUPLING
A3 0.3
VALGD MB L
5 4 3 2 1
A B C D
+3VGS
PR807 @ @10K_0402_1%
10K_0402_1%
10K_0402_1%
10K_0402_1%
10K_0402_1%
10K_0402_1%
@10K_0402_1%
@10K_0402_1%
@10K_0402_1%
PR808 @10K_0402_1%
PR810 @10K_0402_1%
PL801
2
HCB2012KF-121T50 0805
10K_0402_1%
1 2
+VGA_B+
VBOOT:
PR803 @
PR805 @
PR806 @
PL804
Mars XT:0.85V 1 2
PR801
PR802
PR804
PR809
PR811
PR812
B+
1
0110100
HCB2012KF-121T50 0805
San Pro:0.9V
10U_0805_25V6K
10U_0805_25V6K
@0.1U_0402_25V6
2200P_0402_50V7K
GPU_VID5
GPU_VID4
GPU_VID3
GPU_VID2
GPU_VID1
GPU_VID0
GPU_VID5
GPU_VID4
GPU_VID3
GPU_VID2
GPU_VID1
GPU_VID0
0110000
PC801 @
1
PC803
PC804
PC802
1 1
2
PR820
1 2 VGA_VR_ON
<36> EC_VGA_EN 0_0402_5%
GPU_VID5
GPU_VID4
GPU_VID3
GPU_VID2
GPU_VID1
GPU_VID0
<17>
<17>
<17>
<17>
<17>
PR816 PR854 0_0603_5%
@2.2K_0402_1% HGATE2_VGA_1 1 2 HGATE2_VGA PQ801
1
1 2 CSD87351Q5D_SON8-7
+3VS
PR817 2
PR818 @ 2.2_0603_5% PC806 0.36UH_PDME104T-R36MS0R825_37A_20%
<17,50> GPU_GPIO0 1 2 BOOT2_VGA 2 1 BOOT2_2_VGA1 20.22U_0603_10V7K +VGA_CORE
@0_0402_5% 7 PL802
PHASE2_VGA 3 6 SW2_VGA 1 4
PR819 5
1 2 DPRSLPVR_VGA-1 4 LF2_VGA 2 3 V2N_VGA
2.2K_0402_1% 1 1 1 1
330U_D2_2V_Y
330U_D2_2V_Y
330U_D2_2V_Y
330U_D2_2V_Y
1
1
1_0402_1%
@4.7_1206_5%
3.65K_0402_1%
PR826 @
+3VS PR830 + + + +
PC807
PC808
PC809
PC810
10K_0402_1%
@1.91K_0402_1%
8
1 2 CLK_ENABLE#_VGA
PR827
LGATE2_VGA 2 2 2 2
PR828
PR829
1.91K_0402_1%
2
1
SNUB2_VGA
PR831
VSUM-_VGA
2
VSUM+_VGA
ISEN2_VGA
PR833
100K_0402_1%
@680P_0402_50V7K
> VGA_PWRGD
PC811 @
1 2
+3VS
1
1 PR834 2
2
2 @0_0402_5% 2
<17,50> GPU_GPIO0
1 PR835 2
@2.2K_0402_1% PC812
PSI#_VGA
1U_0603_10V6K +VGA_CORE
40
39
38
37
36
35
34
33
32
31
RBIAS_VGA
2 PR836 1 PU801 1 2
47K_0402_1%
CLK_EN#
VID6
VID5
VID4
VID3
VID2
VID1
VID0
DPRSLPVR
VR_ON
30
BOOT2 29
1 UGATE2 28
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2 PGOOD PHASE2 27
PSI# VSSP2
1
3 26
PC824
PC825
PC826
PC827
PC828
PC829
PC830
PC831
PC832
PC833
PC834
PC835
PC836
PC837
PC838
PC839
4 RBIAS LGATE2 25
5 VR_TT# VCCP 24 +5VS
2
VW_VGA 6 NTC PWM3 23
COMP_VGA 7 VW LGATE1 22
FB_VGA 8 COMP VSSP1 21
1 2ISEN3_VGA 9 FB PHASE1
ISEN3
1
UGATE1
10 PC872
BOOT1
ISUM+
ISEN2
ISEN1
ISUM-
VSEN
IMON
PC871 1U_0603_10V6K
8.06K_0402_1%
VDD
1000P_0402_50V7K
RTN
VIN
22P_0402_50V8J 41
@120K_0402_1%
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
2
AGND
2
1
PR840 @
PC873
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
ISL62883CHRTZ-T_TQFN40_5X5
PR841
11
12
13
14
15
16
17
18
19
20
1
PR842 PR864 @
PC840
PC841
PC842
PC843
PC844
PC845
PC846
PC851
PC852
PC853
PC854
PC855
PC856
PC857
2
499_0402_1% PC874 @0_0402_5%

1 2FB1_VGA1 2 1 2
ISUM-_VGA
1
2
VDD_VGA
390P_0402_50V7K
PC847 PR843 0_0402_5%
33P_0402_50V8J 1.4K_0402_1% IMON_VGA 1 2
+5VS
1 2 1 2 PR844
PR845 1 2
@11K_0402_1%
@0.047U_0402_16V7-K
2
VIN_VGA 1 2
1
PR846 <36> VGA_IMVP_IMON

PR865
PR847
+VGA_B+
1 2FB2_VGA1 2 0_0402_5% @0_0402_5%
ISEN2_VGA
2
PC848 221K_0402_1% 1 PR848 2 +VGA_B+

PC849
3 3
1
1
150P_0402_50V8J ISEN1_VGA 1_0402_5% +5VS

0.22U_0402_10V6K
1
PC876
PC877
1U_0603_10V6K
0.22U_0603_25V7K
PR849
0.22U_0402_10V6K
61.9K_0402_1%
2200P_0402_50V7K
2
2
1
BOOT1_VGA
PC875
10U_0805_25V6K
10U_0805_25V6K
@0.1U_0402_25V6
2
VGA_VSS_SEN
PC878 @
PC850
2
1
@0_0402_5%
1 2
PC879
PC880
PC881
+5VS
PR851 0_0603_5%
2
PR863 @ HGATE1_VGA_1 1 2 HGATE1_VGA
VSUM+_VGA
VSUM-_VGA PQ802
PR852 PC858 CSD87351Q5D_SON8-7
1
1 2 2.2_0603_5% 0.22U_0603_10V7K
+VGA_CORE
1
2 1 BOOT1_1_VGA 1 2 2
2.61K_0402_1%
PR850 0.36UH_PDME104T-R36MS0R825_37A_20%
PR853
10_0402_1%
0.33U_0603_10V7K
7 PL803
PHASE1_VGA 3 6 SW1_VGA 1 4
<20> VGA_CORE_SEN +VGA_CORE
2
5
0.047U_0603_25V7K
1
4 2 3 V1N_VGA
NTC_VGA
PC859 LF1_VGA
PC860
1
1
330P_0402_50V7K
PC861
3.65K_0402_1%
2
1
PR856
1_0402_1%
10K_0402_1%
@4.7_1206_5%
PR855 @
PR858
2
8
LGATE1_VGA
PR857
2
2
1
1
11K_0402_1%
2
1
PC862 PH802
PR859
1000P_0402_50V7K 10K_0402_1%_TSM0A103F34D1RZ
1 SNUB1_VGA
2
VSUM-_VGA
<20> VGA_VSS_SEN
2
Layout Note:
Place near Phase1 Choke
VSUM+_VGA
PR862
ISEN1_VGA
@680P_0402_50V7K
PC865 @
PR861 931_0402_1%
4
1 2 1 2 4
VSUM-_VGA
10_0402_1%
2
1
PC866
0.1U_0402_16V7K
2

VGA_COREP
1.0
VALGD MB L
A B C D
5 4 3 2 1
PR703
20K_0402_1%
D 0.95V_EN 1 2 D
PXS_PWREN <13,18,36,45,52>
1
PC702
100K_0402_5%
0.1U_0402_10V6K
2
PR707 +0.95VSP PJ701
1 2
+0.95VGS
2
1 2
B+ JUMP_43X118 @
@ PR704 @ PC703
@4.7_1206_5% @680P_0603_50V7K
PL701 1 2SNB_0.95V 1 2
HCB2012KF-121T50_0805 PU701
1 2 B+_0.95V 8 1 PR705 PC706
IN EN
10U_0805_25V6K
0_0603_5% 0.1U_0603_25V7K
2200P_0402_50V7K
@0.1U_0402_25V6
6 1
BST_0.95V 2BST_0.95V_1
1 2 PL702
BS
1
1
PC715
1UH_PCMB063T-1R0MS_12A_20%
+0.95VSP
PC705 @
PC704
9 10 LX_0.95V 1 2
GND LX
2
59K_0402_1%
47U_0805_6.3V6M
47U_0805_6.3V6M
22U_0805_6.3VAM
@22U_0805_6.3VAM
1
330P_0402_50V7K
1
1
PR701
4 FB_0.95V
C FB C
PC709
PC710
PC714
PC711
@ PC701
ILMT_0.95V 3 7 FB=0.6V
+3VALW
2
ILMT BYP
4.7U_0603_6.3V6K
2
2 5 LDO_0.95V
4.7U_0603_6.3V6K
PG LDO
PC713
ILMT_0.95V
PC712
SY8208DQNC_QFN10_3X3
1
1
2
0_0402_5% PR702
PR706
100K_0402_1%
2
2
+0.95V
TDC=4.56A
B B
A A

+0.95VSP
B 0.1
VALGD MB L
5 4 3 2 1
5 4 3 2 1
PR453
D EN_1.5V_VRAM 1 2 D
PXS_PWREN <13,18,36,45,51>
@30K_0402_1%
1
PC463
2
@0.1U_0402_10V6K PR454
1 2
SUSP# <36,40,45,47>
@0_0402_5%
@ PR455 @ PC452
@4.7_1206_5% @680P_0603_50V7K
PL451 1 2SNB_1.5V_VRAM 1 2
@HCB2012KF-121T50_0805 PU451
B+ 1 2 B+_1.5V_VRAM 8
IN EN
1 PC453
@0.1U_0603_25V7K
@10U_0805_25V6K
6BST_1.5V_VRAM
1 2 PL452
@2200P_0402_50V7K
@0.1U_0402_25V6
BS
1
1
@1UH_PCMB053T-1R0MS_7A_20%
PC456
+1.5VSP
PC455 @
9 10 1 2
PC454
LX_1.5V_VRAM
GND LX
2
@30.1K_0402_1%
@47U_0805_6.3V6M
@47U_0805_6.3V6M
@22U_0805_6.3VAM
@22U_0805_6.3VAM
1
C C
@220P_0402_50V7K
1
1
4 FB_1.5V_VRAM
PR451
FB
PC457
PC458
PC459
PC460
@ PC451
3
ILMT_1.5V_VRAM 7
+3VALW
2
ILMT BYP
@4.7U_0603_6.3V6K
2
ILMT_1.5V_VRAM 2 5LDO_1.5V_VRAM
@4.7U_0603_6.3V6K
PG LDO
PC462
1
PC461
@SY8208DQNC_QFN10_3X3
1
PR457
2
@0_0402_5% PR452
2
@20K_0402_1%
2
PJ451
+1.5VSP 1
1 2
2
+1.5VGS
@JUMP_43X118 @
B B
A A

Title
Issued Date 2011/10/03 Deciphered Date 2014/12/31
+1.5VSP(VRAM)
Custom 0.1
VALGD MB L
5 4 3 2 1
5 4 3 2 1
Version Change List ( P. I. R. List ) Page 1

Request
Item Page# Title Date Issue Description Solution Description Rev.
Owner
P41 P41-PWR-DCIN / RTC Battery 12/11 PWR add smart Adapter function ADD PQ208,PQ102,PR111,PR225,PR228,PR227;Del PR973,PR974,PR972,PR975
Ĳ
D D
2 P42 P42-PWR-BATTERY CONN/OTP 12/11 PWR add smart Adapter function change PQ206,PR110,PR222,PR221,PC109 part number
3 P51 P51-PWR-+0.95VSP 12/11 PWR modify 1.5V output level modify PR701&PR702 to 59K&100K
4 P50 P50-PWR-+VGA_CORE PWR PWR EMI rule Add PC802 CAP
5 P50 P50-PWR-+VGA_CORE 01/08 PWR vender FAE requset change VGA enable pin from SUSP# to EC_VGA_EN
6 P45 P45-PWR-+1.5VP/+1.8VSP 01/08 PWR 0.75V can't power on change 0.75V enable pin from SUSP to SUSP#
7 P42 P42-PWR-BATTERY CONN/OTP 01/08 PWR modify smart Adapter schematic modify smart Adapter schematic
8 P44 P44-PWR-3VALWP/5VALWP 02/23 PWR Add RC delay for 3V power sequence Add RC delay for 3V power sequence
9 P48 P48-PWR-CPU_CORE/CPU_CORE_NB 02/23 PWR modify over temperature setting modify over temperature setting
10 P42 P42-PWR-BATTERY CONN/OTP 02/23 PWR Units will shut down on Optimized Battery Health mode when plug out battery modify battery health mode schematic
11 P45 P45-PWR-+1.5VP/+1.8VSP 02/23 PWR VRAM transient fail Add remote sense schematic
change Mars XT VBOOT from 1.1V to 0.85V

12 P50 P50-PWR-+VGA_CORE 02/23 PWR AMD change VBOOT SPEC change Sun pro VBOOT from 1.1V to 0.9V
C C
13 P41,42,48,50 P41,42,48,50 01/10 PWR Add bead for cost down plan Add bead for cost down plan
B B
A A

PWR - PIR
0.1
5 4 3 2 1
5 4 3 2 1

Request
Owner
1.SW3 add DEBUG@
1 37 1114 2.add J13
D D
1.change netname form +3VS_VGA to +3VGS
2 38 1114 2.change netname form +V1.05S_VCCP to +3VALW
3.remove RG10
4.change U71 P/N form SA000063300 to SA00006D500 for DIS,.change U71 P/N form SA000057I00 to SA00005DO00 for UMA
3 36 1114 1.VR_ON reserve PD 10K
4 17 1114A 1.remove RV16,RV17
5 27 1114A 1.reserve RV687,RV92
6 12,30 1115 1.change netname from PCH_BT_ON# to BT_ON#

2.change netname from PCH_WL_OFF# to WL_OFF#
1.change 1.1VALW to 1.1VS circuit follow QAWYA

2. remove R1138,Q158,R1140(include discharge of 1.2VS and 2.5VS)
7 40 1115 3.change SUSP reverse circuit follow QAWYA
4.change SYSON reverse circuit follow QAWYA
5.remove VLDT_EN reverse circuit
6.add +1.5V to +1.5VS follow QAWYA
8 13 1116 1.change netname from LAN_CLKREQ# to CLKREQ_LAN#
9 13 1116A 1.change netname from WLAN_CLKREQ# to CLKREQ_WLAN#

C C
10 13,27,30,37 1.CMOS change port from port1 to port3

1116B 2.WLAN change port form port7 to port2
3.USB(R)change port form port8 to port0
11 35 1119C 1.change netname from +3V_PCH to +3VALW
12 11 1119D 1.remove R84
1.change net name from APU_VDD_RUN_FB_L toAPU_VDD_SEN_L

13 7 1119D 2.change net name from APU_VDD_SEN to APU_VDD_SEN_H
3..change net name from APU_VDDNB_SEN to APU_VDDNB_SEN_H
14 20 1119D 1.change net name from VCCSENSE_VGA to VGA_CORE_SEN

2.change net name from VSSSENSE_VGA to VGA_VSS_SEN
15 36 1119D 1.remove EC_VGA_EN

2.remove VGA_AC_DET
16 34 1120A 1.reserve Q96,R711
17 7 1120C 1.remove C159,C161,C210,C164

2.change net name from LVDS_A1 to DP0_TXP1_C
3.change net name from LVDS_A1# to DP0_TXN1_C
B 18 26 1120C 1.add RP26,R241,R242 B
19 26 1121C 1.remove R301,R302,R826,C422,U11
20 27 1121C 1.remove R687
21 19 1122 1.remove CV54,CV55,CV56,CV57,CV58,CV59
22 20 1122 1.remove CV96,CV97
23 36 1122A 1.remove C431,R305,C438,C439
24 7,26,36 1123A 1.remove C113,C115,RP26,R239~242 for eDP circuit

2.add R826
3.add "ENBKL"signal
4. change EC GPIO(VGATE and EC_TS_ON)
25 17,33,39 1126A 1. Change C736 from SGA00003000 to SE00000T780

2. Remove Q11
3. Set RV24,RV25,QV3 are @
4. Add REMOTE1+ to UV1.AF29 & REMOTE1- to UV1.AG29
26 38 1127 1. Change net name from +3VGS to +1.8VGS on U71 pin11
A 27 27 1127A 1.Change net name from DISPOFF# to BKOFF# A

2.update P04 table
28 33 1127A 1add ZZZ for MB PCB

PIR
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS VALGD MB L 2.0
5 4 3 2 1
5 4 3 2 1

Request
Owner
D 1.remove R801,R207,RV40,RL13,CL27 for GCLK circuit D
29 11,18,31,38 1128 2.GCLK circuit in p.38
30 31 1128 1.remove GCLK@ in RL3,CL7,QL1

2.change LL1 P/N to SHI00008W00
31 37 1128 1.change U40 P/N to SA00005LN00
32 28 1128A 1.change RP22 to RV94~RV96
33 32 1128B 1.change CL30 P/N to SE067102K80
34 11 1128B 1.change CLK_PCIE_LAN/CLK_PCIE_LAN# form port0 to port3

2.change CLK_PCIE_WLAN1/CLK_PCIE_WLAN1# from port1 to port2
35 28 1128B 1.add R3334,R3335
36 26 1129 1.add RA10,RA11,RA15,RA24,R1459,R1460
37 36,41 1129 1.add signal"ADP_ID_CLOSE"for smart adapter function
38 32,33 1130 1.remove OPT@ of C587

2.change from @EMI@ to EMI@ for CL30
C C
39 5,16 1130 1.change cap form .22u to .1u for PCIE Gen2
40 35 1130 1.change shot pad to .1u for CA64~CA66
41 39 1204 1.change JTS1 conn to SP010013W10
42 12,30 1204A 1.remove BT_ON#,add BT_DISABLE#
43 07 1204A 1.RP9.4 connect to +1.5V_APU,R348.1 connect to +1.5VS for leakage issue
44 11,18,31,38 1204B 1.add R801,R207,RV40,RL13,CL27 for GCLK circuit

2.add GCLK circuit in p.38
45 36 1205 1.change net name form NOVO# to EC_FAN_PWM in EC

2.change net name form EC_FAN_PWM to NOVO# in EC
3.change net name form ENBKL to APU_IMON in EC
4.change net name form APU_IMON to ENBKL in EC
46 38 1206 1.change RG2 to 10ohm,RG3 to 33ohm,RG4 to 33ohm

2.U74.2 change from +3V_LAN to +3VALW
47 39 1206A 1.change C736 to SE00000PL00(0805 package)
B B
48 38 1210 1.add GCLK@ in RG2,RG3,RG4
49 55,56 1210A 1.add P55,P56
50 03,12,33,37,39 1212 1.update BOM Structure Table

2.change U3 symbol to SA00003K820
3.change U35,U36 symbol to SA00003TV00
4.change U99 P/N to SA00001Z710
51 41~52 1213 1.update PWR circuit for BOM
52 20 1220 1.change LV7 BOM structure from PX@ to SHORT PAD@
53 40 1220 1.remove @ in Q157A
54 20 1224 1.add TEST POINT@ to TV15
55 18 1224 1.change net name from PXS_PWREN to PXS_PWREN# in QV2.2
56 28 1224 1.remove C528 based on LA-9901 DVT schematic
57 37 1224 1.change JKB1 from SP01000WK00 to SP010011A00

A 2.change JTP1,JPWRB1 from SP010014M10 to SP010010T00 A
58 34 1224 1.change JODD2 from SP01001FJ00 to SP010016C00

PIR
5 4 3 2 1
5 4 3 2 1

Request
Owner
1.change JSPK1 from SP02000RR00 to SP02000H700
59 35 1224
D D
60 37 1224 1.change JLED1 from SP01001A900 to SP010010T00
61 33 1225 1.change U99 from SA00001Z710 to SA000067P00
62 24,25 1225 1.change CHB form PX@ to MARS@
63 26 1225 1.change Panel PWM circuit 2132R@
63 29 1225 1.change Q93 & Q95 to Q93A & Q93B
64 27 0105 1.Change BID R311=>18K
65 35 0107 1.RA12,RA16 change to 100-ohm., RA13, RA14 to 15-ohm, ADD CA27,CA28 to 1uF
65 36 0108 1.add PXS_PWREN & EC_VGA_EN
66 14 ,34 0108 1.Change R177 ,180 & R550 from 0805 short pad to Jumper (J14, J15, & J10)
66 35 0110 1.RA22=>DEBUG@ for Beep 2. CA28 CA27=>2.2u for THD+N
67 27, 32 and 37 0110 1.R813=>220 ohm Bead 2.Add C492 for EMI request 3.DLL1=>EMI@
C C
68 33 0111 1.ADD ZZZ & ZZZ1 for 14"_DIS & 15"_DIS pcb
69 12 0114 1.ADD GPIO54 for RTD2132R@ 2.change U99
70 33 0116 1.change H21 from 2P8 to 4P6 2.change U99 to 1001101x (4D)
71 39 0116 1.add C737 &C735@ for USB droop (follow Intel)
72 0121 1.change D24 to SCA00001G00 for ESD request
73 28 0121 1.L30, L31 & L32 downsize to 0402,SM010005X00
74 39 0121 1/21 L51,L55,L58 &L66 change PN to SM070001N00 for action plan
75 29 0121 1/21 L35,L36,L37 &L38(HDMI) L49,L50,L53 & L54(USB3) change PN from SM070001S00 to SM070003K00 for action plan
76 10 0126 SIT: change C145 from OS-Con to POLY
77 37 0129 1/29 SIT: Del R806 & Q12 for change audio type from normal close to normal open.
B 78 36 0201 2/1 SIV: add PU resistor for LID_SW# B
79 35 0221 1.upgrade capacitors of CA36 & CA46 from 1uF to 2.2uF/X5R 2.AVDD_HP connect to standby power rail (+3VLP) for prevent speaker hum noise issue.
80 20 0221 1.Change Cap of CV66 to 220U 4V Y D2 ESR15M = SGA00000Y80 for PWR request
81 38 0221 1.add CG5 on 1.8VGS for GCLK 2.reserve CG6 & CG7 for vender request.
82 22~25 0221 1. p22 & p23==>Channel B Mars@ 2.p24 & p25==>ChannelA PX@
83 35 0225 1. add speaker bypass Cap CA38,CA39,CA40 & CA43 for EMI requirement
84 07 0226 1. add C438 100pF on H_THERMTRIP# for ESD requirement
85 34 0301 SIT: 3/1 Change footprint of JHDD1 from SANTA_191501-1_22P to LCN_ASF98-2231S10-0002_22P (DC010005W00 toDC010009C00)
86 34 0301 Del CV168 ,CV159,CV160 &CV189 for VRAM body size issue
87 37 0301 change C492, SE00000FD80 to SE074331K80 by Sourcer requiremrnt.
88 0301 LV4,LV10,L3,L6,L9,L11& L77 Downsize to 0402 BLM15AX221SN1D (Murata) ,SM01000MK00 by Sourcer requiremrnt.
A A
89 36 0301 Add R311=8.2K for SIT
90 11 0301 Change R85 from 0 ohm short pad @ to 33 ohm EMI@

PIR
5 4 3 2 1
5 4 3 2 1

Request
Owner
91 26 0301 1.add R1461 for RTD2132R ,MIIC_SDA :MIIC_SCL=0 : 1
D 92 35 0301 1.Change +VDDIO_HDA power rail from +3VALW to +3VS. D
93 26 0304 1.add R1462 for RTD2132R ,MIIC_SDA :MIIC_SCL=0 : 1 2.Del RP16.3 & RP16.4
94 12,13 0304 1.Change R367 from 10K to 100K. 2.Change R234 from 10K to 100K
94 32 0305 1.add CL32 & CL33 for ESD request.
95 32 0306 1.add R236 & R237 (LVDS_SEL) for C build only.
96 8 0306 1.add J3 for 1.5V
96 33 0306 1.Change Power rail of the U99 from +3VS to +3VGS.
97 12 0306 1.Change Power rail of the GPIO54 from +3VALW to +3VS.
98 12 0307 1.Change +1.5GVS enable pin from +VSB to +5Valw for Eup lot 6.
99 12,36 0311 1.Change BOM structure of R367 & R368 to @,2132S only 2.R237 & R236 =>@
Pre-MP 100 33 0311 1.Change U99 to SA00001Z710
C C
Pre-MP 101 12,36 & 26 0403 1.Reduce part count for RTD2132R only
Pre-MP 102 12,36 & 26 0403 1.Reduce part count for RTD2132R only
Pre-MP 103 34 0403 1.ODD Power Control cuicuits =>@
Pre-MP 104 33 0410 1.Change H17 form H_8P0N to H_7P0N SD309100280
Pre-MP 105 36 0410 1.Change RP11 form SD309100280(10K) to SD309100300(100K)
Pre-MP 106 18 0410 1.Change RV41 to 47K for Erp Lot6
Pre-MP 107 18 0410 1.Change RV37 from 20Kto 100K ,RV38 from 20K to 0 ohm.
Pre-MP 108 18 0410 1.Change RV37 from 20Kto 100K ,RV38 from 20K to 0 ohm.
Pre-MP 109 36 0411 1.Del Net VLDT_EN & 1V_ALW_EN
Pre-MP 110 7, 13 0412 1.change C438 from 100p to 1000p. 2. add C439, 1000p for ESD request.
B B
A A

PIR
5 4 3 2 1
A B C D E
EC_ON
B+ +3VLP
PU401
SY8208BQKC +3VALW
+EC_VCCA
LAN_PWR_ON#
+3V_LAN
QL1
PMV65XP
1 1
SUSP#
U35P +3VS
TPS22966DPUR
PXS_PWREN
U315V +3VGS
TPS22966DPUR
CMOS_ON#
Q70 +3V_CMOS
PMV65XP
SPOK , 095_18ALW_PWR_EN
PU502 +1.8VALW
SY8033BDBC
SUSP#
U1895P +1.8VS
TPS22966DPUR
2 2
PXS_PWREN
U1895V +1.8VGS
TPS22966DPUR
EC_ON
+VL
PU402
SY8208CQKC
+5VALW
SUSP#
U35P +5VS
TPS22966DPUR
SUSP# / SYSON
+0.75VS
PU501
RT8207MZQW
+1.5V
SUSP#
Q20 +1.5VS
3
LP2301ALT1G 3
PXS_PWREN
U315V +1.5VGS
TPS22966DPUR
SPOK , 095_18ALW_PWR_EN
PU601 +0.95VALW
TPS51212DSCR
095VS_PWR_EN
U1895P +0.95VS
TPS22966DPUR
PXS_PWREN
U1895V +0.95VGS
TPS22966DPUR
EC_VGA_EN
PU801 +VGA_CORE
ISL62883CHRTZ
4 4
VR_ON
+APU_CORE
PU901
ISL62771HRTZ
+APU_CORE_NB

Title
Issued Date Deciphered Date Power Map
Custom VAWGA/GB 0.1
A B C D E
5 4 3 2 1
+3VALW/ +3VS / +1.1VALW /+1.1VS /

+2.5VS / +1.2VS / +1.5V / +1.5V_APU
+3VLP +3VALW
+APU_CORE / +APU_CORE_NB
B+ B+ B+ +RTCBATT +3VGS / +1.5VGS
+1.8VGS / +0.95VGS
+VGA_CORE
3A 4B EC_RSMRST# 5 +3VGS
D EC D
V V
PU403 PU401 SPOK PU601 1V_ALW_EN
V
PBTN_OUT# 6 APU/FCH 20 PXS_RST# 21
+5VALW
V / VL +3VALW/+3VLP
V +1.1VALW
V V
SLP_S3# / SLP_S5# 7 U5 GPU_RST# GPU
V
AND GATE MarsXT
V V
4A 5
2A 3B EC_ON
KBRST# 10 19 APU_PCIE_RST#
4B 5
V
17 APU_PWRGD +3VS +1.5VA
BATT MODE 13 VGA_PEWGD
V
BATT+
1B
BATT+ PU301
V
LPC_RST# 18 12 PXS_PWREN
V
B+ WLAN / WiMAX
V
AC MODE VIN
Mini-Express Card
1A
VIN B+ +5VS +3VS
C C
ON/OFF
V
+3V_LAN
4A 2B
EC_VGA_EN 11
+5VS / +3VS / +1.8VS
V V
+5VALW B+ PU801
+VGA_CORE
V
LAN
17 +1.8VALW +5VALW
APU_PWRGD 15
V
PU901 VGATE
V
14 +APU_CORE /
VR_ON PU502
+APU_CORE_NB
V
+3VS +5VALW
V
+1.8VGS
SYSON
SUSP#
+5VALW
Q15
V
8 9
+3VGS
+3VALW B+
V
B
+5VALW +3VALW +5VALW U54 B
B+ +5VS
+CHGRTC_R +3VLP PU701
V
B+
U54 +1.5V +VSB
+0.95VGS
V
PU501 +3VS
V
+RTCBATT +1.5V
+1.5V +5VALW PU602
V
UV4
V
+1.2VS
+1.5VGS
+3VALW
Q20
V
+5VALW
+1.5VS B+
MODEL NAME: PU501

V
A
PCB NAME: +0.75VS A
REVISION:
DATE: 2012/12/10 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date Deciphered Date Title
Power sequence
COMPAL CONFIDENTIAL THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Custom
Date: Sheet of
Rev
0.1
5 4 3 2 1

(сервискомп-анна.рф) Lenovo G505s Compal LA-A091p r1.0

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(сервискомп-анна.рф) Lenovo G505s Compal LA-A091p r1.0

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A B C D E

VALGC_GD M/B Schematics Document

Security Classification Compal Secret Data Compal Electronics, Inc.

AMD MARS XT M2 128 bits

RJ45 Conn. Atheros USB20 Port 0

CRT Conn. FCH CRT (VGA DAC)

Thermal Sensor Int. MIC Conn.

4 Touch Screen 8172@ AR8172 LAN part

6 TS@ For Touch Screen circuit

7 X76@ X76 Level part for VRAM

8 GCLK@ Ues GCLK circuit

9 NOGCLK@ No use GCLK circuit

0 10 GCLK302@ 302 part for DIS

USB 2.0 Port (Left Side)

2 12 LVDS@ LVDS circuit

3 13 PXNOGCLK@ No use GCLK circuit in GPU

LDO@ LDO mode for LAN

SWR@ SWR mode for LAN

DEBUG@ For debug

OC# USB Port ME part

Device Address 4 4 2132R@ Panel PWM part for RTD2132R

Samsung 2048Mbits Samsung 2048Mbits

C "Mars" has the following requirements with regards to power-supply sequencing to C

avoid damaging the ASIC:

of the start of the ramp-up sequence, though a shorter ramp-up duration is

before or after both VDDC and VDD_CT have ramped up.

reach 90% before VDD_CT starts to ramp up (or vice versa).

Global ASIC Reset

AE9 P_UMI_RXP3 P_UMI_TXP3 AE3 UMI_TXN3_C C44 1 2 0.1U_0402_16V7K

Power Sequence of APU

Security Classification Compal Secret Data Compal Electronics, Inc.

EVENT# pull high 0.75V reference voltage +1.5V_APU

R6 1 2 1K_0402_5% MEM_MB_EVENT# +MEM_VREF

DISPLAY PORT MISC.

CPU TSI interface level shift HDT Debug conn

R56 1 2 300_0402_5% APU_PWRGD Q3 APU_TRST# 9 10 APU_PWRGD

Security Classification Compal Secret Data Compal Electronics, Inc.

Power Name Consumption

AH3 AH10 JUMP@

Security Classification Compal Secret Data Compal Electronics, Inc.

Security Classification Compal Secret Data Compal Electronics, Inc.

Security Classification Compal Secret Data Compal Electronics, Inc.

PCI EXPRESS INTERFACES

<30> CLK_PCIE_WLAN1# GPP_CLK2N B25 1 2

M26 GPP_CLK5P LFRAME# B27 LPC_FRAME# <36>

APU_RST# APU_RST# <7>

Date: Friday, April 12, 2013 Sheet 11 of 57

+AVDD_SATA 931_0402_1%2 1 R106 SATA_CALRN AF27

+3VS R108 1 2 10K_0402_5% AD22

TEST POINT@T13 AB6 G8

ACPI / WAKE UP EVENTS

DEBUG@ J15 USB3_RX0_P

D PX@ F21 J22 EC_PWM2

R158 1 2 8.2K_0402_5% CLKREQ_WLAN# E18 KSO_3/GPIO212 KSI_0/GPIO201 K22 100K_0402_5%

0 0 PX5 Security Classification Compal Secret Data Compal Electronics, Inc.

DEBUG@ 0 1 Reserved Issued Date 2012/11/13 Deciphered Date 2013/11/12 Title

220 ohm AA20

SM01000MK00 M20 R183 0_0603_5%

3 SM01000MK00 3/1 SIT downsize to 0402, BLM15AX221SN1D (Murata) 3

SM01000MK00 L12 0_0603_5%

R185 0_0603_5% P13 1 1 it to +3.3V_S5 directly if HWM is not used.

220 ohm POWER C226 1 2 2.2U_0402_6.3V6M is supported

J6 VSS VSS AA28