Data Converters

Digital Electronics (Data Converters)
1. A 10 - bit successive approximation ADC has a resolution of 10 mV. Determine digital

output for analog input of 4.365 V.
(a) 43610 (b) 43710
(c) 21810 (d) 25610
2. The aperture time (ns) required for the A/D converter is __________. (n=14, f=1 kHz)
3. For a dual slope type ADC, frequency of Clock is 1 MHz, Vreferance  1.0 . Fixed time period
T1 is 1ms, RC time constant is set to 2ms and Input voltage, Vi  5V . Value of Ramp voltage
Vs is ___________________V
4. In a 8-bit DAC, if the output is 1.55 V for (35)8 , then the full scale output is _________V.
5. If a 12-bit (3-digit) DAC that uses the BCD input code has a full scale output of 9.99V, then
the value of Vout for an input code of 0111 1001 0101 is __________ V.
6. For a dual slope type ADC, frequency of CLK is 1MHz, Vreferenc  5.0V . Fixed time period T1
is 1 ms and input voltage, Vi is 1V. Value of variable time period (T2) is _________ ms.
7. The analog output voltage of a 6 bit DAC with reference voltage as 15 V for the digital
input 011101 is _____ Volts.
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8. Consider the system given below
The clock input is connected to the 4 bit ring counter. The output of the ring counter act as
the clock for the other counters. All the counters shown in figure are synchronous counter
working at positive edge of clock. The output of all counters act as input to a 14 bit DAC with
step size (Δ) equal to 1 mV. The output of DAC after 20 clock pulses is _____ Volts.
9. The ratio of maximum conversion time of 8 bit digital ramp type ADC to that of 8 bit
successive approximation type is _____. (Assume both are applied with the clock of 20 kHz)
10. A certain 12 bit BCD digital to analog converter has full scale reading of 10.24 V. The step
size of converter is
(a) 10 mV (b) 1 mV
(c) 1.025 mV (d) 10.25 mV

11. Consider the circuit given below.
The full scale reading of Digital to Analog converter is 10.5 V. Each bit of Gray code converter
output is given to digital to Analog converter through an inverter. If input to the circuit is
110011, then corresponding output. Voltage Va is _____ Volts
12. A binary weighted resistor digital to analog converter has 6 bits as input and a reference
voltage of 10 volts. If resistance of MSB is 2 kΩ. Then smallest quantized value of output
current is _____ μA
13. A 16 bit DAC provides an Analog output which has a maximum value of 20 V. The output
may have an error of ∆V due to drift in its component values. How long can ∆V be before
the LSB would no longer be significant?
5 10
(a) 16
(b) 16
2 1 2 1
15 20
(c) 16 (d) 16
2 1 2 1
14. A ramp type ADC has the following parameters, n = 6, Vref = 10.2 V, clock frequency =
1MHz. Assume the threshold voltage for the comparator is 5 mV.__________is the digital word
for an input voltage of 3.4 V.
15. A ramp type ADC has the following parameters, n = 6, Vref = 10.2 V, clock frequency =
1MHz. Assume the threshold voltage for the comparator is 5 mV. __________ s is the
conversion time taken to reach this value. Input voltage is 3.4 V.
16. A five-bit DAC produces 10 mA for a digital input of 10100. For digital input of 11101
output current is ____________mA

17. The resolution of an n-bit D/A converter with a maximum input of 5V is 5 mV. The value
of n is
(a) 8 (b) 9
(c) 10 (d) 11
18. The step size of the DAC of the given figure can be changed by changing the value of RF .
Which of the following represents the required value of RF for a step size of 0.5 V?
(a) 80Ω (b) 160 Ω

(c) 1600 Ω (d) 800 Ω
19. An eight digital-ramp ADC with a 40 mV resolution use a clock frequency of 2.5 MHz and
comparator with VT =1 mV. The digital output for VA =6.000 V is
(a) 100101112 (b) 100101102

(c) 100111012 (d) 100111002
20. A sample and hold (S/H) circuit, having a holding capacitor of 0.1 nF, is used at the input
of an ADC ( analog-to-digital converter). The conversation time of the ADC is 1  sec , and
during this time, the capacitor should not loose more than 0.5% of the charge put across it
during the sampling time. The maximum value of the input signal to the S/H circuit is 5V. The
leakage current of the S/H circuit should be less than
(a) 2.5 mA (b) 0.25 mA

(c) 25.0 A (d) 2.5 A

21. Consider the following figure in which a computer is controlling the speed of a motor.
The 0 to 2 mA analog current from the DAC is amplified to produce motor speeds from 0 to
1000 rpm (revolution per minute). Number of bits required to be used if computer is able to
produce a motor speed that is within 2 rpm of the desired speed is _________
22. Consider the following basic current-out DAC circuit
Given that VREF =10V, R=10Ω and RL is much smaller than R. the full-scale output for this
DAC is
(a) 1 mA (b) 0.5 mA

(c) 1.5 mA (d) 1.875 mA

1000 rpm (revolution per minute). Which of the following gives the closest value of 328 rpm.
The motor speed be adjusted using 9 bits?
(a) 327.6 (b) 327.8

(c) 328.2 (d) 328.8
24. Consider the following input waveforms and the enable pulse for a 3-bit flash ADC. If
VREF =+8V then the resultant digital output is

(a) 001, 011, 111, 011, 010, 000, 100, 110

(b) 100, 110, 111, 110, 010, 000, 001, 011
(c) 100, 110, 110, 110, 010, 000, 001, 010
(d) 100, 111, 111, 111, 100, 010, 000, 001
1000 rpm (revolution per minute). The closest value to 250 rpm upto which the motor speed
of a 12 bit DAC can be adjusted is
(a) 250 (b) 250.061
(c) 249.939 (d) 348.061

26. In the circuit given below VREF =10V. Fine full scale value of the output______V
27. When a dual slope integrating DVM is used for voltage measurement, it integrates
analog input signal for 20 period of supply frequency of 50 Hz. Reference voltage is 2 V.
Then what is the conversion time while measuring 1 V dc signal?
(a) 0.4 s (b) 0.2 s

(c) 0.6 s (d) 0.8 s
28. What is the number of output bits required for an A/D converter to give a quantizing
error less than 1%?
(a) 7 (b) 16
(c) 8 (d) 5
29. The most preferred ADC in the design of digital multimeter is _____________
(a) Flash type (b) Single slope type

(c) Dual slope type (d) Successive approximation type
30. Analog inputs are converted to digital outputs using op-amps as comparators. Assuming
a 5-bit digital output, the number of comparators required would be
(a) 32 (b) 31
(c) 63 (d) 64
31. A 10 bit D/A converter provides an analog output which has maximum value of 10.23
volts. The resolution is _________ mV.

32. An analog voltage signal highest significant frequency is 1 kHz is to be digitally coded
with a resolution of 0.01% and covering a voltage range of 0 - 10 V. Determine analog value
of LSB.
(a) 1 mV (b)100 mV
(c) 610.4 V (d) 710.4 V
33. An analog voltage signal whose highest significant frequency is 1 kHz is to be coded with
a resolution of 0.01 percent for a voltage range of 0 – 100 V. The minimum sampling
frequency and the minimum number of bits should respectively be
(a) 1 kHz and 12 (b) 1 kHz and 14

(c) 2 kHz and 12 (d) 2 kHz and 14
34. A 6 bit R-2R ladder D/A converter has a reference voltage of 6.5 V. It meets standard
linearity. ____________ V is the output for 011100.
35. A 8-bit successive approximation DVM of 6V range is used to measure 2.235 V. The
contents of the SAR after ________ clock pulses is equal to the measured value.
36. If the switch in figure shown below is in position D, and the input resistance of the
amplifier Ri is 100 k, _______ is the attenuation factor.
37. An 8 bit DAC produces an output voltage of 2.0V for an input code of 01100100. What
will be the value of Vout for an input code of 10110011.
(a) 1.58 V (b) 2.58 V

(c) 3.58 V (d) 4.58 V

38. In a dual slope integrating type digital voltmeter, the first integration is carried out for 10
periods of the supply frequency of 50 Hz. If the reference voltage used is 2V, the total
conversion time for an output of 1V is
(a) 0.1 sec (b) 0.2 sec

(c) 0.25 sec (d) 0.3 sec
39. A 6 bit R-2R ladder D/A converter has a reference voltage of 6.5 V. It meets standard
linearity. Find the output for an input of 011100.
(a) 2.84 V (b) 3.84 V

(c) 4.84 V (d) 5.84 V
40. A 10 bit resistive divider is constructed such that the current through the LSB resistor is
100A. The maximum current that will flow through the MSB resistor
(a) 200 A (b)1 mA

(c) 51.2 mA (d) 102.4 mA
41. Which type of DVM is called as voltage to time conversion?
(a) Ramp type DVM (b) Dual stop integrating DVM

(c) Successive approximation DVM (d) Integrating type DVM
42. A 10 bit A/D converter is used to digitize an analog signal in the -10V to +10V range.
The maximum peak to ripple voltage that can be allowed in the D.C. supply voltage is nearly
(a) 10mV (b) 100mV

(c) 20mV (d) 50V
43. In a dual slope integrating DVM, the 1st integration is carried out for 2 periods of supply
frequency 50Hz. The DVM is used to measure a dc voltage of 2V and the reference voltage
is 5V. What is the conversion time?
(a) 140 ms (b) 20 ms

(c) 160 ms (d) 200 ms

Solutions
1. Ans: (a)
4.365
Solution: Digital output= =436.510  43610
10 mV
2. Ans: 9.6 to 9.8

E
Solution: Aperture time ta=
2πfEm
E 1 1 1
But  n
 14

Em 2 2 16384
f = 1 KHz
1
ta = 3
= 9.71 n sec
2π  10  16384
3. Ans: -2.5
tfix 1
Solution: Vs  Vin  5  2.5V
RC 2
4. Ans: 13.4 to 13.8

Solution: 358  (3  (8)  5)10  2910
1.55
 step size=  0.0534
29
 Full scale output= 28  0.0535  13.5V
5. Ans: 7.8 to 8.0

9.99
Solution: Step size=  10mV
999
0111 1001 0101
7 9 5
Vout  795  10mV  7.95V

6. Ans: 0.2
Vi 1
Solution: T2   T2  (1)  0.2 ms
Vref 5
7. Ans: 6.5 to 6.9

Solution: Analog voltage=resolution  binary equivalent
15
 25  0  24  1  23  1  22  1  21  0  20  1   6.79V
26 
8. Ans: 10.9 to 11.1

Solution: In 4 clock pulses each output of ring counter is complimented one. So in 20 clock
pulses each output is complimented 5 time. Output of every counter connected at input of
DAC will change 5 time
So input to 14 bit DAC is
I13 I12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 I0
1 0 1 0 1 0 1 0 1 1 1 0 1 1
Binary equivalent=10939
Analog output voltage=step size  binary equivalent  1 103  10939  10.939Volts
9. Ans: 32
Solution: fclk  20KHz
1
Tclk   50 sec
20K
Maximum conversion time of digital ramp type ADC
T1  2n Tclk  28  50  10 6 sec = 12.8msec
Maximum conversion time of successive approximation type ADC
T2  n  Tclk  8  50  10 6 sec = 0.4msec
T1 12.8m
  32
T2 0.4m
10. Ans: (d)

Solution: For a 12 bit BCD number
Range is 000 to 999
10.24
Step size= =10.25mV
999

11. Ans: 3.40 to 3.50

Solution: Input 110011
Gray code 101010
Input to digital to analog converter 010101=21
10.5
Analog voltage= 6  21  3.45V
2
12. Ans: 156.0 to 156.5

Solution: Resistance of LSB= 2n1  2k  25  2k  64k
10
Smallest quantized output current   156.25A
64k
13. Ans: (b)

20 S 10
Solution: Step size or resolution, S= 16
V as long as V  i.e. 16 the LSB will be
2 1 2 2 1
significant.
14. Ans: 10110

Vr10.2
Solution: Step voltage =   0.1594V = 159.4 mV
2 n
26
Comparator voltage = 5 mV = 0.005 V
3.405
No, of steps to reach 3.405 V = = 21.36 = 22
0.1594
Binary equivalent of 22 = 010110
digital word = 010110
15. Ans: 21.0 to 22.0

1 1
Solution: Clock period= T    1s
f 1  106
V 3.4
Conversion time= in  2n  T   26  1s =21.33 s
Vef 10.2
16. Ans: 14.5
Solution: The digital input 101002 is equal to decimal 20. Since IOUT =10 mA for 20, the
proportionality factor must be 0.5 mA. Thus, we can find IOUT for any digit input such as
111012  2910 as follows.
IOUT  0.5mA   29  14.5 mA

17. Ans: (c)

Solution: Here resolution and 5 mV and VFS is 5V
VFS
Now Resolution=
2 1n
5V
Or 5 mV= n
2 1
Or 2  1 = 1  103
n
2n  1000  1  1001
Since 2n  1001
Thus n=10
18. Ans: (d)

 5V 
Solution: Since step size= RF   
 8K 
0.5  8  103
RF   800
5
19. Ans: (a)

Solution: (Digital value)  (resolution)  VA  VT
(Digital value)  (40 mV)  6.001V
6.001V
Digital value   150.025
40mV
This indicates a digital value of 151 i.e. 100101112 in binary.
20. Ans: (a)

Solution: Leakage current is given by
1
0.5  Q
Q 100 0.005  CV
I  
t t t
0.005  0.1  10 9  5
I  2.5A
t

21. Ans: 9
Solution: Range of motor speed is 0 to 1000 rpm as the DAC goes from zero to full scale.
1000
Step size required is  2 rpm. So, we require at least  500 steps.
2
Now, we determine number of bits required so that there are at least 500 steps from zero to
full scale i.e.
2n  1  500
n9
So, at least 9 bits are required.
22. Ans: (d)

VREF
Solution: I0   1mA
R
This is the weight of the MSB. The outer 3 currents will be 0.5, 0.25, and 0.125 mA. So, the full
scale output will occur when the binary inputs are all HIGH so that each current switch is
closed. i.e. TOUT  1  0.5  0.25  0.125  1.875mA
23. Ans: (d)

 
Solution: With 9 bits, there will be 511 steps 29  1 . Thus the motor speed will go up in
1000 326
steps of  1.957 rpm. The number of steps needed to reach 326 rpm is  167.60 .
511 1.957
This is not a whole number of steps and so we will round it to 168. The actual motor speed
on the 168th step will be 168  1.957  328.8 rpm
24. Ans: (b)

Solution: The resultant digital output sequence is as shown below:100, 110, 111, 110, 100,
010, 000, 001
25. Ans: (b)

 
Solution: With 12 bits, there will be 4095 steps 212  1 . Thus the motor speed will go up in
1000
steps of  0.2442 rpm. The number of steps needed to reach 250 rpm is
4095

250
 1023.75 . This is not a whole number of steps and so we will around it to 1024. The
0.2441
actual motor speed on the 1024th step will be 1024  0.2442  250.061 rpm.
26. Ans: -9.0 to -9.5

Solution: The resolution is equal to the weight of the LSB, which we can determine by
VREF
setting B=0001=1 in VOUT  B
16
10V  1
i.e. resolution=  0.625V
16
and full scale output occurs at B=1111= 1510
10V  15
full scale=   9.375V
16
27. Ans: (c)

1
Solution: Vm  T1  Vref  T2 => 1V  20   2V  T 2
50Hz
1
T2   20  20 ms  200 ms  0.2s
2
Tconv  T1  T2  0.4s  0.2s  0.6s
28. Ans: (a)

Solution: For 1% quantizing error, count  100. For any A/D converter, the number of
quantized level (count) of inputs is given by
N  2n  1
For n=7, N=27  1  127  100
For less than 1% error, no of bits required n=7.
29. Ans: (c)

Solution: Accuracy of Dual slope type digital multi-meter is high as compare to others.
30. Ans: (b)

Solution: When op-amps are used as comparators in ADC, this means ADC is flash type
ADC. So, number of comparators required for n-bit ADC is 2n-1.
n= 25 – 1 = 31 comparators

31. Ans: 10
10.23 10.23 10.23
Solution: Re solution     10 mV
2n  1 210  1 1023
32. Ans: (c)

0.01 1
Solution: Resolution = 0.01% = 
100 10000
1 1

2n
10000
 Minimum number of bits, n  14 as 214  16384
(we cannot choose n=13 as 213  8192. Which is less than 10000)
1 1 1
Analog value of LSB =  10  14  10   10 V  610.4 V
2n
2 16384
33. Ans: (d)

Solution: Minimum sampling frequency = Nyquist sampling rate = 2 kHz
1
resolution  0.01   100
2 1
n
n  14
34. Ans: 2.84

VR 6.5 4 28
Solution: V0 
2n a
n1 
2n1  an2 2n2  ......  a121  a0 20 
2 6 
2  23  22  6.5 
64
 2.84 V
35. Ans: 8
Solution:
After 1st clock pulse: 1 0 0 0 0 0 0 0
128
 6V  3.011V
255
After 2nd clock pulse: 0 1 0 0 0 0 0 0
64
 6V  1.505V
255
After 3rd clock pulse: 0 1 1 0 0 0 0 0
96
 6V  2.258V
255
After 4th clock pulse: 0 1 0 1 0 0 0 0
80
 6V  1.882V
255


88
 6V  2.070V
255

92
 6V  2.164V
255
94
 6V  2.211V
255
95
 6V  2.235V
255
36. Ans: 11
Solution: Since the amplifier input resistance is in parallel with the attenuator resistance, this
parallel combination must be used in the voltage divider equation. The parallel resistance is
RR 100  103  10  103
Rp  i   9.09 k
R i  R 100  103  10  103
V0 Rp 9.09
Therefore,    0.0909
Vi R i 100
So, the attenuation factor is 1/0.0909=11.
37. Ans: (c)

Solution: Input code 01100100 = 10010
For an input of 100 output is 2.0 V
2
 proportinality factor K   0.02V
100
 for an input of 10110011, i.e. 17910
output is  0.02  179  3.58V
38. Ans: (d)
Solution: In a dual slope integrating type digital voltmeter
T2
Vin  Vref
T1
Where T1 is first integration time.

1
T1  10   0.2s
50
Vin  1V
Vref  2V
Vin T1 1 0.2
T2    0.1sec
Vref 2
Total conversion time = T1  T2  0.2  0.1  0.3sec
39. Ans: (a)

VR 6.5 4 28
Solution: V0 
2 n a n1 
2n1  an2 2n2  ...  a121  a0 20 
2 6 
2  23  22  6.5 
64
 2.84 V
40. Ans: (c)

Solution: In a weighted resistor D/A converter
1 1 1
1st LSB  n  10 
2  1 2  1 1023
2
For the 2nd LSB is 
1023
22
For the 3rd bit value is
1023
29 512
and for the 10th bit MSB, value is 
1023 1023
1
LSB   100A
1023
512
MSB   100  512  106  51.2 mA
1023
41. Ans: (a)
42. Ans: (c)

V V
Solution: Given, to
2 2
Range  V  20
V 20 20
Ripple voltage =  10   20mV
2  1 2  1 1023
N

43. Ans: (a)

1
Solution: T1  2   40ms
50
Vref 5
T2  T1   40   100ms
Vdc 2
T2  100ms
Tconv  T1  T2  40 ms  100 ms  140 ms

We recommend you to take the Chapter Test first and then

check the Solutions.

Chapters Solutions
1. Ans: (c)
Solution: Resolution = Vi = 5mV
Maximum Analog input = Vi(max) = 5V
1 n
Vi = n
 5 => 2 - 1 = 1000
2 1
n
2 = 1001
n must be 10
2. Ans: (a)
 1
Solution: Resolution= n => 0.4%= n
n8
2 2
3. Ans: (c)
IFS 2mA
Solution: Resolution=   7.84A;n  8
2  1 255
n
Ideal output= 138  7.84A  1082A

Error= 0.5%  F.S. output  0.5%  2mA  10A
The range output= (1082  10) A  1092 A to 1072  A
1072  A to 1092  A
4. Ans: (c)
5. Ans: (c)
1 1 100
Solution: %Resolution= N
 100%  4  100%   6.67%
2 1 2 1 15
6. Ans: (b)
Solution: (0111111001)2  (0111110100)2  (101)2  (5)10
25mV
Resolution=
5
FSD= resolution (2n  1)  5  103  1023  5.115volts  5.12volts

7. Ans: (a)
Solution: Resolution of weighted resistor DAC or
R
Step size= N1 F  Vi
2 RMSB
RF
1 5
2  1k
3
8  1000
RF   1.6k
5
8. Ans: (b)
Solution: Full scale reading=Resolution (2n  1)  2  103  (28  1) =51.mA
0.5
Error=   0.51  2.55mA
100
Analog output=Decimal equivalent  Resolution= 170  2  2.55mA   (340  2.55)mA
9 Ans: (b)
9.99
Solution: Step size = = 10 mV
999
0110 1001 0101
6 9 5
Output voltage=no. of bits  step size
Vout  695  10mV  6.95V
10. Ans: (b)

Solution: Conversion time is independent of VA in successive approximation ADC.
11. Ans: (d)

Solution: For an ADC, we have n=10 bit and VFS  5V
VFS 5 5
Resolution= = 10
  5.0 mV
2 1n
2  1 1023
12. Ans: (d)

Solution: t 0 : Set MSB (bit 5)
t1 : Set bit 4; clear bit 4
t 2 : Set bit 3; clear bit 3
t3 : Set bit 2

t 4 : Set bit 1; clear bit 1

t5 : Set LSB;
So digital result is 1001012
13. Ans: (a)

Solution: Maximum conversation time=Max. No of steps  Tclock  
 
 2  1   0.4 sec 
8
= 102 sec
102 sec
Average conversation time=  51 sec
2
14. Ans: (a)

1
Solution: Accuracy  LSB  Tcoff  T
2
1 10.24
Or  10  Tcoff  T
2 2
10.24
Or Tcoff   200V / 0 C
2  1024  (50  25) C
0
15. Ans: (a)

2n  1 15
Solution: Conversion time    7.5s
clock rate 2  106
1 1
Conversion rate  =  133 kilo conversions / s
tc 7.5  106

Data Converters

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Digital Electronics (Data Converters)

1. A 10 - bit successive approximation ADC has a resolution of 10 mV. Determine digital

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8. Consider the system given below

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11. Consider the circuit given below.

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(a) 80Ω (b) 160 Ω

(a) 100101112 (b) 100101102

(a) 2.5 mA (b) 0.25 mA

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22. Consider the following basic current-out DAC circuit

(a) 1 mA (b) 0.5 mA

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(a) 327.6 (b) 327.8

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(a) 001, 011, 111, 011, 010, 000, 100, 110

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(a) 0.4 s (b) 0.2 s

(a) Flash type (b) Single slope type

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(a) 1 kHz and 12 (b) 1 kHz and 14

(a) 1.58 V (b) 2.58 V

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(a) 0.1 sec (b) 0.2 sec

(a) 2.84 V (b) 3.84 V

(a) 200 A (b)1 mA

41. Which type of DVM is called as voltage to time conversion?

(a) Ramp type DVM (b) Dual stop integrating DVM

(a) 10mV (b) 100mV

(a) 140 ms (b) 20 ms

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2. Ans: 9.6 to 9.8

4. Ans: 13.4 to 13.8

 Full scale output= 28  0.0535  13.5V

5. Ans: 7.8 to 8.0

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7. Ans: 6.5 to 6.9

8. Ans: 10.9 to 11.1

10. Ans: (d)

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11. Ans: 3.40 to 3.50

12. Ans: 156.0 to 156.5

13. Ans: (b)

14. Ans: 10110

15. Ans: 21.0 to 22.0

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17. Ans: (c)

18. Ans: (d)

19. Ans: (a)

20. Ans: (a)

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22. Ans: (d)

23. Ans: (d)

24. Ans: (b)

25. Ans: (b)

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26. Ans: -9.0 to -9.5

27. Ans: (c)

28. Ans: (a)

For less than 1% error, no of bits required n=7.

29. Ans: (c)

30. Ans: (b)

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