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1 1

LC22 Schematic
2 2

Pentium-M
RS400MD+SB400

DATE: May. 5th Revision: 0.1

3 3

4 4

Title
Compal Electronics, Inc.
SCHEMATIC, M/B LA-2642P
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401380
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: 星期五, 七月 29, 2005 Sheet 1 of 48
A B C D E
5 4 3 2 1

Page Function

1 Cover Page

2 Index

3 Block Diagram

4 Notes List

D 5 Power Block D

6 Pentium-M(1/3)

7 Pentium-M(2/3)

8 CPU Decoupling/FAN(3/3)

9 RS400MD-FSB/A-PCIE(1/4)

10 RS400MD-DDRII/MISC(2/4)

11 RS400MD-DISPLAY(3/4)

12 RS400MD-PWR/GND(4/4)

13 DDRII-SODIMM0

14 DDRII-SODIMM1

15 TV_OUT/LVDS/CRT
C C
16 ClockGen ICS951413

17 SB400-PCIE/PCI/LPC/RTC(1/4)

18 SB400-USB/AC97/MISC.(2/4)

19 SB400-IDE/SATA(3/4)

20 SB400-Power/GND(4/4)

21 Hardware Trap

22 IDE/CD-ROM Conn.

23 USB/BlueTooth/FP

24 MINI_PCI SLOT-WLAN

25 BCM5751M-GLAN

26 RJ-45 Connector
B B

27 R5C842-PCI/CARD BUS/OHCI

28 CARD BUS/1394

29 AC97 Codec AD1981B/MDC

30 AMP./Audio Jack

31 ENE-KB910L/TPM

32 BIOS/EE-Prom/TP/KB/SW

33 DC TO DC

34 PWR DCIN/ Precharge

35 PWR CPU OTP

36 PWR-CHARGER

A 37 PWR-Battery Select A

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
38 PWR-3.3V/5V AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
39 +1.2VSP & +1.8VALWP
Compal Electronics, Inc.
40 PWR 0.9VSP/VCCP Title
SCHEMATIC, M/B LA-2642P
41 PWR CPU_CORE Size Document Number Rev

42 Optional VGA MVCORE Power 401380 B

Date: 星期五, 七月 29, 2005 Sheet 2 of 48


5 4 3 2 1
A B C D E

4
BLOCK DIAGRAM 4

Pentium-M
CPU Thermal Sensor Clock Generator

6,7,8 ADM1032ARM ICS951413CGLFT


6 16

FSB
TV-OUT 15
400/533MHz

CRT Conn.
15 400/533MHz FANController 6
(1.8V) SO-DIMM x 2(DDRII)
3
LVDS Conn.
ATI-RS400MD Memory Bus BANK 0,1,2,3 13,14 Power Buttom/SW/LED 32
3

15
VGA M10P Embeded
923 pin BGA 9,10,11,12 BATTERY 37
Broadcom PCIE BUS
RJ-45 BCM5751M

A-Link Express x 2
26 25
CHARGER 36

Bandwidth 500MB
2.5GHz(1.2V)
DC/DC Interface 33

3VALWP/5VALWP 38
480MHz
PCI BUS USB 2.0 Port *4
IDSEL: AD20 IRQE/F/G/H REQ#/GNT#2 IDSEL: AD18 IRQF/G REQ#/GNT#3 33MHz (3.3V) 23
VCCP/0.9VSP 40
ATI-SB400 Primary ATA

2 564 pin BGA IDE HDD 22 1.2VSP/1.8VALWP 39 2

Secondary ATA//SATA
17,18,19,20
ODD Module CPU_COR 41
22
Ricoh Mini PCI
R5C842 FOR WLAN AC-LINK
27 24 24.576MHz
LPC 33MHz

1394-Port CardBus*2 Embedded


28 28 Controller
MDC ADI
ENE KB910L Connector
31 29 AD1981B 29
CB PWR SW
CP 2211 28

Audio Amp. HP*1


RJ-11 MIC*1
TPA601730 30
1
Int. KB & 1

BIOS(1MB)
32 Touch-PAD 32

SPK 1W*2
30 Title
Compal Electronics, Inc.
SCHEMATIC, M/B LA-2642P
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401380
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: 星期五, 七月 29, 2005 Sheet 3 of 48
A B C D E
A B C D E

Voltage Rails Dip SW function


KBSEL0/1# 11:JP K/B 01:US K/B 10:UK K/B 00: Reserve
Power Plane Description S1 S3 S5 PASSWORD# 0:Override 1:Avaliable
FINGERPRINT# 0:Existence 1:Non-Existence
VIN Adapter power supply (19V) ON ON ON
B+ AC or battery power rail for power circuit. ON ON ON
1 1
+CPU_CORE Core voltage for CPU ON OFF OFF
+VCCP 1.2V switched power rail for CPU AGTL Bus ON OFF OFF
+1.2VS 1.2VS for PCI-Express ON OFF OFF
+1.8VS 1.8VS switched power rail ON OFF OFF Function Table
+1.8V 1.8V power rail ON ON OFF Function Japan
+0.9VS 0.9V power rail ON OFF OFF Commercial Consumer
+3.3V 3.3V switched power rail ON ON OFF NEC
Direct(Internet HK/CHINA Comment
+3VALW 3.3V always on power rail ON ON ON* LaVie Retailing)
+3VS 3.3V switched power rail ON OFF OFF
TV-OUT Yes
+5VALW 5V always on power rail ON ON ON*
Bluetooth No Yes Need BTO
+5VS 5V switched power rail ON OFF OFF
PWR LED No Not need
+RTCVCC RTC power ON ON ON (Odekake) Odekake
S/W I/II Key all same
4 in 1 Card No Yes
Adapter
Finger Print Yes (BTO) No Yes (BTO) No Need BTO
2 2
TPM Yes No Need BTO
W-LAN JP JP JP Oversea

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

External PCI Devices Chip Reversion


Device IDSEL# REQ#/GNT# Interrupts
Chip Phase ES Phase PP Phase MP1 Phae DR2
CardBus(R5C842) AD20 2 PIRQE/PIRQF/PIRQG/PIRQH
RS400MD A12 A21-LF A21-LF
AD18 3
SB400 A31 A31-LF A32-LF
Mini-PCI(WLAN) PIRQF/PIRQG
Clk Gen B C C
KB910L A0 A1 A1
AD1981B A A A

3 3

EC SM Bus1 address EC SM Bus2 address


Device Address Device Address
Main Battery 0001 011X b ADM1032 1001 110X b
EEPROM(24C16/02) 1010 000X b
Second Battery

SB400 SM Bus address


Device Address

Clock Generator 1101 001Xb


(ICS951413CYGLFT)
4 4
DDR DIMM0 1010 000Xb
DDR DIMM2 1010 001Xb

Compal Electronics, Inc.


Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-2642P
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
401380
星期五, 七月 29, 2005 Sheet 4 of 48
A B C D E
5 4 3 2 1

LC2 Power block


RTC Charger
Page 33
D D

Battery OVP CPU OTP


Page 35 Page 34
CHPRTC
Vin Detector
Page 33
Turn Off Turn Off

Input B+
DC IN Switch Page 35 +3VALWP: OCP:5.3A OVP:107%~115%
+5VALWP: OCP:7.8A OVP:107%~115%
(SC1403) Page 37
Always
C C

CHARGER +3VALW +1.5VS


CC:0.6A~3.3A Thermal protection: 150 degree C
CV:12.6V (G914G) Page 39
SUSP#
(MB3887)
Page 35
+3VALW +2.5VS
Thermal protection: 150 degree C
(G914E) Page 39
SUSP#

+3VALW +1.8VALWSB
Thermal protection: 150 degree C
(G914H) Page 39
MAINPWON
Battery
VL +3V_EC
B
Thermal protection: 150 degree C B

(G914C) Page 39
VL

CPU CORE
OCP:41A (Typical, 27A_min) +1.8VP: OCP:11.7A OVP:112%~117%
OVP:2V +1.2VSP: OCP:9.8A OVP:112%~117% +1.8VP:SUSP#
(MAX8743) +1.2VSP:SUSP#
(MAX1532A) Page 38
VR_ON Page 40

+1.8VP +0.9VSP
Protection:depend on +1.8VP
(APL5331) Page 39
SUSP

+1.2VSP +VCCP
A Protection:depend on +1.2VSP A

Page 39
SUSP#

Compal Electronics, Inc.


Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
SCHEMATIC, M/B LA-2642P
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number R ev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. B

Date: 星期五, 七月 29, 2005 Sheet 5 of 48


5 4 3 2 1
A B C D E

+VCCP
9 H_A#[3..31] H_D#[0..63] 9
JCPU1A

Dothan
H_A#3 P4 A19 H_D#0 1 2 ITP_TDO
H_A#4 A3# D0# H_D#1 R2 54.9_0603_1%
U4 A4# D1# A25
H_A#5 V3 A22 H_D#2 1 2 ITP_BPM#5
H_A#6 A5# D2# H_D#3 +VCCP R4 R3 54.9_0603_1%
R3 A6# D3# B21
H_A#7 V2 A24 H_D#4 37.4_0402_1% 1 2 ITP_BPM#4
H_A#8 A7# D4# H_D#5 ITP_TMS R5 54.9_0603_1%
W1 A8# D5# B26 1 2
H_A#9 T4 A21 H_D#6 R6 1 2 ITP_BPM#3
H_A#10 A9# D6# H_D#7 150_0603_1% R9 54.9_0603_1%
W2 A10# D7# B20
H_A#11 Y4 C20 H_D#8 1 2 ITP_TDI 1 2 ITP_BPM#2
H_A#12 A11# D8# H_D#9 R8 54.9_0603_1%
1 Y1 A12# D9# B24 1
H_A#13 U1 D24 H_D#10 1 2 ITP_TRST# 1 2 ITP_BPM#1
H_A#14 A13# D10# H_D#11 R7 680_0402_5% R10 54.9_0603_1%
AA3 A14# D11# E24
H_A#15 Y3 C26 H_D#12
H_A#16 A15# D12# H_D#13 ITP_TCK
AA2 A16# D13# B23 1 2 1 2 ITP_BPM#0
H_A#17 AF4 E23 H_D#14 R11 27.4_0603_1% R14 54.9_0603_1%
H_A#18 A17# D14# H_D#15
AC4 A18# D15# C25
H_A#19 AC7 H23 H_D#16
A19# D16#
ITP Test Point
H_A#20 AC3 G25 H_D#17
H_A#21 A20# D17# H_D#18
AD3 A21# D18# L23
H_A#22 AE4 M26 H_D#19
H_A#23 A22# D19# H_D#20
AD2 A23# D20# H24
H_A#24 AB4 F25 H_D#21 ITP_TDI @ PAD TP1
H_A#25 A24# D21# H_D#22 R12 ITP_TMS
AC6 A25# ADDR GROUP DATA GROUP D22# G24 @ PAD TP2
H_A#26 H_D#23 +3VS @ 22_0402_5% ITP_TCK
H_A#27
AD5
AE2
A26# D23# J23
M23 H_D#24
Thermal Sensor ITP_TDO 1 2 ITP_TDO_R
@ PAD TP3
A27# D24# @ PAD TP4

0.1U_0402_16V4Z
H_A#28 AD6 J25 H_D#25 R13 ITP_TRST# @ PAD TP5
H_A#29 A28# D25# H_D#26 @ 22_0402_5%
AF3 A29# D26# L26 1
H_A#30 AE1 N24 H_D#27 C2 H_RESET#1 2 RESETITP# @ PAD TP6
A30# D27#

1
H_A#31 AF1 M25 H_D#28
9 H_REQ#[0..4] A31# D28#
H26 H_D#29 H_THERMDA R19
H_REQ#0 D29# H_D#30 2
R2 REQ0# D30# N25

10K_0402_5%
H_REQ#1 P3 K25 H_D#31 1 @ PADTP16
REQ1# D31# 16 CLK_ITP_BCLK#
H_REQ#2 T2 Y26 H_D#32 C3 @ PAD TP8
16 CLK_ITP_BCLK

2
H_REQ#3 REQ2# D32# H_D#33 U1
P1 REQ3# D33# AA24
H_REQ#4 T1 T25 H_D#34 2200P_0402_50V7K~N 2 1 ITP_BPM#0 @ PAD TP9
REQ4# D34# H_D#35 2 D+ VDD1 ITP_BPM#1
D35# U23 @ PAD TP10
H_ADSTB#0 U3 V23 H_D#36 H_THERMDC 3 6 ITP_BPM#2 @ PAD TP11
9 H_ADSTB#0 H_ADSTB#1 ADSTB0# D36# H_D#37 D- ALERT# @ ITP_BPM#3
9 H_ADSTB#1 AE5 ADSTB1# D37# R24 @ PAD TP12
R26 H_D#38 8 4 ITP_BPM#4 @ PAD TP13
D38# 31,37 EC_SMB_CK2 SCLK THERM#
R23 H_D#39 ITP_BPM#5 @ PAD TP14
D39#
R17 1 2 1K_0402_5%CPU_CK_ITP A16 ITP_CLK0 D40# AA23 H_D#40
31,37 EC_SMB_DA2 7 SDATA GND 5
2 2
+VCCP
R16 1 2 1K_0402_5%CPU_CK_ITP# A15 ITP_CLK1 D41# U26 H_D#41 R15
V24 H_D#42 ITP_DBRESET# 2 1 @ PAD TP15
D42# H_D#43 @ 200_0402_1%
16 CLK_CPU_BCLK B15 BCLK0 D43# U25 ADM1032ARMZ_MSOP8~N
B14 HOST CLK V26 H_D#44
16 CLK_CPU_BCLK# BCLK1 D44# H_D#45
D45# Y23
AA26 H_D#46
D46# H_D#47
D47# Y25
N2 AB25 H_D#48
9 H_ADS# ADS# D48#
L1 AC23 H_D#49
9 H_BNR# BNR# D49#
J3 AB24 H_D#50
R18 200_0402_5% 9 H_BPRI# BPRI# D50# H_D#51 +VCCP
+VCCP 1 2 N4 BR0# D51# AC20
L4 AC22 H_D#52
9 H_DEFER# DEFER# D52# +3VS
H2 AC25 H_D#53
9 H_DRDY# DRDY# D53#
K3 AD23 H_D#54
9 H_HIT# HIT# D54#

1
56_0402_5% R20 K4 CONTROL GROUP AE22 H_D#55
9 H_HITM# HITM# D55#
1 2 H_IERR# A4 AF23 H_D#56 R461 R41
+VCCP IERR# D56#

1
J2 AD24 H_D#57 470_0402_5% 200_0402_5%
9 H_LOCK# LOCK# D57#
H_RESET# B11 AF20 H_D#58 R463
9,17 H_RESET# RESET# D58#
AE21 H_D#59 1K_0402_5%

2
D59# H_D#60 DPSLP_CPU#
9 H_RS#[0..2] D60# AD21
H_RS#0 H1 AF25 H_D#61

2
RS0# D61#

1
H_RS#1 K1 AF22 H_D#62 C C
H_RS#2 RS1# D62# H_D#63 Q18 Q17
L2 RS2# D63# AF26 16,17,41 H_DPSLP# 1 2 2 2
M3 R462 470_0402_5% B B PMBT3904_SOT23
9 H_TRDY# TRDY# E PMBT3904_SOT23 E

3
DINV0# D25 H_DINV#0 9
DINV1# J26 H_DINV#1 9
ITP_BPM#0 C8 T24
BPM0# DINV2# H_DINV#2 9
ITP_BPM#1 B8 AD20
BPM1# DINV3# H_DINV#3 9
ITP_BPM#2 A9
ITP_BPM#3 BPM2#
C9 BPM3# H_DSTBN#[0..3] 9
3 C23 H_DSTBN#0 3
ITP_DBRESET# DSTBN0# H_DSTBN#1
18 ITP_DBRESET# A7 DBR# DSTBN1# K24
M2 W25 H_DSTBN#2 +3VALW
9 H_DBSY# DBSY# DSTBN2# +VCCP
DPSLP_CPU# B7 AE24 H_DSTBN#3
DPSLP# DSTBN3# H_DSTBP#[0..3] 9 +VCCP
CPU_DPRSLP# G1 C22 H_DSTBP#0
DPRSTP# DSTBP0#

1
C19 L24 H_DSTBP#1
9 H_DPWR# DPWR# DSTBP1#
ITP_BPM#4 A10 MISC W24 H_DSTBP#2 R21
PRDY# DSTBP2#

1
ITP_BPM#5 B10 AE25 H_DSTBP#3 1K_0402_5%
PROCHOT# PREQ# DSTBP3# R23
B17 PROCHOT#

1
@ 470_0402_5%

2
H_PWRGOOD E4 R22
17 H_PWRGOOD PWRGOOD
17 H_SLP# H_SLP# A6 56_0402_5% H_PROCHOT# 18

2
ITP_TCK SLP# CPU_DPRSLP#
A13 TCK
ITP_TDI C12 C2 H_A20M# 17

2
TDI A20M#

1
ITP_TDO A12 D3 H_FERR# R26 C C
@ R24 TDO FERR# H_FERR# 17
1 2 1K_0402_5% C5 TEST1 IGNNE# A3 H_IGNNE# 17 56_0402_5% 2 17,41 H_DPRSLP 1 2 2 Q2
@ R25 1 2 1K_0402_5% F23 B5 B R1031 B PMBT3904_SOT23
TEST2 INIT# H_INIT# 17
ITP_TMS C11 D1 E Q1 @ 470_0402_5% E @
H_INTR 17

3
ITP_TRST# TMS LINT0 PMBT3904_SOT23
B13 D4 H_NMI 17

2
TRST# LINT1 PROCHOT#
LEGACY CPU
THERMAL
H_THERMDA B18 C6
H_THERMDC THERMDA DIODE STPCLK# H_STPCLK# 17 +VCCP +VCCP
A18 THERMDC SMI# B4 H_SMI# 17 1 2
H_THERMTRIP# C17 @ R479 0_0402_5%
THERMTRIP# D45 H_FERR#
1 2

1
@ RB521S-30_SOD523 R28 56_0402_5%
FOX_PZ47813-2749-42_DOTHAN +CPU_CORE R27
1 2 MAINPWON 18,34,35,38,40
R482 0_0402_5% 100K_0402_5% 1 2 H_PWRGOOD
R29 330_0402_5%

1
C

2
1 2 2 Q3 1 2 H_SLP#
4 B PMBT3904_SOT23 R30 200_0402_5% 4
C4 E

3
@ 0.1U_0402_10V6K~N 1 2 H_RESET#
R31 200_0402_5%
NA 1 2
+VCCP R32
56_0402_5%
H_THERMTRIP#
Compal Electronics, Inc.
Title
SCHEMATIC, M/B LA-2642P
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401380 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: 星期五, 七月 29, 2005 Sheet 6 of 48
A B C D E
A B C D E

41 VCCSENSE
41 VSSSENSE
+CPU_CORE
JCPU1C
Check it with ATI R33 JCPU1B
@ 54.9_0402_1% F20 T26
VCC VSS
OPEN +VCCA_PROC 1 2 VCCSENSE
VSSSENSE
AE7 VCCSENSE VSS A2 F22 VCC VSS U2
1 2 AF6 VSSSENSE VSS A5 G5 VCC VSS U6
J1 R34 A8 G21 U22
+1.8VS @ 54.9_0402_1% VSS VCC VSS
2 1 VSS A11 H6 VCC VSS U24
F26 VCCA0 VSS A14 H22 VCC VSS V1
@ PAD-OPEN 2x2m B1 A17 J5 V4
VCCA1 VSS VCC VSS
1 N1 VCCA2 VSS A20 J21 VCC VSS V5 1
AC26 VCCA3 VSS A23 K22 VCC VSS V21
J2 A26 U5 V25
+1.5VS +VCCP VSS VCC VSS
2 1 P23 VCCQ0 VSS B3 V6 VCC VSS W3
W4 VCCQ1 VSS B6 V22 VCC VSS W6

10U_1206_10V4Z
@ PAD-OPEN 2x2m B9 W5 W22
VSS VCC VSS
Dothan VSS B12 W21 VCC VSS W23

0.01U_0402_16V7K
SHORT 1 1 D10 VCCP VSS B16 Y6 VCC Dothan VSS W26
D12 VCCP VSS B19 Y22 VCC VSS Y2

C5

C6
D14 VCCP VSS B22 AA5 VCC VSS Y5
D16 VCCP VSS B25 AA7 VCC VSS Y21
2 2
E11 VCCP VSS C1 AA9 VCC VSS Y24
E13 VCCP VSS C4 AA11 VCC VSS AA1

POWER, GROUNG, RESERVED SIGNALS AND NC


E15 VCCP VSS C7 AA13 VCC VSS AA4
F10 VCCP VSS C10 AA15 VCC VSS AA6
F12 VCCP VSS C13 AA17 VCC VSS AA8
F14 VCCP VSS C15 AA19 VCC VSS AA10
F16 VCCP VSS C18 AA21 VCC VSS AA12
K6 VCCP VSS C21 AB6 VCC VSS AA14
L5 VCCP VSS C24 AB8 VCC VSS AA16
L21 VCCP VSS D2 AB10 VCC VSS AA18
M6 VCCP VSS D5 AB12 VCC VSS AA20
M22 VCCP VSS D7 AB14 VCC VSS AA22
N5 VCCP VSS D9 AB16 VCC POWER, GROUND VSS AA25
N21 VCCP VSS D11 AB18 VCC VSS AB3
P6 VCCP VSS D13 AB20 VCC VSS AB5
P22 VCCP VSS D15 AB22 VCC VSS AB7
R5 VCCP VSS D17 AC9 VCC VSS AB9
R21 VCCP VSS D19 AC11 VCC VSS AB11
T6 VCCP VSS D21 AC13 VCC VSS AB13
T22 VCCP VSS D23 AC15 VCC VSS AB15
U21 VCCP VSS D26 AC17 VCC VSS AB17
VSS E3 AC19 VCC VSS AB19
+CPU_CORE VSS E6 AD8 VCC VSS AB21
2 2
D6 VCC VSS E8 AD10 VCC VSS AB23
D8 VCC VSS E10 AD12 VCC VSS AB26
D18 VCC VSS E12 AD14 VCC VSS AC2
D20 VCC VSS E14 AD16 VCC VSS AC5
+VCCP D22 E16 AD18 AC8
VCC VSS VCC VSS
E5 VCC VSS E18 AE9 VCC VSS AC10
E7 VCC VSS E20 AE11 VCC VSS AC12
E9 VCC VSS E22 AE13 VCC VSS AC14
E17 VCC VSS E25 AE15 VCC VSS AC16
E19 VCC VSS F1 AE17 VCC VSS AC18
E21 VCC VSS F4 AE19 VCC VSS AC21
1

1
10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%
F6 VCC VSS F5 AF8 VCC VSS AC24
F8 VCC VSS F7 AF10 VCC VSS AD1
R465

R466

R467

R468

R469

R470
F18 VCC VSS F9 AF12 VCC VSS AD4
VSS F11 AF14 VCC VSS AD7
@ @ @ @ @ @ F13 AF16 AD9
2

2
VSS VCC VSS
41 H_PSI# E1 PSI# VSS F15 AF18 VCC VSS AD11
VSS F17 VSS AD13
41 CPU_VID0 E2 VID0 VSS F19 VSS AD15
41 CPU_VID1 F2 VID1 VSS F21 VSS AD17
41 CPU_VID2 F3 VID2 VSS F24 VSS AD19
41 CPU_VID3 G3 VID3 VSS G2 VSS AD22
41 CPU_VID4 G4 VID4 VSS G6 M4 VSS VSS AD25
41 CPU_VID5 H4 VID5 VSS G22 M5 VSS VSS AE3
VSS G23 M21 VSS VSS AE6
VSS G26 M24 VSS VSS AE8
+V_CPU_GTLREF AD26 GTLREF VSS H3 N3 VSS VSS AE10
VSS H5 N6 VSS VSS AE12
VSS H21 N22 VSS VSS AE14
16,21 CPU_BSEL0 C16 BSEL0 VSS H25 N23 VSS VSS AE16
16 CPU_BSEL1 C14 BSEL1 VSS J1 N26 VSS VSS AE18
VSS J4 P2 VSS VSS AE20
COMP0 P25 J6 P5 AE23
3 +VCCP 20 mils COMP1 COMP0 VSS VSS VSS 3
P26 COMP1 VSS J22 P21 VSS VSS AE26
5 mils COMP2 AB2 J24 P24 AF2
COMP2 VSS VSS VSS
R_A 20 mils COMP3 AB1 COMP3 VSS K2 R1 VSS VSS AF5
1

27.4_0402_1%

54.9_0402_1%

27.4_0402_1%

54.9_0402_1%

5 mils K5 R4 AF9
VSS VSS VSS
VSS K21 R6 VSS VSS AF11
R35 K23 R22 AF13
VSS VSS VSS
1

+V_CPU_GTLREF 1K_0603_1% B2 K26 R25 AF15


T1 PAD RSVD VSS VSS VSS
T3 PAD C3 L3 T3 AF17
2

RSVD VSS VSS VSS


R37

R38

R39

R40

T2 PAD E26 RSVD VSS L6 T5 VSS VSS AF19


T4 PAD AF7 RSVD VSS L22 T21 VSS VSS AF21
R_B T5 PAD AC1 L25 T23 AF24
2

RSVD VSS VSS VSS


1

VSS M1

R36 FOX_PZ47813-2749-42_DOTHAN
2K_0603_1% FOX_PZ47813-2749-42_DOTHAN
2

4 4

Compal Electronics, Inc.


Title
SCHEMATIC, M/B LA-2642P
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401380 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: 星期五 , 七月 29, 2005 Sheet 7 of 48
A B C D E
A B C D E

+CPU_CORE +CPU_CORE

1 1 1 1 1 1 1 1 1 1 ESR <= 3m ohm


Capacitor > 880 uF
C7 C8 C9 C10 C11 C12 C13 C14 C15 C16
10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
2 2 2 2 2 2 2 2 2 2
1 1

+CPU_CORE +CPU_CORE

Near VCORE regulator.


1 1 1 1 1 1 1 1 1 1
C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 +CPU_CORE
10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
2 2 2 2 2 2 2 2 2 2
@ @

330U_D2E_2.5VM_R9

330U_D2E_2.5VM_R9

330U_D2E_2.5VM_R9

330U_D2E_2.5VM_R9
+CPU_CORE +CPU_CORE
1 1 1 1

C39

C40

C29

C31
+ + + +
1 1 1 1 1 1 1 1 1 1
C32 C33 C30 C34 C35 C36 C27 C28 C37 C38 2 2 2 2
10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
2 2 2 2 2 2 2 2 2 2

+CPU_CORE

1 1 1 1 1
C41 C42 C43 C44 C45
10uF 0805 X5R High Frequence Decoupling
10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
2 2 2 2 2 2 2

+VCCP

1
1 1 1 1 1 1 1 1 1 1
+ C46
150U_D2_6.3VM C47 C48 C49 C50 C51 C52 C53 C54 C55 C56
0.1U_0402_10V6K~N 0.1U_0402_10V6K~N 0.1U_0402_10V6K~N 0.1U_0402_10V6K~N 0.1U_0402_10V6K~N 0.1U_0402_10V6K~N 0.1U_0402_10V6K~N 0.1U_0402_10V6K~N 0.1U_0402_10V6K~N 0.1U_0402_10V6K~N
2 2 2 2 2 2 2 2 2 2 2

3 3

+5VS +5VS_FAN
F2
1 2

1.1A_6VDC_FUSE
1

+5VS C57
FAN CONN. 1 0.1U_0402_16V4Z
1 2
R68
1K_0402_5%
4

SI3443DV_TSOP6
2

S
3
8

U2A
1

D G
1 2 3
P

31 EN_FAN1 +IN D
R43 100K_0402_5% 1 ENFAN1 2
OUT G Q56 Q52
2
1
2
5
6

-IN
G

2 S
3
4

C59 LM358AMX-NOPB_SO8~N 2N7002_SOT23


0.1U_0402_16V4Z
1

1 2
C909 2200P_0402_50V7K~N
1 2 FAN1
R44 100K_0402_5%
1

1 1 JP2
1

D2
U2B R42 @C911 C60 1
4 4
RB751V_SOD323 2
5 +IN 150K_0402_5% 3
2 2
7
2

OUT 1000P_0402_50V7K~N MOLEX_53398-0371~N


6
2

-IN 22U_1206_10V4Z
+3VS 1 2
LM358AMX-NOPB_SO8~N R45 10K_0402_5%
Compal Electronics, Inc.
31 FAN1_SPEED Title
1
C910 SCHEMATIC, M/B LA-2642P
0.01U_0402_16V7K THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
2 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401380 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: 星期五, 七月 29, 2005 Sheet 8 of 48
A B C D E
A B C D E

6 H_A#[3..31] H_D#[0..63] 6
6 H_REQ#[0..4] H_DINV#[0..3] 6
6 H_RS#[0..2] H_DSTBN#[0..3] 6
H_DSTBP#[0..3] 6
U3A
U3B
H_A#3 G34 PART 1 OF 7 E34 H_D#0
H_A#4 CPU_A3# CPU_D0# H_D#1 PART 2 OF 7
H32 CPU_A4# CPU_D1# D34 F6 GFX_RX0P GFX_TX0P D5
H_A#5 G33 D35 H_D#2 F5 D4
H_A#6 CPU_A5# CPU_D2# H_D#3 GFX_RX0N GFX_TX0N
G36 CPU_A6# CPU_D3# C35 G5 GFX_RX1P GFX_TX1P E4
H_A#7 G35 D36 H_D#4 G4 F4
H_A#8 CPU_A7# CPU_D4# H_D#5 GFX_RX1N GFX_TX1N
G32 CPU_A8# CPU_D5# C36 J6 GFX_RX2P GFX_TX2P J4
H_A#9 H34 B35 H_D#6 J5 H4
CPU_A9# CPU_D6# GFX_RX2N GFX_TX2N

ADDR. GROUP 0
H_A#10 J34 C34 H_D#7 K5 F2
H_A#11 CPU_A10# CPU_D7# H_D#8 GFX_RX3P GFX_TX3P
1 H31 CPU_A11# CPU_D8# C32 K4 GFX_RX3N GFX_TX3N F1 1
H_A#12 K34 B31 H_D#9 L4 G1

DATA GROUP 0
H_A#13 CPU_A12# CPU_D9# GFX_RX4P GFX_TX4P
H35 CPU_A13# CPU_D10# B33 H_D#10 M4 GFX_RX4N GFX_TX4N G2
H_A#14 J35 C31 H_D#11 M6 H2
H_A#15 CPU_A14# CPU_D11# GFX_RX5P GFX_TX5P
K30 CPU_A15# CPU_D12# A33 H_D#12 M5 GFX_RX5N GFX_TX5N J2
H_A#16 K31 C30 H_D#13 N5 J1
H_REQ#0 CPU_A16# CPU_D13# GFX_RX6P GFX_TX6P
F35 CPU_REQ0# CPU_D14# A30 H_D#14 N4 GFX_RX6N GFX_TX6N K1
H_REQ#1 G31 B32 H_D#15 P4 K2
H_REQ#2 CPU_REQ1# CPU_D15# GFX_RX7P GFX_TX7P
F32 CPU_REQ2# CPU_DBI0# C33 H_DINV#0 R4 GFX_RX7N GFX_TX7N L2
H_REQ#3 F34 A34 H_DSTBN#0 R6 M2
H_REQ#4 CPU_REQ3# CPU_DSTB0N# GFX_RX8P GFX_TX8P
E35 CPU_REQ4# CPU_DSTB0P# B34 H_DSTBP#0 R5 GFX_RX8N GFX_TX8N M1
6 H_ADSTB#0 H33 CPU_ADSTB0# T5 GFX_RX9P GFX_TX9P N1
CPU_D16# C25 H_D#16 T4 GFX_RX9N GFX_TX9N N2
H_A#17 M34 C29 H_D#17 U4 P2
H_A#18 CPU_A17# CPU_D17# GFX_RX10P GFX_TX10P
K35 CPU_A18# CPU_D18# C26 H_D#18 V4 GFX_RX10N GFX_TX10N R2
H_A#19 K36 C28 H_D#19 V6 R1
H_A#20 CPU_A19# CPU_D19# GFX_RX11P GFX_TX11P
J32 CPU_A20# CPU_D20# B28 H_D#20 V5 GFX_RX11N GFX_TX11N T1
H_A#21 L34 B29 H_D#21 W5 T2

PCIE I/F
CPU_A21# CPU_D21# GFX_RX12P GFX_TX12P

ADDR. GROUP 1
H_A#22 L35 C27 H_D#22 W4 U2
H_A#23 CPU_A22# CPU_D22# GFX_RX12N GFX_TX12N
N34 CPU_A23# CPU_D23# B30 H_D#23 Y4 GFX_RX13P GFX_TX13P V2
H_A#24 K33 E27 H_D#24 AA4 V1
H_A#25 CPU_A24# CPU_D24# GFX_RX13N GFX_TX13N
M35 CPU_A25# CPU_D25# B27 H_D#25 AA6 GFX_RX14P GFX_TX14P W1
H_A#26 K32 B26 H_D#26 AA5 W2

DATA GROUP 1
H_A#27 CPU_A26# CPU_D26# GFX_RX14N GFX_TX14N
N36 CPU_A27# CPU_D27# G25 H_D#27 AB5 GFX_RX15P GFX_TX15P Y2
H_A#28 L32 F27 H_D#28 AB4 AA2
H_A#29 CPU_A28# CPU_D28# GFX_RX15N GFX_TX15N
N31 CPU_A29# CPU_D29# B25 H_D#29
H_A#30 L31 E26 H_D#30 AB2 AA1
H_A#31 CPU_A30# CPU_D30# GPP_RX3P GPP_TX3P
N30 CPU_A31# CPU_D31# D27 H_D#31 AC2 GPP_RX3N GPP_TX3N AB1
6 H_ADSTB#1 L33 CPU_ADSTB1# CPU_DBI1# A27 H_DINV#1 25 PCIE_MRX_LTX_P0 AC4 GPP_RX2P GPP_TX2P AD2 PCIE_MTX_LRX_P0 C268 2 1 0.1U_0402_10V6K~N
PCIE_MTX_C_LRX_P0 25
CPU_DSTB1N# D28 H_DSTBN#1 25 PCIE_MRX_LTX_N0 AD4 GPP_RX2N GPP_TX2N AD1 PCIE_MTX_LRX_N0 C269 2 1 0.1U_0402_10V6K~N
PCIE_MTX_C_LRX_N0 25
6 H_ADS# F31 CPU_ADS# CPU_DSTB1P# E28 H_DSTBP#1
P-4 AGTL+ I/F
6 H_BNR# F30 CPU_BNR# AD6 GPP_RX1P/SB_RX3P GPP_TX1P/SB_TX3P AE1
2 2
6 H_BPRI# E29 CPU_BPRI# CPU_D32# C24 H_D#32 AD5 GPP_RX1N/SB_RX3N GPP_TX1N/SB_TX3N AE2
6 H_DEFER# E31 CPU_DEFER# CPU_D33# F25 H_D#33 AE5 GPP_RX0P/SB_RX2P GPP_TX0P/SB_TX2P AF2
6 H_DRDY# G30 CPU_DRDY# CPU_D34# E25 H_D#34 AE4 GPP_RX0N/SB_RX2N GPP_TX0N/SB_TX2N AG2
6 H_DBSY# F29 CPU_DBSY# CPU_D35# A24 H_D#35 C62 0.1U_0402_10V6K~N
6 H_DPWR# G28 DPWR# CPU_D36# D25 H_D#36 17 ALNK_MRX_STX_P1 AF3 SB_RX1P SB_TX1P AG1 ALNK_MTX_SRX_P1 1 2 ALNK_MTX_C_SRX_P1 17
6 H_LOCK# E33 CPU_LOCK# CPU_D37# B24 H_D#37 17 ALNK_MRX_STX_N1 AG3 SB_RX1N SB_TX1N AH1 ALNK_MTX_SRX_N1 1 2 C64 ALNK_MTX_C_SRX_N1 17
D31 C23 H_D#38 AG4 AH2 ALNK_MTX_SRX_P0 1 2 0.1U_0402_10V6K~N
RESERVED0 CPU_D38# 17 ALNK_MRX_STX_P0 SB_RX0P SB_TX0P ALNK_MTX_C_SRX_P0 17
6,17 H_RESET#
R47 1 2 0_0402_5% C17 CPU_CPURST# CPU_D39# B23 H_D#39 17 ALNK_MRX_STX_N0 AG5 SB_RX0N SB_TX0N AJ2 ALNK_MTX_SRX_N0 C63 1 2 C65 ALNK_MTX_C_SRX_N0 17
H_RS#2 D29 E23 H_D#40 0.1U_0402_10V6K~N 0.1U_0402_10V6K~N
CONTROL

H_RS#1 G29 CPU_RS2# CPU_D40#


@ B22 H_D#41 C1 AK4 PCE_TXISET
DATA GROUP 2

CPU_RS1# CPU_D41# 16 CLK_A_NB SB_CLKP PCE_TXISET


H_RS#0 E32 C21 H_D#42 D1
CPU_RS0# CPU_D42# 16 CLK_A_NB# SB_CLKN
CPU_D43# A21 H_D#43 PCE_ISET AH6 PCE_ISET
B21 H_D#44
6
6 H_TRDY#
H_HIT#
F28
D32
CPU_TRDY#
CPU_HIT#
CPU_D44#
CPU_D45# F22 H_D#45
D2
E2
GFX_CLKP
GFX_CLKN
PCIE CLK PCE_NCAL AJ4 PCE_NCAL
6 H_HITM# E30 CPU_HITM# CPU_D46# G24 H_D#46
CPU_D47# F24 H_D#47 17,21 SB_BMREQ# B5 BMREQ# PCE_PCAL AJ3 PCE_PCAL
CPU_DBI2# C22 H_DINV#2
@ R48 1 2 402_0603_1% E17 RESERVED1 CPU_DSTB2N# D24 H_DSTBN#2
NB_SUS_STAT# AJ6 E24 H_DSTBP#2 216DLP4AKA21G_BGA923_RS400MD
18 NB_SUS_STAT# SUS_STAT# CPU_DSTB2P#
17,18,25,42 NB_RST# C9 SYSRESET#
21 NB_PWRGD F8 POWERGOOD CPU_D48# E22 H_D#48
CPU_D49# D22 H_D#49
2 1 R49 HRCOMP B17 C20 H_D#50
CPU_COMP_P CPU_D50#
49.9_0603_1%
CPU_D51# B20 H_D#51
+VCCP 2 1 R50 HSCOMP D17 E21 H_D#52 +1.8V
CPU_COMP_N CPU_D52#
24.9_0603_1%
CPU_D53# D21 H_D#53
CPU_D54# C19 H_D#54
+1.8VS 1 2 +1.8VS_CPVDD H27 CPVDD CPU_D55# E20 H_D#55 Place R

1
FBM-11-160808-121-T_0603 F19 H_D#56 Close to Ball
MISC.

CPU_D56#
12.47mA L1 1 2CPVSS H26 B19 H_D#57 R52
DATA GROUP 3

C66 1U_0603_10V6K CPVSS CPU_D57#


A18 H_D#58 10K_0402_1% 2 1 R51 PCE_ISET 10 mils 27K_0402_5%
CPU_D58#
3 1 2 CPU_D59# C18 H_D#59 8.25K_0402_1%2 1 R54 PCE_TXISET 10 mils 3
CPU_VREF C1012 10U_0805_10V4Z~N
H28 CPU_VREF E18 H_D#60 +1.2VS 82.5_0402_1% 2 1 R53 PCE_NCAL 10 mils

2
CPU_D60# 10 mils
1 CPU_D61# D19 H_D#61 150_0402_1% 2 1 R55 PCE_PCAL
CPU_D62# D18 H_D#62 NB_SUS_STAT#
C67 AL5 B18 H_D#63
THERMALDIODE_P CPU_D63#
@ 220P_0402_50V7K AK5 THERMALDIODE_N CPU_DBI3# E19 H_DINV#3
2
CPU_DSTB3N# F21 H_DSTBN#3
B9 TESTMODE CPU_DSTB3P# G21 H_DSTBP#3

216DLP4AKA21G_BGA923_RS400MD
1

R57
4.7K_0402_5%
2

+VCCP

Normal ModePULL-DOWN
1

CPU_VREF
R56
Trace=15Mil 49.9_0603_1%
Space=15Mil
2

CPU_VREF
1
1U_0603_10V6K

1
4 C68 R58 4
100_0603_1%
2
2

Compal Electronics, Inc.


Title
SCHEMATIC, M/B LA-2642P
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401380 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: 星期五, 七月 29, 2005 Sheet 9 of 48
A B C D E
A B C D E

DDR_B_D[0..63] 14
DDR_A_D[0..63] 13

U3D
14 DDR_B_MA[0..17]
U3C DDR_B_MA0 AR24 AK8 DDR_B_D0
1 13 DDR_A_MA[0..17] MEMB_A0 PART 4 OF 7 MEMB_DQ0 1
DDR_A_MA0 AR30 AM6 DDR_A_D0 DDR_B_MA1 AR17 AL10 DDR_B_D1
DDR_A_MA1 MEMA_A0 PART 3 OF 7 MEMA_DQ0 DDR_A_D1 DDR_B_MA2 MEMB_A1 MEMB_DQ1 DDR_B_D2
AP24 MEMA_A1 MEMA_DQ1 AL6 AP17 MEMB_A2 MEMB_DQ2 AL11
DDR_A_MA2 AR23 AM8 DDR_A_D2 DDR_B_MA3 AR16 AK11 DDR_B_D3
DDR_A_MA3 MEMA_A2 MEMA_DQ2 DDR_A_D3 DDR_B_MA4 MEMB_A3 MEMB_DQ3 DDR_B_D4
AP23 MEMA_A3 MEMA_DQ3 AN8 AP16 MEMB_A4 MEMB_DQ4 AM9
DDR_A_MA4 AR22 AM5 DDR_A_D4 DDR_B_MA5 AR15 AL8 DDR_B_D5
DDR_A_MA5 MEMA_A4 MEMA_DQ4 DDR_A_D5 DDR_B_MA6 MEMB_A5 MEMB_DQ5 DDR_B_D6
AT22 MEMA_A5 MEMA_DQ5 AN5 AP15 MEMB_A6 MEMB_DQ6 AN11
DDR_A_MA6 AP22 AM7 DDR_A_D6 DDR_B_MA7 AP14 AM12 DDR_B_D7
DDR_A_MA7 MEMA_A6 MEMA_DQ6 DDR_A_D7 DDR_B_MA8 MEMB_A7 MEMB_DQ7 DDR_B_D8
AR21 MEMA_A7 MEMA_DQ7 AN7 AR14 MEMB_A8 MEMB_DQ8 AM16
DDR_A_MA8 AT21 AK1 DDR_A_D8 DDR_B_MA9 AR13 AM17 DDR_B_D9
DDR_A_MA9 MEMA_A8 MEMA_DQ8 DDR_A_D9 DDR_B_MA10 MEMB_A9 MEMB_DQ9 DDR_B_D10
AP21 MEMA_A9 MEMA_DQ9 AL1 AP25 MEMB_A10 MEMB_DQ10 AM19
DDR_A_MA10 AP31 AN1 DDR_A_D10 DDR_B_MA11 AP13 AN19 DDR_B_D11
DDR_A_MA11 MEMA_A10 MEMA_DQ10 DDR_A_D11 DDR_B_MA12 MEMB_A11 MEMB_DQ11 DDR_B_D12
AR20 MEMA_A11 MEMA_DQ11 AN3 AR12 MEMB_A12 MEMB_DQ12 AL16
DDR_A_MA12 AP20 AK2 DDR_A_D12 DDR_B_MA13 AR29 AN16 DDR_B_D13
DDR_A_MA13 MEMA_A12 MEMA_DQ12 DDR_A_D13 MEMB_A13 MEMB_DQ13 DDR_B_D14
AP35 MEMA_A13 MEMA_DQ13 AK3 AR11 MEMB_A14 MEMB_DQ14 AK17
AP19 AM3 DDR_A_D14 DDR_B_MA15 AP26 AL19 DDR_B_D15
DDR_A_MA15 AP32 MEMA_A14 MEMA_DQ14 DDR_A_D15 DDR_B_MA16 AR25 MEMB_A15 MEMB_DQ15 DDR_B_D16
MEMA_A15 MEMA_DQ15 AN2 MEMB_A16 MEMB_DQ16 AN20
DDR_A_MA16 AR31 AP2 DDR_A_D16 DDR_B_MA17 AP12 AL20 DDR_B_D17
DDR_A_MA17 AR19 MEMA_A16 MEMA_DQ16 DDR_A_D17 MEMB_A17 MEMB_DQ17 DDR_B_D18
MEMA_A17 MEMA_DQ17 AP3 MEMB_DQ18 AN23
AP5 DDR_A_D18 AM24 DDR_B_D19
13 DDR_A_DM[0..7] MEMA_DQ18 14 DDR_B_DM[0..7] MEMB_DQ19
DDR_A_DM0 AJ7 AR5 DDR_A_D19 DDR_B_DM0 AM10 AM20 DDR_B_D20
DDR_A_DM1 MEMA_DM0 MEMA_DQ19 DDR_A_D20 DDR_B_DM1 MEMB_DM0 MEMB_DQ20 DDR_B_D21
AL2 MEMA_DM1 MEMA_DQ20 AP1 AN17 MEMB_DM1 MEMB_DQ21 AM21
DDR_A_DM2 AR3 AR2 DDR_A_D21 DDR_B_DM2 AK20 AN22 DDR_B_D22
DDR_A_DM3 MEMA_DM2 MEMA_DQ21 DDR_A_D22 DDR_B_DM3 MEMB_DM2 MEMB_DQ22 DDR_B_D23
AR7 MEMA_DM3 MEMA_DQ22 AT4 AN25 MEMB_DM3 MEMB_DQ23 AM23
DDR_A_DM4 AK36 AR4 DDR_A_D23 DDR_B_DM4 AL32 AL25 DDR_B_D24
DDR_A_DM5 MEMA_DM4 MEMA_DQ23 DDR_A_D24 DDR_B_DM5 MEMB_DM4 MEMB_DQ24 DDR_B_D25
AF34 MEMA_DM5 MEMA_DQ24 AP7 AF32 MEMB_DM5 MEMB_DQ25 AM25
DDR_A_DM6 AA35 AT7 DDR_A_D25 DDR_B_DM6 W33 AL26 DDR_B_D26
DDR_A_DM7 MEMA_DM6 MEMA_DQ25 DDR_A_D26 DDR_B_DM7 MEMB_DM6 MEMB_DQ26 DDR_B_D27
T35 MEMA_DM7 MEMA_DQ26 AR9 T30 MEMB_DM7 MEMB_DQ27 AK27
AP10 DDR_A_D27 AL23 DDR_B_D28
MEMA_DQ27 DDR_A_D28 MEMB_DQ28 DDR_B_D29
13 DDR_A_RAS# AR32 MEMA_RAS# MEMA_DQ28 AP6 14 DDR_B_RAS# AR26 MEMB_RAS# MEMB_DQ29 AK23
AR34 AR6 DDR_A_D29 AT28 AM27 DDR_B_D30
13 DDR_A_CAS# MEMA_CAS# MEMA_DQ29 14 DDR_B_CAS# MEMB_CAS# MEMB_DQ30
AT33 AP9 DDR_A_D30 AP28 AK26 DDR_B_D31
2 13 DDR_A_WE# MEMA_WE# MEMA_DQ30 14 DDR_B_WE# MEMB_WE# MEMB_DQ31 2
AT9 DDR_A_D31 AM33 DDR_B_D32
13 DDR_A_DQS[0..7] MEMA_DQ31 14 DDR_B_DQS[0..7] MEMB_DQ32
DDR_A_DQS0 AL7 AM34 DDR_A_D32 DDR_B_DQS0 AM11 AL31 DDR_B_D33
DDR_A_DQS1 AM2 MEMA_DQS0P MEMA_DQ32 DDR_A_D33 DDR_B_DQS1 MEMB_DQS0P MEMB_DQ33 DDR_B_D34
MEMA_DQS1P MEMA_DQ33 AL34 AL17 MEMB_DQS1P MEMB_DQ34 AH32
DDR_A_DQS2 AP4 AH35 DDR_A_D34 DDR_B_DQS2 AM22 AH33 DDR_B_D35
DDR_A_DQS3 AR8 MEMA_DQS2P MEMA_DQ34 DDR_A_D35 DDR_B_DQS3 MEMB_DQS2P MEMB_DQ35 DDR_B_D36
MEMA_DQS3P MEMA_DQ35 AH34 AN26 MEMB_DQS3P MEMB_DQ36 AM31
DDR_A_DQS4 AK34 AM35 DDR_A_D36 DDR_B_DQS4 AK32 AL33 DDR_B_D37

MEM_A I/F
DDR_A_DQS5 AE36 MEMA_DQS4P MEMA_DQ36 DDR_A_D37 DDR_B_DQS5 MEMB_DQS4P MEMB_DQ37 DDR_B_D38
MEMA_DQS5P MEMA_DQ37 AL35 AE32 MEMB_DQS5P MEMB_DQ38 AJ32
DDR_A_DQS6 Y35 AJ35 DDR_A_D38 DDR_B_DQS6 W30 AJ33 DDR_B_D39
DDR_A_DQS7 R36 MEMA_DQS6P MEMA_DQ38 DDR_A_D39 DDR_B_DQS7 MEMB_DQS6P MEMB_DQ39 DDR_B_D40
AJ34 P32 AH30

MEM_B I/F
MEMA_DQS7P MEMA_DQ39 DDR_A_D40 MEMB_DQS7P MEMB_DQ40 DDR_B_D41
13 DDR_A_DQS#[0..7] MEMA_DQ40 AG34 14 DDR_B_DQS#[0..7] MEMB_DQ41 AF31
DDR_A_DQS#0 AK7 AF35 DDR_A_D41 DDR_B_DQS#0 AN10 AD32 DDR_B_D42
DDR_A_DQS#1 AL3 MEMA_DQS0N MEMA_DQ41 DDR_A_D42 DDR_B_DQS#1 AM18 MEMB_DQS0N MEMB_DQ42 DDR_B_D43
MEMA_DQS1N MEMA_DQ42 AD35 MEMB_DQS1N MEMB_DQ43 AE30
DDR_A_DQS#2 AT3 AC35 DDR_A_D43 DDR_B_DQS#2 AL22 AG32 DDR_B_D44
DDR_A_DQS#3 AP8 MEMA_DQS2N MEMA_DQ43 DDR_A_D44 DDR_B_DQS#3 AM26 MEMB_DQS2N MEMB_DQ44 DDR_B_D45
MEMA_DQS3N MEMA_DQ44 AG36 MEMB_DQS3N MEMB_DQ45 AH31
DDR_A_DQS#4 AK35 AG35 DDR_A_D45 DDR_B_DQS#4 AK31 AE33 DDR_B_D46
DDR_A_DQS#5 AE35 MEMA_DQS4N MEMA_DQ45 DDR_A_D46 DDR_B_DQS#5 AF33 MEMB_DQS4N MEMB_DQ46 DDR_B_D47
MEMA_DQS5N MEMA_DQ46 AE34 MEMB_DQS5N MEMB_DQ47 AE31
DDR_A_DQS#6 AA34 AD34 DDR_A_D47 DDR_B_DQS#6 W31 Y32 DDR_B_D48
DDR_A_DQS#7 T36 MEMA_DQS6N MEMA_DQ47 DDR_A_D48 DDR_B_DQS#7 P31 MEMB_DQS6N MEMB_DQ48 DDR_B_D49
MEMA_DQS7N MEMA_DQ48 AB35 MEMB_DQS7N MEMB_DQ49 W32
AA36 DDR_A_D49 U32 DDR_B_D50
MEMA_DQ49 DDR_A_D50 MEMB_DQ50 DDR_B_D51
Place these R and C 13 DDR_A_CLK0# AM32 MEMA_CK0N MEMA_DQ50 W34 14 DDR_B_CLK0# AN29 MEMB_CK0N MEMB_DQ51 U33
AN31 V36 DDR_A_D51 AM29 Y31 DDR_B_D52
close to relative Ball. 13 DDR_A_CLK0
AN15
MEMA_CK0P MEMA_DQ51
AC34 DDR_A_D52 14 DDR_B_CLK0
AN13
MEMB_CK0P MEMB_DQ52
Y33 DDR_B_D53
13 DDR_A_CLK1# MEMA_CK1N MEMA_DQ52 DDR_A_D53 14 DDR_B_CLK1# MEMB_CK1N MEMB_DQ53 DDR_B_D54
13 DDR_A_CLK1 AN14 MEMA_CK1P MEMA_DQ53 AB34 14 DDR_B_CLK1 AM14 MEMB_CK1P MEMB_DQ54 U30
AB30 Y34 DDR_A_D54 AB32 U31 DDR_B_D55
+1.8V MEMA_CK2N MEMA_DQ54 DDR_A_D55 MEMB_CK2N MEMB_DQ55 DDR_B_D56
AB31 MEMA_CK2P MEMA_DQ55 W35 AC33 MEMB_CK2P MEMB_DQ56 T33
AL29 V34 DDR_A_D56 AN28 T31 DDR_B_D57
MEMA_CK3N MEMA_DQ56 DDR_A_D57 MEMB_CK3N MEMB_DQ57 DDR_B_D58
AM30 MEMA_CK3P MEMA_DQ57 U34 AM28 MEMB_CK3P MEMB_DQ58 N32
AK14 R34 DDR_A_D58 AL13 M32 DDR_B_D59
MEMA_CK4N MEMA_DQ58 MEMB_CK4N MEMB_DQ59
0.1U_0402_10V6K~N 0.1U_0402_10V6K~N

AL14 P34 DDR_A_D59 AM13 T32 DDR_B_D60


MEMA_CK4P MEMA_DQ59 DDR_A_D60 MEMB_CK4P MEMB_DQ60 DDR_B_D61
AA33 MEMA_CK5N MEMA_DQ60 V35 AC32 MEMB_CK5N MEMB_DQ61 R32
1
1K_0603_1%

R59 1 AB33 U35 DDR_A_D61 AC31 P33 DDR_B_D62


3
MEMA_CK5P MEMA_DQ61 DDR_A_D62 MEMB_CK5P MEMB_DQ62 DDR_B_D63 +1.8V 3
MEMA_DQ62 R35 MEMB_DQ63 N33
AR18 P35 DDR_A_D63 AP11
C69 13 DDR_A_CKE0 MEMA_CKE0 MEMA_DQ63 14 DDR_B_CKE0 MEMB_CKE0 MEM_COMPN
13 DDR_A_CKE1 AP18 MEMA_CKE1 14 DDR_B_CKE1 AR10 MEMB_CKE1 MEM_COMPN AN35 1 2
2 R60 61.9_0603_1%
2

+DDR_VREF AR33 AK30 MPVDD 1 2 +1.8VS AR27 AM4 MEM_COMPP 1 2


13 DDR_A_CS0# MEMA_CS0# MPVDD FBM-11-160808-121-T_0603 14 DDR_B_CS0# MEMB_CS0# MEM_COMPP R61 61.9_0603_1%
13 DDR_A_CS1# AR35 MEMA_CS1# 14 DDR_B_CS1# AP29 MEMB_CS1#
1
1K_0603_1%

R62 1 AP33 L2 14.69mA AP27 N35 MEM_CAP2 1 2


MEMA_CS2# MPVSS MEMB_CS2# MEM_CAP2 C73 0.47U_0603_16V4Z
AP36 MEMA_CS3# MPVSS AL30 1 2 AP30 MEMB_CS3#
C71 1U_0603_10V6K AL4 MEM_CAP1 1 2
C70 MEM_CAP1 C72 0.47U_0603_16V4Z
13 DDR_A_ODT0 AP34 MEMA_ODT0 1 2 14 DDR_B_ODT0 AT27 MEMB_ODT0
2 C1013 10U_0805_10V4Z~N +DDR_VREF
AN34 AN32 AR28 AN36 MEM_STRAP 21
2

MEMA_ODT1 MEM_VREF MEMB_ODT1 MEM_VMODE


216DLP4AKA21G_BGA923_RS400MD 216DLP4AKA21G_BGA923_RS400MD

4 4

Compal Electronics, Inc.


Title
SCHEMATIC, M/B LA-2642P
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401380 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: 星期五, 七月 29, 2005 Sheet 10 of 48
A B C D E
5 4 3 2 1

AVDD DAC VDD (2.5V/3.3V)


AVDDDI DIGITAL VDD (1.8V)
AVDDQ DAC2 BANDGAP REF (1.8V)
PLLVDD PLL VDD (1.8V) +3VS

+3VDDR 1 2 1.56mA
+3VS 1 R63 0_0603_5%
PUT AVDD, AVDDDI, AVDDQ, 63.31mA
PLVDD DECOUPLING CAPS ON THE 1 2 +3VDDR3 C74
FBM-11-160808-121-T_0603 1 1U_0603_10V6K
BOTTOM, CLOSE TO BALLS 2
L3
D D
C75
0.1U_0402_16V4Z
2

+1.8VS
4.04mA U3E

1 2 +1.8VDDI G10 PART 5 OF 7 A9


VDDR3_1 TXOUT_U0N LVDS_TXU0- 15
FBM-11-160808-121-T_0603 F9 A10
VDDR3_2 TXOUT_U0P LVDS_TXU0+ 15
L4 B10
TXOUT_U1N LVDS_TXU1- 15
+1.8VS 1 C15 C11
AVDD TXOUT_U1P LVDS_TXU1+ 15
TXOUT_U2N B11 LVDS_TXU2- 15
8.37mA 1 2 C76 C16 C12
2.2U_0603_6.3V6M AVSSN TXOUT_U2P LVDS_TXU2+ 15
FBM-11-160808-121-T_0603 1 B12
L6 2 TXOUT_U3N LVDS_TXU3- 15
TXOUT_U3P A12 LVDS_TXU3+ 15
C77 C14
0.1U_0402_16V4Z AVDDDI
TXOUT_L0N D10 LVDS_TXL0- 15
2
D14 AVSSDI TXOUT_L0P C10 LVDS_TXL0+ 15
+1.8VDDQ G11
TXOUT_L1N LVDS_TXL1- 15
TXOUT_L1P F11 LVDS_TXL1+ 15
+1.8VS B14 E10
AVDDQ TXOUT_L2N LVDS_TXL2- 15
20.44mA E11 +1.8VS
TXOUT_L2P LVDS_TXL2+ 15
1 2 B15 AVSSQ TXOUT_L3N F12 LVDS_TXL3- 15
FBM-11-160808-121-T_0603 1 E12
L7 TXOUT_L3P LVDS_TXL3+ 15 +1.8VLPVDD 1 2
C78 +1.8PLLVDD H10 H12 1 1 R64 0_0603_5%
1U_0603_10V6K PLLVDD LPVDD_1
LPVDD_2 H13
2 PLLGND C79 C80
1 2 H9 PLLVSS LPVSS H11
FBM-11-160808-121-T_0603 0.1U_0402_16V4Z 1U_0603_10V6K
L5 +1.8V_LVDDR 2 2
LVDDR18A_1 B13
D3 TMDS_HPD LVDDR18A_2 C13 1 1
C C
C3 DDC_DATA 1 2
A13 C81 C82 FBM-11-160808-121-T_0603
LVDDR18D 1U_0603_10V6K 0.1U_0402_16V4Z L8
15,21 CRT_VSYNC# D9 DACVSYNC 2 2 +1.8V_LDDR18D
B8 1 2

DAC
15,21 CRT_HSYNC# DACHSYNC
D13 1 1 R65 0_0603_5%
LVSSR_1
1 2 RSET B16 RSET LVSSR_2 E13
R66 715_0603_1% E14 C83 C84
LVSSR_3 0.1U_0402_16V4Z 1U_0603_10V6K
15 CRT_R F16 RED 2 2
D16 B6 +3VS

CRT
15 CRT_G GREEN LVDS_DIGON ENVDD 15
A6 ENABLT
LVDS_BLON ENABLT 31
E16 D7 ENABLT
15 CRT_B BLUE LVDS_BLEN

1
1 2 TXCLK_UP G13 LVDS_TXUCLK+ 15

1
@ R67 49.9_0603_1% G12 R987
TXCLK_UN LVDS_TXUCLK- 15
B4 OSCIN D12 R1029 @ 4.7K_0402_5%
16 CLK_NB_14M TXCLK_LP LVDS_TXLCLK+ 15
D11 2K_0402_5%
TXCLK_LN LVDS_TXLCLK- 15

2
B2 SCL_STRAP
16 CLK_MCH_BCLK

2
CPU_CLKP
16 CLK_MCH_BCLK# C2 CPU_CLKN C E15 C/R_VGA 15

1
C

CLK.
D15 Q54 2 1 2

SVID
Y Y/G_VGA 15 B R998 SB_PWRGD# 21
1 2 C6 PMBT3904_SOT23 2K_0402_5%
R509 10K_0402_5% TVCLKIN E
F15 COMP/B_VGA 15

3
COMP_B
DACSCL:SCL_STRAP (DEFAULT=0 FOR MOBILE)
A4 C8 SCL_STRAP R69 2 1
OSCOUT DACSCL DAC_CLK 15
0_0402_5%
E8 R70 2 1
DACSDA DAC_DAT 15
0_0402_5%
15 LVDS_CLK A7 I2C_CLK
B B7 C7 STRAP_EEPROM B
15 LVDS_DAT I2C_DATA STRP_DATA STRAP_EEPROM 21,42

216DLP4AKA21G_BGA923_RS400MD

A A

Compal Electronics, Inc.


Title
SCHEMATIC, M/B LA-2642P
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401380 B

Date: 星期五, 七月 29, 2005 Sheet 11 of 48


5 4 3 2 1
A B C D E

+1.8V
1324.57mA
+1.8V
+1.2VMVCORE
U3G U3F 1 2
P3 AT16 PART 6 OF 7 AB29 C102 10U_0805_10V4Z~N
VSSA1 PART 7 OF 7 VSS107 +1.2VMVCORE VDD_MEM1
N3 VSSA2 VSS108 V16 AA14 VDD_CORE1 VDD_MEM2 AD29 1 2
T3 AB14 AA16 AD30 C103 10U_0805_10V4Z~N
VSSA3 VSS109 VDD_CORE2 VDD_MEM3
V3 VSSA4 VSS110 P20 1 2 AA18 VDD_CORE3 VDD_MEM4 AE29 1 2
Y3 R17 C172 150U_D2_6.3VM AA20 AF30 C104 10U_0805_10V4Z~N

+
VSSA5 VSS111 VDD_CORE4 VDD_MEM5
AA3 VSSA6 VSS112 T18 1 2 AA22 VDD_CORE5 VDD_MEM6 AH29 1 2
AC3 U17 C88 10U_0805_10V4Z~N AB15 AJ9 C106 10U_0805_10V4Z~N
VSSA7 VSS113 VDD_CORE6 VDD_MEM7
U3 VSSA8 VSS114 AB16 1 2 AB17 VDD_CORE7 VDD_MEM8 AJ10 1 2
AD3 W17 C108 10U_0805_10V4Z~N AB19 AJ12 C107 0.1U_0402_16V4Z
VSSA9 VSS115 VDD_CORE8 VDD_MEM9
1 E3 VSSA10 VSS116 Y16 1 2 AB21 VDD_CORE9 VDD_MEM10 AJ13 1 2 1
F3 AA17 C639 0.1U_0402_16V4Z AB23 AJ16 C89 0.1U_0402_16V4Z
VSSA11 VSS117 VDD_CORE10 VDD_MEM11
H3 VSSA12 VSS118 Y22 1 2 AC14 VDD_CORE11 VDD_MEM12 AJ17 1 2
K3 AC17 C635 0.1U_0402_16V4Z AC16 AJ20 C90 0.1U_0402_16V4Z
VSSA13 VSS119 VDD_CORE12 VDD_MEM13
L3 VSSA14 VSS120 AN18 1 2 AC18 VDD_CORE13 VDD_MEM14 AJ21 1 2
Y5 A19 C634 0.1U_0402_16V4Z AC20 AJ24 C91 0.1U_0402_16V4Z
VSSA15 VSS121 VDD_CORE14 VDD_MEM15
P5 VSSA16 VSS122 D20 1 2 AC22 VDD_CORE15 VDD_MEM16 AJ25 1 2
U5 AT2 C637 0.1U_0402_16V4Z P15 AJ28 C92 0.1U_0402_16V4Z
VSSA17 VSS123 VDD_CORE16 VDD_MEM17
L5 VSSA18 VSS124 G20 1 2 P17 VDD_CORE17 VDD_MEM18 AJ29 1 2
H5 P18 C636 0.1U_0402_16V4Z P19 AK9 C94 0.1U_0402_16V4Z
VSSA19 VSS125 VDD_CORE18 VDD_MEM19
E5 VSSA20 VSS126 R19 1 2 P21 VDD_CORE19 VDD_MEM20 AK12 1 2
AC5 T20 C95 0.1U_0402_16V4Z P23 AK16 C96 0.1U_0402_16V4Z

MEM I/F PWR


VSSA21 VSS127 VDD_CORE20 VDD_MEM21
AH3 VSSA22 VSS128 U19 1 2 R14 VDD_CORE21 VDD_MEM22 AK19 1 2
Y6 V18 C111 0.1U_0402_16V4Z R16 AK21 C97 0.1U_0402_16V4Z
VSSA23 VSS129 VDD_CORE22 VDD_MEM23
AC6 VSSA24 VSS130 AC21 1 2 R18 VDD_CORE23 VDD_MEM24 AK24 1 2

CORE POWER
U6 Y18 C98 0.1U_0402_16V4Z R20 AK29 C112 0.1U_0402_16V4Z
VSSA25 VSS131 VDD_CORE24 VDD_MEM25
P6 VSSA26 VSS132 Y20 1 2 R22 VDD_CORE25 VDD_MEM26 AL28 1 2
L6 AB18 C99 0.1U_0402_16V4Z T15 AT13 C113 0.1U_0402_16V4Z
VSSA27 VSS133 VDD_CORE26 VDD_MEM27
H6 VSSA28 VSS134 AC19 1 2 T17 VDD_CORE27 VDD_MEM28 AT15 1 2
E6 AT19 C114 0.1U_0402_16V4Z T19 AT18 C115 0.1U_0402_16V4Z
VSSA29 VSS135 VDD_CORE28 VDD_MEM29
AA7 VSSA30 VSS136 H20 1 2 T21 VDD_CORE29 VDD_MEM30 AT24 1 2
AC8 AA19 C116 0.1U_0402_16V4Z T23 AT30 C117 0.1U_0402_16V4Z
VSSA31 VSS137 VDD_CORE30 VDD_MEM31
AG8 VSSA32 VSS138 W19 1 2 U14 VDD_CORE31 VDD_MEM32 AT34 1 2
N8 H15 C118 0.1U_0402_16V4Z U16 T29 C119 0.1U_0402_16V4Z
VSSA33 VSS139 VDD_CORE32 VDD_MEM33
R8 VSSA34 VSS140 H21 1 2 U18 VDD_CORE33 VDD_MEM34 U29 1 2
U8 V20 C120 0.1U_0402_16V4Z U20 W29 C121 0.1U_0402_16V4Z

POWER
VSSA35 VSS141 VDD_CORE34 VDD_MEM35
AE7 VSSA36 VSS142 AA21 1 2 U22 VDD_CORE35 VDD_MEM36 Y29 1 2
L7 AN21 C100 0.1U_0402_16V4Z V15 Y30 C122 0.1U_0402_16V4Z
VSSA37 VSS143 VDD_CORE36 VDD_MEM37
AG7 A22 1 2 V17 AK13
R7
VSSA38
VSSA39
GND VSS144
VSS145 G15 C101 0.1U_0402_16V4Z V19
VDD_CORE37
VDD_CORE38
VDD_MEM38
+VCCP
U7 G8 1 2 V21 A16 +VCCP 19.1mA
VSSA40 VSS146 C123 0.1U_0402_16V4Z VDD_CORE39 VDD_CPU1
W7 VSSA41 VSS147 AB20 V23 VDD_CORE40 VDD_CPU2 F17
2 2
AC7 VSSA42 VSS148 W21 W14 VDD_CORE41 VDD_CPU3 F18 1 2
AH7 V22 W16 G16 C124 10U_0805_10V4Z~N
VSSA43 VSS149 VDD_CORE42 VDD_CPU4
N7 VSSA44 VSS150 AB22 W18 VDD_CORE43 VDD_CPU5 G17 1 2
J7 AJ23 +1.2VSA W20 G18 C125 10U_0805_10V4Z~N
VSSA45 VSS151 VDD_CORE44 VDD_CPU6
AA8 VSSA46 VSS152 D23 W22 VDD_CORE45 VDD_CPU7 G19 1 2
J8 G26 1 2 Y15 G23 C127 0.1U_0402_16V4Z
VSSA47 VSS153 @ C1020 22U_1206_6.3V6M VDD_CORE46 VDD_CPU8
AE8 VSSA48 VSS154 AN24 Y17 VDD_CORE47 VDD_CPU9 H16 1 2
L8 A25 1 2 Y19 H17 C129 0.1U_0402_16V4Z
VSSA49 VSS155 C1014 22U_1206_6.3V6M VDD_CORE48 VDD_CPU10
W8 VSSA50 VSS156 AT25 Y21 VDD_CORE49 VDD_CPU11 H18 1 2
G3 AJ26 1 2 1082.42mA Y23 H19 C131 0.1U_0402_16V4Z
VSSA51 VSS157 C126 10U_0805_10V4Z~N VDD_CORE50 VDD_CPU12
AE6 G27 H23 1 2

CPU I/F PWR


VSSA52 VSS158 +1.2VSA VDD_CPU13 C133 0.1U_0402_16V4Z
AF4 VSSA53 VSS159 AN27 1 2 +1.2VS 1 2 A3 VDDA12_1 VDD_CPU14 H24
AF5 A28 C128 10U_0805_10V4Z~N BLM21P300S_0805 L9 AB7 H25 1 2
VSSA54 VSS160 BLM21P300S: 3Amp. VDDA12_2 VDD_CPU15 C135 0.1U_0402_16V4Z
VSS161 D26 1 2 AB8 VDDA12_3 VDD_CPU16 J29
E9 M30 C130 1U_0402_6.3V4Z AD7 J30 1 2
VSS55 VSS162 VDDA12_4 VDD_CPU17 C137 0.1U_0402_16V4Z
AN4 VSS56 VSS163 R30 1 2 AD8 VDDA12_5 VDD_CPU18 K29
AC15 R29 C132 1U_0402_6.3V4Z B3 L29 1 2
VSS57 VSS164 VDDA12_6 VDD_CPU19 C139 0.1U_0402_16V4Z
AN6 VSS58 VSS165 AG29 1 2 C4 VDDA12_7 VDD_CPU20 L30
C134 1U_0402_6.3V4Z

PCIE PWR
AT6 VSS59 VSS166 V29 C5 VDDA12_8 VDD_CPU21 N29 1 2
AJ14 AA29 1 2 D6 P29 C141 0.1U_0402_16V4Z
VSS60 VSS167 C136 1U_0402_6.3V4Z VDDA12_9 VDD_CPU22
AC23 VSS61 VSS168 V32 E7 VDDA12_10 VDD_CPU23 P30 1 2
D8 AK22 1 2 F7 C143 0.1U_0402_16V4Z
VSS62 VSS169 C138 1U_0402_6.3V4Z VDDA12_11
AH8 VSS63 VSS170 AG30 H7 VDDA12_12 1 2
AJ8 AJ30 1 2 H8 AF7 +1.8VSA C145 0.1U_0402_16V4Z
VSS64 VSS171 C140 1U_0402_6.3V4Z VDDA12_13 VDDA18_1
AN9 VSS65 VSS172 AK25 K7 VDDA12_14 VDDA18_2 AF8 1 2
AT10 V30 1 2 K8 AH4 C147 0.1U_0402_16V4Z

PCIE I/O PWR


VSS66 VSS173 C142 1U_0402_6.3V4Z VDDA12_15 VDDA18_3
AK10 VSS67 VSS174 AA30 M7 VDDA12_16 VDDA18_4 AH5 1 2
AJ11 AJ22 1 2 M8 AG6 C149 0.1U_0402_16V4Z
VSS68 VSS175 C144 1U_0402_6.3V4Z VDDA12_17 VDDA18_5
AJ15 VSS69 VSS176 AJ19 T7 VDDA12_18 VDDA18_6 P7
AK15 AN30 1 2 T8 P8 +1.8VS
VSS70 VSS177 C146 1U_0402_6.3V4Z VDDA12_19 VDDA18_7
AN12 VSS71 VSS178 A31 V7 VDDA12_20 VDDA18_8 Y7
3 AT12 D30 1 2 V8 Y8 1 2 72.9mA 3
VSS72 VSS179 C148 1U_0402_6.3V4Z VDDA12_21 VDDA18_9 FBM-11-160808-121-T_0603
VSS180 M29
AA15 AJ27 1 2 AH9 J9 L10 FBM-11-160808-121-T_0603: 300mA
VSS74 VSS181 C150 1U_0402_6.3V4Z VDD_18_1 VDD_18_3
W23 VSS75 VSS182 AK28 AH28 VDD_18_2 VDD_18_4 J28
V14 VSS76 VSS183 AJ18
AA23 AK18 109.95mA 216DLP4AKA21G_BGA923_RS400MD
VSS77 VSS184 0_0603_5%
AM15 VSS78 VSS185 AF29
A15 AC29 +1.8VS
VSS79 VSS186 R74
Y14 VSS80 VSS187 AC30
W15 AK33 1 2 +1.8VS_VDD
VSS81 VSS188
A35 VSS82 VSS189 AT31 1 1 1 1
B36 VSS83 VSS190 D33
F36 F33 D3B C151
VSS84 VSS191 1U_0402_6.3V4Z
J36 VSS85 VSS192 J33 4
+3VSD 3 2 2 2 2 C154
M36 VSS86 VSS193 M33
T34 R33 5 1U_0402_6.3V4Z 1
VSS87 VSS194 C152 C153
W36 VSS88 VSS195 V33 1 1 1 1
AB36 AA32 BAV99DW-7-F_SOT363~N 1U_0402_6.3V4Z 1U_0402_6.3V4Z +
VSS89 VSS196 C155 C159
AD36 VSS90 VSS197 AD33
AH36 AG33 D3A 47U_D2_6.3VM 1U_0402_6.3V4Z
VSS91 VSS198 2 2 2 2 2
AL36 VSS92 VSS199 AJ31 2
AR36 VSS93 VSS200 AN33 6
H29 AT35 +3VS 1 C156
VSS94 VSS201 1U_0402_6.3V4Z
H30 VSS95 VSS202 AJ5
A2 G14 BAV99DW-7-F_SOT363~N C158
VSS96 VSS203 C157 1U_0402_6.3V4Z
F14 VSS97 VSS204 G9
H14 AR1 1U_0402_6.3V4Z
VSS98 VSS205
AK6 VSS99 VSS206 B1
R21 VSS100 VSS207 G22
R23 VSS101 VSS208 H22
U21 VSS102 VSS209 U15
4 U23 VSS103 VSS210 T16 4
P14 VSS104 VSS211 R15
P22 VSS105 VSS212 P16
T14 VSS106 VSS213 T22

216DLP4AKA21G_BGA923_RS400MD
Compal Electronics, Inc.
Title
SCHEMATIC, M/B LA-2642P
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401380 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: 星期五, 七月 29, 2005 Sheet 12 of 48
A B C D E
A B C D E F G H

10 DDR_A_DQS#[0..7]

10 DDR_A_D[0..63]
+1.8V +1.8V
10 DDR_A_DM[0..7] Trace=20mil
V_DDR_MCH_REF
10 DDR_A_MA[0..13] V_DDR_MCH_REF 14
JDIM2
10 DDR_A_DQS[0..7] 1 VREF VSS 2
Layout Note: DD R_A_D8
3 VSS DQ4 4 DDR_A_D12
DD R_A_D9
5 6
Place near JDIM1 DDR_A_D13 7
DQ0 DQ5
8
DQ1 VSS DDR_A_DM1
9 VSS DM0 10
DDR_A_DQS#1 11 12
DDR_A_DQS1 DQS0# VSS DDR_A_D15
13 DQS0 DQ6 14
+1.8V 15 16 DDR_A_D11
DDR_A_D10 VSS DQ7
1
17 DQ2 VSS 18 1
DDR_A_D14 19 20 DDR_A_D17
DQ3 DQ12 DDR_A_D21
21 VSS DQ13 22

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
1 DDR_A_D20 23 24
DDR_A_D16 DQ8 VSS DDR_A_DM2
1 1 1 1 1 1 1 1 1 25 DQ9 DM1 26

C162

C163

C164

C168

C169

C173

C174

C167

C629
+ 27 28
C170 DDR_A_DQS#2 VSS VSS DDR_A_CLK1
29 DQS1# CK0 30 DDR_A_CLK1 10
470U_D2_2.5VM DDR_A_DQS2 31 32 DDR_A_CLK1#
2 2 2 2 2 2 2 2 2 2 DQS1 CK0# DDR_A_CLK1# 10
33 VSS VSS 34
DDR_A_D23 35 36 DDR_A_D18
DDR_A_D22 DQ10 DQ14 DDR_A_D19
37 DQ11 DQ15 38
39 VSS VSS 40

41 VSS VSS 42
DD R_A_D1 43 44 DD R_A_D5
DD R_A_D4 DQ16 DQ20 DD R_A_D0
45 DQ17 DQ21 46
47 VSS VSS 48
DDR_A_DQS#0 49 50
DDR_A_DQS0 DQS2# NC DDR_A_DM0
51 DQS2 DM2 52
@ DDR_A_CLK0 @ DDR_A_CLK1 53 54
VSS VSS
10P_0402_50V8J

10P_0402_50V8J
DD R_A_D6 55 56 DD R_A_D7
DD R_A_D2 DQ18 DQ22 DD R_A_D3
1 1 57 DQ19 DQ23 58
C165 C166 59 60
DDR_A_D29 VSS VSS DDR_A_D24
61 DQ24 DQ28 62
DDR_A_D28 63 64 DDR_A_D25
2 2 DQ25 DQ29
65 VSS VSS 66
DDR_A_CLK0# DDR_A_CLK1# DDR_A_DM3 67 68 DDR_A_DQS#3
DM3 DQS3# DDR_A_DQS3
69 NC DQS3 70
71 VSS VSS 72
DDR_A_D30 73 74 DDR_A_D31
DDR_A_D26 DQ26 DQ30 DDR_A_D27
75 DQ27 DQ31 76
Layout Note: DDR_A_CKE0
77 VSS VSS 78
DDR_A_CKE1
79 80
Place one cap close to every 2 pullup 10 DDR_A_CKE0
81
CKE0 NC/CKE1
82
DDR_A_CKE1 10
VDD VDD
resistors terminated to V_DDR_MCH_REF 83 NC NC/A15 84
10 DDR_A_MA17 85 BA2 NC/A14 86
87 VDD VDD 88
2 DDR_A_MA12 89 90 DDR_A_MA11 2
DDR_A_MA9 A12 A11 DDR_A_MA7
91 A9 A7 92
DDR_A_MA8 93 94 DDR_A_MA6
A8 A6
95 VDD VDD 96
DDR_A_MA5 97 98 DDR_A_MA4
DDR_A_MA3 A5 A4 DDR_A_MA2
99 A3 A2 100
+0.9VS DDR_A_MA1 101 102 DDR_A_MA0
A1 A0
103 VDD VDD 104
DDR_A_MA10 105 106 DDR_A_MA16
A10/AP BA1 DDR_A_MA16 10
107 108 DDR_A_RAS#
10 DDR_A_MA15 BA0 RAS# DDR_A_RAS# 10
DDR_A_WE# 109 110 DDR_A_CS0#
10 DDR_A_WE# WE# S0# DDR_A_CS0# 10
111 VDD VDD 112
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

DDR_A_CAS# 113 114 DDR_A_ODT0


10 DDR_A_CAS# CAS# ODT0 DDR_A_ODT0 10
DDR_A_CS1# 115 116 DDR_A_MA13
10 DDR_A_CS1# NC/S1# NC/A13
1 1 1 1 1 1 1 1 1 1 1 1 1 117 VDD VDD 118
DDR_A_ODT1 119 120
NC/ODT1 NC
121 VSS VSS 122

1
DDR_A_D32 123 124 DDR_A_D36
2 2 2 2 2 2 2 2 2 2 2 2 2 R1045 DDR_A_D33 DQ32 DQ36 DDR_A_D37
125 DQ33 DQ37 126
C176

C177

C178

C179

C180

C181

C182

C183

C184

C185

C186

C187

C188

0_0402_5% 127 128


DDR_A_DQS#4 VSS VSS DDR_A_DM4
129 DQS4# DM4 130
DDR_A_DQS4 131 132

2
DQS4 VSS DDR_A_D35
133 VSS DQ38 134
DDR_A_D39 135 136 DDR_A_D34
DDR_A_D38 DQ34 DQ39
137 DQ35 VSS 138
139 140 DDR_A_D45
DDR_A_D40 VSS DQ44 DDR_A_D41
141 DQ40 DQ45 142
DDR_A_D44 143 144
DQ41 VSS DDR_A_DQS#5
145 VSS DQS5# 146
DDR_A_DM5 147 148 DDR_A_DQS5
DM5 DQS5
149 VSS VSS 150
DDR_A_D46 151 152 DDR_A_D47
DDR_A_D42 DQ42 DQ46 DDR_A_D43
153 DQ43 DQ47 154
155 VSS VSS 156
DDR_A_D52 157 158 DDR_A_D53
DDR_A_D48 DQ48 DQ52 DDR_A_D49
159 DQ49 DQ53 160
161 VSS VSS 162
163 164 DDR_A_CLK0
3 NC,TEST CK1 DDR_A_CLK0 10 3
165 166 DDR_A_CLK0#
VSS CK1# DDR_A_CLK0# 10
DDR_A_DQS#6 167 168
DDR_A_DQS6 DQS6# VSS DDR_A_DM6
169 DQS6 DM6 170
171 VSS VSS 172
DDR_A_D54 173 174 DDR_A_D50
DDR_A_D55 DQ50 DQ54 DDR_A_D51
175 DQ51 DQ55 176
177 VSS VSS 178
DDR_A_D60 179 180 DDR_A_D61
DDR_A_D56 DQ56 DQ60 DDR_A_D57
181 DQ57 DQ61 182
183 VSS VSS 184
DDR_A_DM7 185 186 DDR_A_DQS#7
+0.9VS DM7 DQS7# DDR_A_DQS7
187 VSS DQS7 188
DDR_A_D62 189 190
DDR_A_D58 DQ58 VSS DDR_A_D63
191 DQ59 DQ62 192
RP1 RP2 193 194 DDR_A_D59
DDR_A_MA5 DDR_A_MA17 VSS DQ63
1 4 4 1 14,16,18,26 SB_SMDATA 195 SDA VSS 196
DDR_A_MA8 2 3 3 2 DDR_A_CKE0 197 198
14,16,18,26 SB_SMCLK SCL SAO
+3VS 199 VDDSPD SA1 200
56_0404_4P2R_5% 56_0404_4P2R_5%

2
0.1U_0402_16V4Z

2.2U_0805_10V6K

10K_0402_5%

10K_0402_5%
RP5 RP3

R76
DDR_A_MA1 1 4 4 1 DDR_A_MA7 1 1 FOX_ASOA426-M2R-TR

R75
C190

DDR_A_MA3 C189
2 3 3 2 DDR_A_MA6

DIMMA
56_0404_4P2R_5% 56_0404_4P2R_5%

1
2 2
RP4 RP6 Layout Note:
Reverse
DDR_A_RAS# 1 DDR_A_MA9
DDR_A_CS0#
1 4 4 Place these resistor
2 3 3 2 DDR_A_MA12
closely JDIM2,all
56_0404_4P2R_5% 56_0404_4P2R_5% trace length<750 mil
RP7 RP8
DDR_A_MA15 1 4 4 1 DDR_A_MA4
DDR_A_MA10 2 3 3 2 DDR_A_MA2

56_0404_4P2R_5% 56_0404_4P2R_5%
RP9 RP10
DDR_A_CAS# 1 4 4 1 DDR_A_MA0
DDR_A_WE# 2 3 3 2 DDR_A_MA16
4 4
56_0404_4P2R_5% 56_0404_4P2R_5%
RP11
4 1 DDR_A_ODT0
3 2 DDR_A_MA13

56_0404_4P2R_5%

RP12 RP13 Layout Note:


DDR_A_CKE1
DDR_A_CS1#
1 4 4 1
DDR_A_MA11
Place these resistor
2 3 3 2
closely JDIM2,all Compal Electronics, Inc.
56_0404_4P2R_5% 56_0404_4P2R_5% trace length Max=1.3" Title
SCHEMATIC, M/B LA-2642P
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
401380 B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: 星期五 , 七月 29, 2005 Sheet 13 of 48
A B C D E F G H
A B C D E

+1.8V +1.8V
Trace=20mil
10 DDR_B_DQS#[0..7]
V_DDR_MCH_REF
V_DDR_MCH_REF 13
+1.8V
10 DDR_B_D[0..63]
JDIM1
10 DDR_B_DM[0..7] 1 VREF VSS 2
3 4 DD R_B_D1
DD R_B_D0 VSS DQ4 DD R_B_D4
10 DDR_B_DQS[0..7] 5 DQ0 DQ5 6
Layout Note: DD R_B_D5 7 DQ1 VSS 8

1
9 10 DDR_B_DM0 1
10 DDR_B_MA[0..13] Place near JDIM2 DDR_B_DQS#0 11
VSS DM0
12 R473
DDR_B_DQS0 DQS0# VSS DD R_B_D7 1K_0402_5% C902
13 DQS0 DQ6 14
15 16 DD R_B_D3 0.1U_0402_16V4Z
DD R_B_D2 VSS DQ7 2
17 18

2
+1.8V DD R_B_D6 DQ2 VSS DD R_B_D9
19 DQ3 DQ12 20
21 22 DDR_B_D13 V_DDR_MCH_REF
DDR_B_D12 VSS DQ13
23 DQ8 VSS 24

1
1 1

0.1U_0402_16V4Z
DD R_B_D8 25 26 DDR_B_DM1 1
DQ9 DM1
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
1 27 28 R474
DDR_B_DQS#1 VSS VSS DDR_B_CLK1 1K_0402_5% C903
1 1 1 1 1 1 1 1 1 29 DQS1# CK0 30 DDR_B_CLK1 10
C192

C200

C193

C194

C201

C196

C197

C198

C630
+ DDR_B_DQS1 31 32 DDR_B_CLK1# 0.1U_0402_16V4Z
DQS1 CK0# DDR_B_CLK1# 10 2
C171 33 34

2
470U_D2_2.5VM DDR_B_D14 VSS VSS DDR_B_D10
35 DQ10 DQ14 36
2 2 2 2 2 2 2 2 2 2 DDR_B_D15 DDR_B_D11
37 DQ11 DQ15 38
39 VSS VSS 40

41 VSS VSS 42
DDR_B_D17 43 44 DDR_B_D21
DDR_B_D20 DQ16 DQ20 DDR_B_D16
45 DQ17 DQ21 46
47 VSS VSS 48
DDR_B_DQS#2 49 50
DDR_B_DQS2 DQS2# NC DDR_B_DM2
51 DQS2 DM2 52
53 VSS VSS 54
@ DDR_B_CLK0 @ DDR_B_CLK1 DDR_B_D22 DDR_B_D18
55 DQ18 DQ22 56
10P_0402_50V8J

10P_0402_50V8J DDR_B_D23 DDR_B_D19


57 DQ19 DQ23 58
1 1 59 VSS VSS 60
C202 C195 DDR_B_D28 61 62 DDR_B_D25
DDR_B_D29 DQ24 DQ28 DDR_B_D24
63 DQ25 DQ29 64
65 VSS VSS 66
2 2 DDR_B_DM3 DDR_B_DQS#3
67 DM3 DQS3# 68
DDR_B_CLK0# DDR_B_CLK1# 69 70 DDR_B_DQS3
NC DQS3
71 VSS VSS 72
DDR_B_D26 73 74 DDR_B_D31
DDR_B_D30 DQ26 DQ30 DDR_B_D27
75 DQ27 DQ31 76
77 VSS VSS 78
DDR_B_CKE0 79 80 DDR_B_CKE1
10 DDR_B_CKE0 CKE0 NC/CKE1 DDR_B_CKE1 10
81 VDD VDD 82
Layout Note: DDR_B_MA17
83 NC NC/A15 84
85 86
Place one cap close to every 2 pullup 10 DDR_B_MA17
87
BA2 NC/A14
88
VDD VDD
resistors terminated to V_DDR_MCH_REF DDR_B_MA12
DDR_B_MA9
89 A12 A11 90 DDR_B_MA11
DDR_B_MA7
91 A9 A7 92
DDR_B_MA8 93 94 DDR_B_MA6
A8 A6
2 95 VDD VDD 96 2
DDR_B_MA5 97 98 DDR_B_MA4
DDR_B_MA3 A5 A4 DDR_B_MA2
99 A3 A2 100
DDR_B_MA1 101 102 DDR_B_MA0
A1 A0
103 VDD VDD 104
DDR_B_MA10 105 106 DDR_B_MA16 DDR_B_MA16 10
+0.9VS DDR_B_MA15 A10/AP BA1 DDR_B_RAS#
10 DDR_B_MA15 107 BA0 RAS# 108 DDR_B_RAS# 10
DDR_B_WE# 109 110 DDR_B_CS0#
10 DDR_B_WE# WE# S0# DDR_B_CS0# 10
111 VDD VDD 112
DDR_B_CAS# 113 114 DDR_B_ODT0
10 DDR_B_CAS# CAS# ODT0 DDR_B_ODT0 10
DDR_B_CS1# 115 116 DDR_B_MA13
10 DDR_B_CS1# NC/S1# NC/A13
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

117 VDD VDD 118


DDR_B_ODT1 119 120
NC/ODT1 NC
1 1 1 1 1 1 1 1 1 1 1 1 1 121 VSS VSS 122
DDR_B_D36 123 124 DDR_B_D33
DQ32 DQ36

1
DDR_B_D38 125 126 DDR_B_D34
R1046 DQ33 DQ37
127 VSS VSS 128
2 2 2 2 2 2 2 2 2 2 2 2 2 0_0402_5% DDR_B_DQS#4 DDR_B_DM4
129 DQS4# DM4 130
C207

C208

C209

C210

C211

C212

C213

C214

C215

C216

C217

C218

C219

DDR_B_DQS4 131 132


DQS4 VSS DDR_B_D37
133 134

2
DDR_B_D32 VSS DQ38 DDR_B_D39
135 DQ34 DQ39 136
DDR_B_D35 137 138
DQ35 VSS DDR_B_D40
139 VSS DQ44 140
DDR_B_D41 141 142 DDR_B_D44
DDR_B_D45 DQ40 DQ45
143 DQ41 VSS 144
145 146 DDR_B_DQS#5
DDR_B_DM5 VSS DQS5# DDR_B_DQS5
147 DM5 DQS5 148
149 VSS VSS 150
DDR_B_D47 151 152 DDR_B_D42
DDR_B_D46 DQ42 DQ46 DDR_B_D43
153 DQ43 DQ47 154
155 VSS VSS 156
DDR_B_D54 157 158 DDR_B_D48
DDR_B_D52 DQ48 DQ52 DDR_B_D53
159 DQ49 DQ53 160
161 VSS VSS 162
163 164 DDR_B_CLK0
NC,TEST CK1 DDR_B_CLK0 10
165 166 DDR_B_CLK0#
VSS CK1# DDR_B_CLK0# 10
DDR_B_DQS#6 167 168
DDR_B_DQS6 DQS6# VSS DDR_B_DM6
3
169 DQS6 DM6 170 3
171 VSS VSS 172
DDR_B_D55 173 174 DDR_B_D50
DDR_B_D49 DQ50 DQ54 DDR_B_D51
175 DQ51 DQ55 176
177 VSS VSS 178
DDR_B_D57 179 180 DDR_B_D61
DDR_B_D60 DQ56 DQ60 DDR_B_D56
181 DQ57 DQ61 182
183 VSS VSS 184
DDR_B_DM7 185 186 DDR_B_DQS#7
DM7 DQS7# DDR_B_DQS7
187 VSS DQS7 188
DDR_B_D62 189 190
+0.9VS DDR_B_D58 DQ58 VSS DDR_B_D63
191 DQ59 DQ62 192
193 194 DDR_B_D59
VSS DQ63 +3VS
RP14 RP15 13,16,18,26 SB_SMDATA 195 196
DDR_B_MA1 DDR_B_MA9 SDA VSS R78
1 4 4 1 13,16,18,26 SB_SMCLK 197 SCL SA0 198
DDR_B_MA3 2 3 3 2 DDR_B_MA12 +3VS 199 200 1 2
VDDSPD SA1

10K_0402_5%
56_0404_4P2R_5% 56_0404_4P2R_5% 10K_0402_5%

1
0.1U_0402_16V4Z

2.2U_0805_10V6K

RP17 RP16 TYCO_1720800-2

R77
DDR_B_MA15 1 4 4 1 DDR_B_CKE1 1 1
C220

C221

DDR_B_MA10 2 3 3 2 DDR_B_MA11

56_0404_4P2R_5% 56_0404_4P2R_5% DIMMB

2
2 2
DDR_B_MA0
DDR_B_MA16
1
RP18
4 4
RP19
1 DDR_B_MA5
DDR_B_MA8
Layout Note: Standar
2 3 3 2 Place these resistor
56_0404_4P2R_5% 56_0404_4P2R_5% closely JDIM1,all
RP20 RP21 trace length<750 mil
DDR_B_RAS# 1 4 4 1 DDR_B_MA7
DDR_B_CS0# 2 3 3 2 DDR_B_MA6

56_0404_4P2R_5% 56_0404_4P2R_5%
RP22 RP23
DDR_B_MA4 1 4 4 1 DDR_B_ODT0
DDR_B_MA2 2 3 3 2 DDR_B_MA13

56_0404_4P2R_5% 56_0404_4P2R_5%
4 RP24 4
DDR_B_CAS# 1 4
DDR_B_WE# 2 3

56_0404_4P2R_5%

RP25 RP26 Layout Note:


DDR_B_MA17
DDR_B_CS1#
1 4 4 1
DDR_B_CKE0
Place these resistor
2 3 3 2
closely JDIM1,all Compal Electronics, Inc.
56_0404_4P2R_5% 56_0404_4P2R_5% trace length Title
Max=1.3" SCHEMATIC, M/B LA-2642P
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401380
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: 星期五 , 七月 29, 2005 Sheet 14 of 48
A B C D E
A B C D E

C/R_VGA 1 2
11 C/R_VGA
L11

1
1 CHB1608B121_0603

1
R79
75_0402_1% C222 C223 TV-OUT Connector
82P_0402_50V8J 82P_0402_50V8J

2
2 JTV1

2
SVIDEO_C 7
6
Y/G_VGA SVIDEO_Y 5
11 Y/G_VGA 1 2 4
L12
3

1
1 1 CHB1608B121_0603 SVIDEO_COMP/B 1
2

1
R80
75_0402_1% C224 C225 1
82P_0402_50V8J 82P_0402_50V8J SUYIN_030107FR007T115ZR~N

1
2

2
D6 D5 D7

COMP/B_VGA 1 2
11 COMP/B_VGA
L13

3
1
CHB1608B121_0603 +3VS
1

1
R81
75_0402_1% C226 C227
82P_0402_50V8J 82P_0402_50V8J @ DAN217_SC59 @ DAN217_SC59 @ DAN217_SC59

2
2

2
Inverter Pin Define LVDS from NB
1 INV_PWR
PANEL +LCDVDD CTRL CKT 2 INV_PWR
B+ JLVDS1
3 INV_PWM LVDS_TXU2- 11
C907 1 1 21
2 0.1U_0603_50V4Z 2 22
+LCDVDD +5VALW 4 DISOFF# DISPOFF#
3 23 LVDS_TXU2+ 11
W to B Pin Define 1 2 68P_0402_50V8K LVDS_TXL0- 11
+3VS 5 DAC_BRIG C908 INVT_PWM 4 24
31 INVT_PWM 5 25
1

R82 B+ 1 2 B+
2 31 DAC_BRIG 6 26 LVDS_TXL0+ 11 2
R83 DISPOFF# 3 4 GND 6 GND EDID_DAT
7 27 LVDS_TXU3- 11
INVT_PWM 5 6 DAC_BRIG EDID_CLK
8 28
300_0402_5% 100K_0402_5% 80mil C228 EDID_DAT 7 8 EDID_CLK 7 GND 11 LVDS_TXU0- 9 29 LVDS_TXU3+ 11
UTX0- 9 10 GND LVDS_TXLCLK- 11
1 2

4.7U_0805_10V4Z UTX0+ 11 12 LTX1- 10 30


11 LVDS_TXU0+ 11 31
3

D 10K_0402_5% Q6 GND 13 14 LTX1+


S 11 LVDS_TXL1- 12 32 LVDS_TXLCLK+ 11
Q52 1 2 2 UTX1- 15 16 GND
13 33 LVDS_TXUCLK- 11
2N7002_SOT23
G R85 2 G AO3401L_SOT23 UTX1+ 17 18 LTX2- 11 LVDS_TXL1+ 14 34 +LCDVDD
0.01U_0402_16V7K

S GND 19 20 LTX2+ 11 LVDS_TXU1- LVDS_TXUCLK+ 11


3

D
UTX2- 21 22 GND 15 35
16 36 LVDS_TXL3- 11
+LCDVDD UTX2+ 23 24 LTX0- 11 LVDS_TXU1+
1

17 37
1

D 1 C231
80mil GND 25 26 LTX0+ 11 LVDS_TXL2- 18 38 LVDS_TXL3+ 11
ENVDD 2 Q7 UTX3- 27 28 GND +3VS 1 2EDID_DAT 1 2
11 ENVDD 19 39
G 2N7002_SOT23 UTX3+ 29 30 LCLK- 10K_0402_5% R87 @ R504 10K_0402_5% +3VS
11 LVDS_TXL2+ 20 40
S 1 GND 31 32 LCLK+ 1 2
3

C232 C233 UCLK- 33 34 GND 1 2EDID_CLK 1 2 JST_BM40B-SRDS-G


UCLK+ 35 36 LTX3- 10K_0402_5% R88 @ R505 10K_0402_5% C1011 C229
1 2 0.1U_0402_16V4Z LCDVDD 37 38 LTX3+ 0.1U_0402_16V4Z
R86 10K_0402_5% 2 LCDVDD 39 40 +3VS 2 1
11 LVDS_DAT 1 2
R506 0_0402_5% +3VS 1 2
4.7U_0805_10V4Z 1 2 R84 10K_0402_5% @ 4.7U_0805_10V4Z
11 LVDS_CLK C230
R507 0_0402_5%
1 2 DISPOFF# 1 2
31 BKOFF#
D8 CH751H-40_SC76 220P_0402_50V7K

CRT CONNECTOR
3 D9 D10 D11 3
@ DAN217_SOT23 @ DAN217_SOT23 @ DAN217_SOT23 +5VS D12 +CRT_VCCF +CRT_VCC
F1
1

2 1 1 2

1.1A_6VDC_FUSE 1
+5VS RB751V_SOD323 C234

0.1U_0402_16V4Z JP4.18&19 will connect to GND by Layout.


2

2
11 CRT_R
JP4
75_0402_1% R89 6
2 1 11
1 L14 2 CRTR 1
FCM2012C-800_0805 7
11 CRT_G
12
75_0402_1% R90 1 L15 2 CRTG 2
2 1 FCM2012C-800_0805 8 +CRT_VCC +CRT_VCC +3VS +3VS +3VS
13
1 L16 2 CRTB 3
11 CRT_B

2
FCM2012C-800_0805 9

2K_0402_5%

2K_0402_5%

4.7K_0402_5%

4.7K_0402_5%
75_0402_1% R91 1 1 1 1 1 1 14 16 R92 R93 R95 R96
3.3P_0402_50V8C~N

3.3P_0402_50V8C~N

3.3P_0402_50V8C~N

2 1 C235 C236 C237 C238 C239 C240 4 17


1 10
15

1
2 2 2 2 2 2 C241 5
3.3P_0402_50V8C~N

2
3.3P_0402_50V8C~N 2

G
+CRT_VCC 3.3P_0402_50V8C~N L17 FOX_DZ11A91-NL201-AF~N Q8
C242
HSY NC# 1 2 CRTHSYNC# 1 3 2N7002_SOT23 DAC_DAT 11
1 2 CHB1608U301_0603 100P_0402_50V8J

2
L18

G
4 4
5

0.1U_0402_16V4Z U4 1 2 CRTVSYNC# Q9
R97 CHB1608U301_0603 1 1 1 1 1 3 2N7002_SOT23
OE#
P

DAC_CLK 11
2 4 1 2 +CRT_VCC 1K_0402_5% C245

S
11,21 CRT_HSYNC# A Y R1023 C247
VSYNC#

0_0402_5% C244 C246


G

1 2 27P_0402_50V8J 27P_0402_50V8J
1

SN74AHCT1G125DCKR_SC70-5 C243 2 2 2 2 100P_0402_50V8J


3

U5
0.1U_0402_16V4Z Compal Electronics, Inc.
OE#
P

2 A 4 1 2 100P_0402_50V8J Title
11,21 CRT_VSYNC# Y R1022 0_0402_5%
SCHEMATIC, M/B LA-2642P
G

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SN74AHCT1G125DCKR_SC70-5 Size Document Number R ev
3

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401380 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: 星期五, 七月 29, 2005 Sheet 15 of 48
A B C D E
A B C D E

Clock Generator

2
49.9_0402_1%

49.9_0402_1%

49.9_0402_1%

49.9_0402_1%

49.9_0402_1%

49.9_0402_1%
R98

R99

R100

R101

R102

R103
+CLK_VDD1 U6

1
L19
1 +3VS 1 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 45 47 CPUCLKT0 R109 1 2 33_0402_5% 1
CHB2012U121_0805 VDDCPU CPUCLKT0 CPUCLKC0 R104 33_0402_5% CLK_MCH_BCLK 11
1 1 1 1 1 1 1 1 51 VDDPCI CPUCLKC0 46 1 2 CLK_MCH_BCLK# 11
C256 C248 C249 C257 C250 C252 C258 32 43 CPUCLKT1 R105 1 2 33_0402_5%
VDDATI CPUCLKT1 CPUCLKC1 R110 33_0402_5% CLK_CPU_BCLK 6
35 VDDSRC CPUCLKC1 42 1 2 CLK_CPU_BCLK# 6
10U_0805_10V4Z~N C251 14 41 CPUCLKT2 R111 1 2 33_0402_5%
2 2 2 2 2 2 2 2 VDDSRC CPUCLKT2_ITP CPUCLKC2 R106 33_0402_5% CLK_ITP_BCLK 6
21 VDDSRC CPUCLKC2_ITP 40 1 2 CLK_ITP_BCLK# 6
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 3 VDD48
56 VDDREF
+3VS 1 2 +VDDA_CLK 39
L20 CHB1608U301_0603 VDDA SRCCLKT0 R108 1
SRCCLKT0 34 2 33_0402_5% CLK_A_SB 17
33 SRCCLKC0 R107 1 2 33_0402_5%
SRCCLKC0 CLK_A_SB# 17
ATIGCLKT0 30
L21 44 29
0.1U_0402_16V4Z +CLK_VDD_48M GNDCPU ATIGCLKC0
+3VS 1 2 49 GNDPCI ATIGCLKT1 27

0.1U_0402_16V4Z
CHB1608U301_0603 1 31 28
GNDATI ATIGCLKC1

1 10U_0805_10V4Z~N
C253 C254 36 24 SRCCLKT3 R112 1 2 33_0402_5%
4.7U_0805_10V4Z GNDSRC SRCCLKT3 SRCCLKC3 R113 33_0402_5% CLK_A_NB 9
26 GNDSRC SRCCLKC3 25 1 2 CLK_A_NB# 9
2 2 20 22 SRCCLKT4 R114 1 2 33_0402_5%
2 GNDSRC SRCCLKT4 SRCCLKC4 R115 33_0402_5% CLK_PCIE_LAN 25
15 GNDSRC SRCCLKC4 23 1 2 CLK_PCIE_LAN# 25
C259 C255 5 18
GND SRCCLKT5
55 GND SRCCLKC5 19
1 1

49.9_0402_1%

49.9_0402_1%

49.9_0402_1%

49.9_0402_1%

49.9_0402_1%

49.9_0402_1%
38 GNDA SRCCLKT6 16 FS_A/B/C- H=0.7V L=0.35V

1
SRCCLKC6 17
33P_0402_50V8J 1 2 XTALIN_CLK 1 12 +VCCP
C260 XIN SRCCLKT7
SRCCLKC7 13

R116

R121

R117

R122

R118

R119
R120
Y2

2
@ 1M_0402_5% 10 R124 2 1 10K_0402_5% +CLK_VDD1
CLKREQA#

1
2 11 R127 2 1 10K_0402_5% +CLK_VDD1

2
33P_0402_50V8J XTALOUT_CLK XOUT CLKREQB# R125 R130
1 2
C261 14.31818MHZ_20P_6X1430004201 50 R128 1 2 33_0402_5% 0: CK410 @ 470_0402_5% @ 470_0402_5%
CK410#/PCICLK0
+3VS 1 R123 2 6 VTT_PWRGD#/PD 1 2 +CLK_VDD1 1: CK409
10K_0402_5% +CLK_VDD1 2 1 48 4 R129 @ 4.7K_0402_5%

2
CPU_STOP# USB_48MHZ
1

D @ R126 10K_0402_5% USB_48MHZ R131 1 2 33_0402_5% CLK_USB_48M 18


CPU_BSEL0
2 Q10 1 2 CPU_BSEL1
2 18,21 CLK_OK 6,17,41 H_DPSLP# 2
G R464 0_0402_5% 9 FS_C R133 1 2 4.7K_0402_5%
FS_C CPU_BSEL0 7,21

1
S 2N7002_SOT23 7 53 FS_B/REF1 R132 1 2 33_0402_5% R135 1 2 4.7K_0402_5%
13,14,18,26 SB_SMCLK
3

SCLK FS_B/REF1 FS_A/REF0 R134 1 CPU_BSEL1 7


13,14,18,26 SB_SMDATA 8 SDATA FS_A/REF0 54 2 33_0402_5% R137 1 2 470_0402_5% +CLK_VDD1 R478 R477
52 TEST_SEL/REF2 R136 1 2 33_0402_5% @ 0_0402_5% @ 0_0402_5%
TEST_SEL/REF2 CLK_AC97_14M 29
CLK_SB_14M 18
37

2
IREF CLK_NB_14M 11

475_0603_1%
1 2 CLK_LPC_14M 31
R138 ICS951413CGLFT_TSSOP56~N @ R1010 0_0402_5%

Keep the trace as short as possible.

2
ICS951411 AND CY28RS400 ARE FULLY PIN FS_C FS_B FS_A CPU SRC PCI REF USB
COMPATIBLE AND CAN BE INTERCHANGED 0 266.66100.0033.33 14.31848.000
WITHOUT ANY HARDWARE MODIFICATION. 0
Internal Pull-low 120k: pin48 1 133.33100.0033.33 14.31848.000
Internal Pull-up 120k: pin 52, 53 and 54. 0
0 200.00100.0033.33 14.31848.000
1
1 166.66100.0033.33 14.31848.000
0 1 100.00100.0033.33 14.31848.000
1
0 400.00100.0033.33 14.31848.000
1
1 RESERVED 14.31848.000

3 3

4 4

Compal Electronics, Inc.


Title
SCHEMATIC, M/B LA-2642P
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Re v
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401380 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: 星 期五, 七月 29, 2005 Sheet 16 of 48
A B C D E
5 4 3 2 1

R139 1 2 8.2K_0402_5%
U7A

SB400
L4 PCI_CLK0_R R141 1 2 39_0402_5%
PCICLK0 PCI_CLK1_R R142 39_0402_5% CLK_PCI_MINI 24
9,18,25,42 NB_RST# AH8 A_RST# PCICLK1 L3 1 2 CLK_PCI_CB 27
L2 PCI_CLK2_R R143 1 2 39_0402_5%
PCICLK2 PCI_CLK3_R R1011 39_0402_5% CLK_PCI_LPC 31
16 CLK_A_SB L27 PCIE_RCLKP PCICLK3 L1 1 2 CLK_PCI_TPM 31

PCI CLKS
16 CLK_A_SB# M27 PCIE_RCLKN PCICLK4 M4 PCI_CLK4 21
PCICLK5 M3 PCI_CLK5 21
D 0.01U_0402_16V7K C263 ALNK_MRX_C_STX_P0 D
9 ALNK_MRX_STX_P0 1 2 M30 PCIE_TX0P PCICLK6 M2 PCI_CLK6 21 PCI_CLK2 21
0.01U_0402_16V7K 1 2 C264 ALNK_MRX_C_STX_N0 N30 M1
9 ALNK_MRX_STX_N0 PCIE_TX0N PCICLK7 PCI_CLK7 21 PCI_CLK3 21
0.01U_0402_16V7K 1 2 C266 ALNK_MRX_C_STX_P1 K30 N4
9 ALNK_MRX_STX_P1 PCIE_TX1P PCICLK8 PCI_CLK8 21
0.01U_0402_16V7K 1 2 C265 ALNK_MRX_C_STX_N1 L30 N3 PCICLK9_R R144 1 2 22_0402_5%
9 ALNK_MRX_STX_N1 PCIE_TX1N PCICLK9 PCICLKFB C267 1
H30 PCIE_TX2P PCICLK_FB N2 2
J30 100P_0402_50V8J
PCIE_TX2N SB_PCIRST#
F30 PCIE_TX3P PCIRST# AJ7 @
G30 W3 PCI_AD0 +3VS
PCIE_TX3N AD0/ROMA18 PCI_AD1
AD1/ROMA17 Y2

1
PCI_AD2

14
9 ALNK_MTX_C_SRX_P0 M29 PCIE_RX0P AD2/ROMA16 W4
N29 Y3 PCI_AD3 R145 U8A
9 ALNK_MTX_C_SRX_N0 PCIE_RX0N AD3/ROMA15
M28 V1 PCI_AD4 8.2K_0402_5% 1

P
9 ALNK_MTX_C_SRX_P1 PCIE_RX1P AD4/ROMA14 A
N28 Y4 PCI_AD5 3 R146 1 2 33_0402_5%
9 ALNK_MTX_C_SRX_N1 PCIE_RX1N AD5/ROMA13 O PCIRST_CB# 27
J29 V2 PCI_AD6 2

2
PCIE_RX2P AD6/ROMA12 B

G
K29 W2 PCI_AD7
PCIE_RX2N AD7/ROMA11 PCI_AD8 74VHC08MTCX_NL_TSSOP14~N
+1.8VS 1 2 J28 AA4

7
R1033 0_0603_5% PCIE_RX3P AD8/ROMA9 PCI_AD9
2 1 K28 PCIE_RX3N AD9/ROMA8 V4
PCI_AD10

14
150_0603_1% AD10/ROMA7 AA3
C279 C271 R148 1 2 G27 U1 PCI_AD11 U8B
0.1U_0402_16V4Z R147 PCIE_CALRP AD11/ROMA6 PCI_AD12
10U_0805_10V4Z~N 1 2 H27 AA2 4

P
1 2 PCIE_PVDDR PCIE_CALRN AD12/ROMA5 A
150_0603_1% U2 PCI_AD13 +3VS 6 R150 1 2 33_0402_5%
AD13/ROMA4 PCI_AD14 O PCIRST_MINI# 24

PCI EXPRESS INTERFACE


1 2 G28 PCIE_CALI AD14/ROMA3 AA1 1 2 5 B

G
R140 4.12K_0603_1% U3 PCI_AD15 R149 10K_0402_5%
PCIE_PVDD AD15/ROMA2 PCI_AD16 74VHC08MTCX_NL_TSSOP14~N
L22 R30 T4

7
PCIE_PVDD AD16/ROMD0 PCI_AD17
80mA AD17/ROMD1 AC1
PCIE_PVDDR PCI_AD18

14
+1.8VS 1 2 F26 PCIE_VDDR_1 AD18/ROMD2 R2
FBM-10-201209-260-T_0805 R29 AD4 PCI_AD19 U8C
C273 10U_0805_10V4Z~N PCIE_VDDR_2 AD19/ROMD3 PCI_AD20
1 2 G26 R3 10

P
C272 10U_0805_10V4Z~N PCIE_VDDR_3 AD20/ROMD4 PCI_AD21 A R151 1
1 2 P26 PCIE_VDDR_4 AD21/ROMD5 AD3 O 8 2 33_0402_5% PCIRST_EC# 31
C274 1 2 0.1U_0402_16V4Z K26 R4 PCI_AD22 9

PCI INTERFACE
PCIE_VDDR_5 AD22/ROMD6 B

G
C275 1 2 0.1U_0402_16V4Z L26 AD2 PCI_AD23
C277 0.1U_0402_16V4Z PCIE_VDDR_6 AD23/ROMD7 PCI_AD24 74VHC08MTCX_NL_TSSOP14~N
1 2 P28 P2

7
C C276 0.1U_0402_16V4Z PCIE_VDDR_7 AD24 PCI_AD25 C
1 2 N26 PCIE_VDDR_8 AD25 AE3
+3VS C262 0.1U_0402_16V4Z PCI_AD26

14
1 2 P27 PCIE_VDDR_9 AD26 P3
C278 1 2 0.1U_0402_16V4Z AE2 PCI_AD27 U8D
AD27 PCI_AD28
H28 P4 13

P
PCIE_VSS_1 AD28 PCI_AD29 A R180 1
F29 PCIE_VSS_2 AD29 AF2 O 11 2 33_0402_5% PCIRST_TPM# 31
RP27 H29 N1 PCI_AD30 PCI_AD[0..31] 12
PCIE_VSS_3 AD30 PCI_AD[0..31] 24,27 B

G
1 8 PCI_PIRQA# H26 PCIE_VSS_4 AD31 AF1 PCI_AD31
2 7 PCI_PIRQB# F27 V3 PCI_C/BE#0 24,27
74VHC08MTCX_NL_TSSOP14~N

7
PCIE_VSS_5 CBE0#/ROMA10
3 6PCI_PIRQC# G29 PCIE_VSS_6 CBE1#/ROMA1 AB4 PCI_C/BE#1 24,27
4 5PCI_PIRQD# L29 PCIE_VSS_7 CBE2#/ROMWE# AC2 PCI_C/BE#2 24,27
J26 PCIE_VSS_8 CBE3# AE4 PCI_C/BE#3 24,27
RP64 8.2K_1206_8P4R_5% L28 T3 PCI_FRAME#
PCIE_VSS_9 FRAME# PCI_FRAME# 24,27 +3VS
J27 AC4 PCI_DEVSEL#
PCIE_VSS_10 DEVSEL#/ROMA0 PCI_DEVSEL# 24,27
1 8 PCI_PIRQE# N27 AC3 PCI _IRDY#
PCIE_VSS_11 IRDY# PCI_IRDY# 24,27
2 7 PCI_PIRQF# M26 T2 PCI_TRDY#
PCIE_VSS_12 TRDY#/ROMOE# PCI_TRDY# 24,27
3 6 PCI_PIRQG# K27 U4
PCIE_VSS_13 PAR/ROMA19 PCI_PAR 24,27
4 5 PCI_PIRQH# P29 T1 PCI_STOP#
PCIE_VSS_14 STOP# PCI_STOP# 24,27
P30 AB2 PCI_PERR# RP28
PCIE_VSS_15 PERR# PCI_PERR# 24,27
8.2K_1206_8P4R_5% AB3 PCI_SERR# PCI_REQ#3 8 1
SERR# PCI_SERR# 24,27
AJ8 AF4 PCI_REQ#0 PCI_REQ#2 7 2
6,16,41 H_DPSLP# CPU_STP#/DPSLP# REQ0# PCI_REQ#1 PCI_REQ#0
AK7 PCI_STP# REQ1# AF3 6 3
PCI_PIRQA# AG5 AG2 PCI_REQ#2 PCI_REQ#1 5 4
INTA# REQ2# PCI_REQ#2 27
PCI_PIRQB# AH5 AG3 PCI_REQ#3
INTB# REQ3#/PDMA_REQ0# PCI_REQ#3 24
PCI_PIRQC# AJ5 AH1 PCI_REQ#4 8.2K_1206_8P4R_5%
PCI_PIRQD# INTC# REQ4#/PLL_BP33/PDMA_REQ1# PCI_REQ#5 RP29
AH6 INTD# REQ5#/GPIO13 AH2
PCI_PIRQE# AJ6 AH3 PCI_REQ#6 PCI_REQ#5 8 1
27 PCI_PIRQE# INTE#/GPIO33 REQ6#/GPIO31
1 R152 2 24,27 PCI_PIRQF#
PCI_PIRQF# AK6 INTF#/GPIO34 GNT0# AJ2 PCI_GNT#0 PCI_GNT#0 7 2
20M_0603_5% PCI_PIRQG# AG7 AK2 PCI_GNT#1 PCI_GNT#1 6 3
24,27 PCI_PIRQG# INTG#/GPIO35 GNT1#
PCI_PIRQH# AH7 AJ3 PCI_GNT#2 PCI_REQ#4 5 4
27 PCI_PIRQH# INTH#/GPIO36 GNT2# PCI_GNT#2 27
SB_32KX2 SB_32KX1 AK3 PCI_GNT#3
GNT3#/PLL_BP66/PDMA_GNT0# PCI_GNT#3 24
15P_0402_50V8D

15P_0402_50V8D

AG4 PCI_GNT#4 8.2K_1206_8P4R_5%


GNT4#/PLL_BP50/PDMA_GNT1# PCI_GNT#5 RP30
GNT5#/GPIO14 AH4
B PCI_GNT#6 PCI_STOP# B
GNT6#/GPIO32 AJ4 8 1
1

SB_32KX1 B2 AG1 PCI_CLKRUN# PCI_TRDY# 7 2


X1 CLKRUN# PCI_CLKRUN# 24,27,31
2

Y3 AB1 PCI_LOCK# PCI_FRAME# 6 3


IN

OUT

XTAL

R153 LOCK# PCI _IRDY# 5 4


@ 20M_0603_5% SB_32KX2 B1 X2 8.2K_1206_8P4R_5%
1 1
C280 C281 LPC_AD0 RP31
NC

NC

AG25 LPC_AD0 31
1

LAD0 LPC_AD1 PCI_PERR#


LAD1 AH25 LPC_AD1 31 8 1
C29 AJ25 LPC_AD2 PCI_SERR# 7 2
LPC_AD2 31
2

2 2 6 H_PWRGOOD CPU_PG/LDT_PG LAD2 LPC_AD3 PCI_LOCK#


6 H_INTR A28 INTR/LINT0 LAD3 AH24 LPC_AD3 31 6 3
C28 AG24 PCI_DEVSEL# 5 4
6 H_NMIR154 NMI/LINT1 LFRAME# LPC_DRQ0# LPC_FRAME# 31
1 2 0_0402_5% B29 AH26
L PC

32.768KHZ_12.5P_1TJS125DJ2A073 6 H_INIT# INIT# LDRQ0# LPC_DRQ1# 8.2K_1206_8P4R_5%


6 H_SMI# D29 SMI# LDRQ1# AG26 LPC_DRQ1# 31
E4 RP32
6 H_SLP# SLP#/LDT_STP# SERIRQ PCI_GNT#4
6 H_IGNNE# B30 IGNNE# SERIRQ AK27 SERIRQ 27,31 8 1
F28 PCI_GNT#5 7 2
CPU

6 H_A20M# A20M# PCI_GNT#2


6 H_FERR# E28 FERR# 6 3
E29 PCI_GNT#3 5 4
6 H_STPCLK# R155 STPCLK#/ALLOW_LDTSTP RTC_CLK
1 2 D25 LDT_PG/SSMUXSEL/GPIO0 RTCCLK C2 RTC_CLK 21
10K_0402_5% E27 F3 8.2K_1206_8P4R_5%
RTC

6,41 H_DPRSLP DPRSLPVR RTC_IRQ#/ACPWR_STRAP AUTO_ON# 21


PCI_CLKRUN# 2
RTC Battery 9,21 SB_BMREQ#
R158 1 2 0_0402_5%
D27
D28
BMREQ#
A2 +SB_VBAT 4.7K_0402_5% R156
1
6,9 H_RESET# LDT_RST# VBAT PCI_GNT#6
RTC_GND A1 2 1
8.2K_0402_5% R157

- + +RTCBATT 218S4EASA32G_BGA564_SB400 10K_1206_8P4R_5%


PCI_REQ#6 8 1 RP34
2 - + 1+RTCBATT LPC_DRQ1# 7 2
LPC_DRQ0# 6 3
SERIRQ 5 4
1

D13
A
Place J1 close LPC_AD3 8 1 A
to DDR-SODIMM JRTC1 BAS40-04_SOT23 LPC_AD0 7 2
MAXELL_1220G +RTCVCC LPC_AD1 6 3
+SB_VBAT LPC_AD2 5 4
3

10K_1206_8P4R_5% RP33
1 R161 2 BAT R162
+CHGRTC
C283 470_0805_5% 1K_0805_1% 1 Compal Electronics, Inc.
1U_0603_10V6K

1 C284
2

W=20mils Title
@ JOPEN1 0.1U_0402_16V4Z SCHEMATIC, M/B LA-2642P
2
1

2 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
401380 B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
PUT JOPEN1 NEAR TO RAM DOOR MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: 星期五, 七月 29, 2005 Sheet 17 of 48
5 4 3 2 1
5 4 3 2 1

+3VALW

U7B

SB400
RP35
1 8 MAINPWON_R A15 USB48M 1 2
48M_X1/USBCLK CLK_USB_48M 16 +3V
2 7 EC_THRM# EC_THRM# C6 B15 R163 0_0402_5%
LPC_PME# TALERT#/TEMP_ALERT#/GPIO10 48M_X2 R169 11.8K_0603_1%
3 6 32 EC_FLASH# D5 BLINK/GPM6# USB_RCOMP C15
4 5 AC_RST# EC_SWI# C4 D16
31 EC_SWI# PCI_PME#/GEVENT4# USB_VREFOUT
10K_1206_8P4R_5% D3 C16
31 EC_LID_OUT# RI#/EXTEVNT0# USB_ATEST1
PM_SLP_S3#

ACPI/WAKE UP
31 PM_SLP_S3# B4 SLP_S3# USB_ATEST0 D15
PM_SLP_S5# E3 B8 USB_OC0#
31 PM_SLP_S5# SLP_S5# USB_OC0#/GPM0# USB_OC0# 23 10K_1206_8P4R_5%
D PBTN_OUT# B3 C8 USB_OC1# D
31 PBTN_OUT#

EVENTS
PWR_BTN# USB_OC1#/GPM1# USB_OC1# 23
C3 C7 USB_OC2# USB_OC3# 5 4
21 SB_PWRGD PWR_GOOD USB_OC2#/FANOUT1/GPM2# USB_OC2# 23
SUS_STAT# D4 B7 USB_OC3# USB_OC2# 6 3
SUS_STAT# USB_OC3#/GPM3# USB_OC3# 23
R1026 1 2 10K_0402_5% PBTN_OUT# R164 1 2 4.7K_0402_5% F2 B6 USB_OC4# USB_OC0# 7 2
R170 1 TEST1 USB_OC4#/GPM4#
2 4.7K_0402_5% E2 TEST0 USB_OC5#/GPM5# A6 EC_SCI#
EC_SCI# 31
USB_OC1# 8 1
GATEA20 AJ26 B5 USB_OC6#
RP39 31 GATEA20 KBRST# GA20IN USB_OC6#/FAN_ALERT#/GEVENT6# EC_SMI# RP37
31 KBRST# AJ27 KBRST# USB_OC7#/CASE_ALERT#/GEVENT7# A5 EC_SMI# 31
1 8 EC_FLASH# MAINPWON_R D6 USB_OC6#
PM_SLP_S3# LPC_PME# SMBALERT#/THRMTRIP#/GEVENT2# R1055 10K_0402_5%
2 7 C5 LPC_PME#/GEVENT3# USB_HSDP7+ A11
3 6 PME# EXTEVENT1# A25 B11 USB_OC4#

USB INTERFACE
PM_SLP_S5# LPC_SMI#/EXTEVNT1# USB_HSDM7- R1057 10K_0402_5%
4 5 6 H_PROCHOT# D8 VOLT_ALERT#/S3_STATE/GEVENT5#
ITP_DBRESET# D7 A10 USBP6+
6 ITP_DBRESET# SYS_RESET#/GPM7# USB_HSDP6+ USBP6+ 23
4.7K_1206_8P4R_5% 1 2 PME# D2 B10 USBP6-
25,31 PCIE_PME# WAKE#/GEVENT8# USB_HSDM6- USBP6- 23
R165 0_0402_5%
R166 1 2 4.7K_0402_5% EC_SWI# EC_RSMRST# D1 A14
RSMRST# USB_HSDP5+ +3VALW
B14

CLK / RST
USB_HSDM5-
16 CLK_SB_14M A23 14M_X1/OSC
1 2 ITP_DBRESET# A13 USBP4+
USB_HSDP4+ USBP4+ 23
R991 4.7K_0402_5% B23 B13 USBP4-
14M_X2 USB_HSDM4- USBP4- 23
EC_SMI#
AK24 A18 USBP3+ R1054 10K_0402_5%
+3VS SIO_CLK USB_HSDP3+ USBP3+ 23
@ 1 B18 USBP3- EC_SCI#
15P_0402_50V8D USB_HSDM3- USBP3- 23
B25 R1056 10K_0402_5%
R1024 22 ODD_EN# ROM_CS#/GPIO1
1 2 10K_0402_5% GATEA20
22 ODD_RST# C25 GHI#/GPIO6 USB_HSDP2+ A17 USBP2+
USBP2+ 23
C285 C23 B17 USBP2-
2 16,21 CLK_OK VGATE/GPIO7 USB_HSDM2- USBP2- 23
R1025 1 2 10K_0402_5% KBRST# D24
32 PASSWORD# AGP_STP#/GPIO4
BRD_ID1 D23 A21 USBP1+
AGP_BUSY#/GPIO5 USB_HSDP1+ USBP1+ 23
R988 1 2 4.7K_0402_5% EXTEVENT1# BRD_ID0 A27 B21 USBP1-
FANOUT0/GPIO3 USB_HSDM1- USBP1- 23
SPKR C24
R173 1 30 SPKR SPKR/GPIO2
C 2 2.2K_0402_5% SB_SMCLK SB_SMCLK A26 A20 USBP0+ C

GPIO
13,14,16,26 SB_SMCLK SCL0/GPOC0# USB_HSDP0+ USBP0+ 23 +3V
SB_SMDATA B26 B20 USBP0-
13,14,16,26 SB_SMDATA SDA0/GPOC1# USB_HSDM0- USBP0- 23
R174 1 2 2.2K_0402_5% SB_SMDATA B27 L23 FBM-10-201209-260-T_0805
22 BAY_ID1 DDC1_SCL/GPIO9
22 BAY_ID2 C26 DDC1_SDA/GPIO8 1 2
C27 C21 AVDDTX
22 BAY_ID3 DDC2_SCL/GPIO11 AVDDTX_0
GPIO12 D26 C18 AVDDTX C286 1 2 10U_0805_10V4Z~N
RP65 DDC2_SDA/GPIO12 AVDDTX_1
AVDDTX_2 D13
BAY_ID[1..3] & BAY_TYPE ARE REAERVED FOR Vesay Bay D10 C287 1 2 1U_0603_10V6K
AC_SDIN0 AVDDTX_3 AVDDRX
1 8 AVDDRX_0 D20
2 7 AC_SDIN1 J2 D17 C288 1 2 0.1U_0402_16V4Z

(NOT USED)
AC_SDIN2 NC1 AVDDRX_1 C289 1
3 6 K3 NC4 AVDDRX_2 C14 2 0.1U_0402_16V4Z
4 5 AC_BITCLK J3 C11 C290 1 2 0.1U_0402_16V4Z
NC3 AVDDRX_3
K2 NC2
R1043 1 10K_1206_8P4R_5%
2 GPIO12 A16 AVDDC
10K_0402_5% AVDDC

AVSSC B16
L24 FBM-10-201209-260-T_0805
AVSS_USB_1 A9 1 2
AC_BITCLK G1 A12
29 AC_BITCLK AC_BITCLK AVSS_USB_2
21,29 AC_SDOUT 1 R176 33_0402_5%
2 G2 AC_SDOUT AVSS_USB_3 A19 AVDDRX C291 1 2 10U_0805_10V4Z~N
AC_SDIN0 H4 A22
29 AC_SDIN0 AC_SDIN0 AVSS_USB_4
AC_SDIN1 C292 1 2 1U_0603_10V4Z

A C97
29 AC_SDIN1 G3 AC_SDIN1 AVSS_USB_5 B9
AC_SDIN2 G4 B12
A C_SYNC AC_SDIN2 AVSS_USB_6
29 AC_SYNC 1 R177 33_0402_5%
2 H1 AC_SYNC AVSS_USB_7 B19 C293 1 2 0.1U_0402_16V4Z

USB PWR
AC_RST# 1 R178 33_0402_5%
2 H3 B22 C295 1 2 0.1U_0402_16V4Z
29 AC_RST# AC_RST# AVSS_USB_8 C294 1
21 SPDIF_OUT H2 SPDIF_OUT AVSS_USB_9 C9 2 0.1U_0402_16V4Z
AVSS_USB_10 C10
AVSS_USB_11 C12
AVSS_USB_12 C13
B SUS_STAT# B
9 NB_SUS_STAT# 2 1 AVSS_USB_13 C17
AVSS_USB_14 C19
D21 CH751H-40_SC76 C20 L25 FBM-10-201209-260-T_0805
AVSS_USB_15 AVDDC
2 1 NB_RST# 9,17,25,42 AVSS_USB_16 C22 1 2
AVSS_USB_17 D9
D22 CH751H-40_SC76 D11 C296 1 2 10U_0805_10V4Z~N
AVSS_USB_18
AVSS_USB_19 D12
D14 C297 1 2 1U_0603_10V4Z
AVSS_USB_20
AVSS_USB_21 D18
D19 C299 1 2 0.1U_0402_16V4Z
AVSS_USB_22
AVSS_USB_23 D21
AVSS_USB_24 D22

218S4EASA32G_BGA564_SB400
MAINPWON_R D17 2 1CH751H-40_SC76 MAINPWON 6,34,35,38,40

+3VS +3VS

R159 R167 EC_RSMRST#


31 EC_RSMRST#
10K_0402_5% 10K_0402_5%

1
BRD_ID0 BRD_ID1 R181
A A

47K_0402_5%
R160 R168
@ 10K_0402_5% @ 10K_0402_5% 2

Compal Electronics, Inc.


Title
For BIOS SCHEMATIC, M/B LA-2642P
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
401380 B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: 星期五, 七月 29, 2005 Sheet 18 of 48
5 4 3 2 1
5 4 3 2 1

U7C

SB400
AK22 SATA_TX0+
AJ22 SATA_TX0- PIDE_IORDY AD30 IDE_PDIORDY 22
PIDE_IRQ AE28 INT_IRQ14 22
AK21 AD27 +3VS
SATA_RX0- PIDE_A0 IDE_PDA0 22
AJ21 SATA_RX0+ PIDE_A1 AC27 IDE_PDA1 22
PIDE_A2 AD28 IDE_PDA2 22

1
AK19 AD29 IDE_PDDACK#
SATA_TX1+ PIDE_DACK# IDE_PDDACK# 22 R183
AJ19 SATA_TX1- PIDE_DRQ AE27 IDE_PDDREQ 22
AE30 @ 10K_0402_5% HIGH: LONG RST(defaul)
PIDE_IOR# IDE_PDIOR# 22 LOW: SHORT RST
AK18 SATA_RX1- PIDE_IOW# AE29 IDE_PDIOW# 22
AJ18 AC28

2
SATA_RX1+ PIDE_CS1# IDE_PDCS1# 22 IDE_PDDACK#
PIDE_CS3# AC29 IDE_PDCS3# 22
AK14 SATA_TX2+

1
D AJ14 AF29 IDE_PDD0 D
SATA_TX2- PIDE_D0 IDE_PDD[0..15] 22
AF27 IDE_PDD1 R184
PIDE_D1 IDE_PDD2 10K_0402_5%
AK13 AG29

PRIMARY ATA 66/100


SATA_RX2- PIDE_D2 IDE_PDD3
AJ13 SATA_RX2+ PIDE_D3 AH30 @
AH28 IDE_PDD4

2
PIDE_D4 IDE_PDD5
AK11 AK29

SERIAL ATA
SATA_TX3+ PIDE_D5 IDE_PDD6
AJ11 SATA_TX3- PIDE_D6 AK28
AH27 IDE_PDD7
PIDE_D7 IDE_PDD8
AK10 SATA_RX3- PIDE_D8 AG27
AJ10 AJ28 IDE_PDD9 Long RST: for A21 and Future version.
SATA_RX3+ PIDE_D9 IDE_PDD10
PIDE_D10 AJ29
AJ15 AH29 IDE_PDD11
SATA_CAL PIDE_D11 IDE_PDD12
PIDE_D12 AG28
AJ16 AG30 IDE_PDD13
SATA_X1 PIDE_D13 IDE_PDD14
PIDE_D14 AF30
AK16 AF28 IDE_PDD15
SATA_X2 PIDE_D15
AK8 SATA_ACT# SIDE_IORDY V29 IDE_SDIORDY 22
SIDE_IRQ T27 INT_IRQ15 22
AH15 PLLVDD_SATA SIDE_A0 T28 IDE_SDA0 22
SIDE_A1 U29 IDE_SDA1 22
AH16 XTLVDD_SATA SIDE_A2 T29 IDE_SDA2 22
SIDE_DACK# V30 IDE_SDDACK# 22
AG10 AVDD_SATA_1 SIDE_DRQ U28 IDE_SDDREQ 22
AG14 AVDD_SATA_2 SIDE_IOR# W29 IDE_SDIOR# 22
AH12 AVDD_SATA_3 SIDE_IOW# W30 IDE_SDIOW# 22
AG12 AVDD_SATA_4 SIDE_CS1# R27 IDE_SDCS1# 22
AG18 AVDD_SATA_5 SIDE_CS3# R28 IDE_SDCS3# 22
AG21 AVDD_SATA_6
AH18 V28 IDE_SDD0
AVDD_SATA_7 SIDE_D0/GPIO15 IDE_SDD[0..15] 22
AG20 W28 IDE_SDD1

SECONDARY ATA 66/100


AVDD_SATA_8 SIDE_D1/GPIO16 IDE_SDD2
SIDE_D2/GPIO17 Y30
AG9 AA30 IDE_SDD3
AVSS_SATA_1 SIDE_D3/GPIO18
1

AF10 Y28 IDE_SDD4


R996 AVSS_SATA_2 SIDE_D4/GPIO19 IDE_SDD5
C
AF11 AVSS_SATA_3 SIDE_D5/GPIO20 AA28 C
0_0402_5% AF12 AB28 IDE_SDD6
AVSS_SATA_4 SIDE_D6/GPIO21 IDE_SDD7
AF13 AVSS_SATA_5 SIDE_D7/GPIO22 AB27

SERIAL ATA POWER


AF14 AB29 IDE_SDD8
2

AVSS_SATA_6 SIDE_D8/GPIO23 IDE_SDD9


AF15 AVSS_SATA_7 SIDE_D9/GPIO24 AA27
AF16 Y27 IDE_SDD10
AVSS_SATA_8 SIDE_D10/GPIO25 IDE_SDD11
AF17 AVSS_SATA_9 SIDE_D11/GPIO26 AA29
AF18 W27 IDE_SDD12
AVSS_SATA_10 SIDE_D12/GPIO27 IDE_SDD13
AF19 AVSS_SATA_11 SIDE_D13/GPIO28 Y29
AF20 V27 IDE_SDD14
AVSS_SATA_12 SIDE_D14/GPIO29 IDE_SDD15
AF21 AVSS_SATA_13 SIDE_D15/GPIO30 U27
AF22 AVSS_SATA_14
AH9 AVSS_SATA_15
AG11 AVSS_SATA_16 AVSS_SATA_33 AG13
AG15 AVSS_SATA_17 AVSS_SATA_34 AH22
AG17 AVSS_SATA_18 AVSS_SATA_35 AK12
AG19 AVSS_SATA_19 AVSS_SATA_36 AH11
AG22 AVSS_SATA_20 AVSS_SATA_37 AJ17
AG23 AVSS_SATA_21 AVSS_SATA_38 AH14
AF9 AVSS_SATA_22 AVSS_SATA_39 AH19
AH17 AVSS_SATA_23 AVSS_SATA_40 AJ20
AH23 AVSS_SATA_24 AVSS_SATA_41 AH21
AH13 AVSS_SATA_25 AVSS_SATA_42 AJ9
AH20 AVSS_SATA_26 AVSS_SATA_43 AG16
AK9 AVSS_SATA_27 AVSS_SATA_44 AK15
AJ12 AVSS_SATA_28 AVSS_SATA_45 AK20
AK17 AVSS_SATA_29
AK23 AVSS_SATA_30
AH10 AVSS_SATA_31
AJ23 AVSS_SATA_32

218S4EASA32G_BGA564_SB400

B B

A A

Compal Electronics, Inc.


Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-2642P
Size Document Number Re v
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401380 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: 星 期五, 七月 29, 2005 Sheet 19 of 48
5 4 3 2 1
+3VS

60mA

U7D

SB400
C302 1 2 10U_0805_10V4Z~N A30 E19
C301 10U_0805_10V4Z~N VDDQ_1 VSS_12
1 2 D30 VDDQ_2 VSS_13 E22
C304 1 2 0.1U_0402_16V4Z E24 E23
C303 0.1U_0402_16V4Z VDDQ_3 VSS_14
1 2 E25 VDDQ_4 VSS_15 E26
C305 1 2 0.1U_0402_16V4Z J5 E30
C306 0.1U_0402_16V4Z VDDQ_5 VSS_16
1 2 K1 VDDQ_6 VSS_17 F1
C332 1 2 0.1U_0402_16V4Z K5 F4
C307 0.1U_0402_16V4Z VDDQ_7 VSS_18
1 2 N5 VDDQ_8 VSS_19 G5
C309 1 2 0.1U_0402_16V4Z P5 H5
C308 0.1U_0402_16V4Z VDDQ_9 VSS_20
1 2 R1 VDDQ_10 VSS_21 J1
C333 1 2 0.1U_0402_16V4Z U5 J4
C310 0.1U_0402_16V4Z VDDQ_11 VSS_22
1 2 U26 VDDQ_12 VSS_23 K4
C311 1 2 0.1U_0402_16V4Z U30 L5
C313 0.1U_0402_16V4Z VDDQ_13 VSS_24
1 2 V5 VDDQ_14 VSS_25 M5
C312 1 2 0.1U_0402_16V4Z V26 P1
C314 0.1U_0402_16V4Z VDDQ_15 VSS_26
1 2 Y1 VDDQ_16 VSS_27 R5
C315 1 2 0.1U_0402_16V4Z Y26 R26
C334 0.1U_0402_16V4Z VDDQ_17 VSS_28
1 2 AA5 VDDQ_18 VSS_29 T5
C316 1 2 0.1U_0402_16V4Z AA26 T26
VDDQ_19 VSS_30
AB5 VDDQ_20 VSS_31 T30
+1.8VS AC30 W1
VDDQ_21 VSS_32
350mA AD5 W5
VDDQ_22 VSS_33
AD26 VDDQ_23 VSS_34 W26
AE1 VDDQ_24 VSS_35 Y5
AE5 VDDQ_25 VSS_36 AB26
AE26 VDDQ_26 VSS_37 AB30
AF6 VDDQ_27 VSS_38 AC5
C335 1 2 10U_0805_10V4Z~N AF7 AC26
C317 10U_0805_10V4Z~N VDDQ_28 VSS_39
1 2 AF24 VDDQ_29 VSS_40 AD1
C319 1 2 10U_0805_10V4Z~N AF25 AF5
C318 10U_0805_10V4Z~N VDDQ_30 VSS_41
1 2 AK1 VDDQ_31 VSS_42 AF8
C320 1 2 0.1U_0402_16V4Z AK4 AF23
C321 0.1U_0402_16V4Z VDDQ_32 VSS_43
1 2 AK26 VDDQ_33 VSS_44 AF26
C323 1 2 0.1U_0402_16V4Z AK30 AG8
C322 0.1U_0402_16V4Z VDDQ_34 VSS_45
1 2 VSS_46 AJ1
C324 1 2 0.1U_0402_16V4Z M12 AJ24
C326 0.1U_0402_16V4Z VDD_1 VSS_47
1 2 M13 AJ30

POWER
C325 0.1U_0402_16V4Z VDD_2 VSS_48
1 2 M18 VDD_3 VSS_49 AK5
C327 1 2 0.1U_0402_16V4Z M19 AK25
C328 0.1U_0402_16V4Z VDD_4 VSS_50
1 2 N12 VDD_5 VSS_51 M14
C329 1 2 0.1U_0402_16V4Z N13 M15
C330 0.1U_0402_16V4Z VDD_6 VSS_52
1 2 N18 VDD_7 VSS_53 M16
C331 1 2 0.1U_0402_16V4Z N19 M17
VDD_8 VSS_54
V12 VDD_9 VSS_55 N14
+3VALW V13 N15
VDD_10 VSS_56
V18 VDD_11 VSS_57 N16
0.3mA V19 N17
VDD_12 VSS_58
W12 VDD_13 VSS_59 P12
W13 VDD_14 VSS_60 P13
W18 VDD_15 VSS_61 P14
W19 VDD_16 VSS_62 P15
C337 1 2 10U_0805_10V4Z~N P16
C339 0.1U_0402_16V4Z VSS_63
1 2 A3 S5_3.3V_1 VSS_64 P17
C338 1 2 0.1U_0402_16V4Z A7 P18
C341 0.1U_0402_16V4Z S5_3.3V_2 VSS_65
1 2 E6 S5_3.3V_3 VSS_66 P19
C342 1 2 0.1U_0402_16V4Z E7 R12
S5_3.3V_4 VSS_67
E1 S5_3.3V_5 VSS_68 R13
F5 S5_3.3V_6 VSS_69 R14
VSS_70 R15
+1.8VALWSB 74.6mA E9 R16
S5_1.8V_1 VSS_71
E10 S5_1.8V_2 VSS_72 R17
C343 1 2 10U_0805_10V4Z~N E20 R18
S5_1.8V_3 VSS_73
E21 S5_1.8V_4 VSS_74 R19
C344 1 2 0.1U_0402_16V4Z 100mA +1.8V T12
C347 1 VSS_75
2 0.1U_0402_16V4Z E13 USB_PHY_1.8V_1 VSS_76 T13
C346 1 2 0.1U_0402_16V4Z E14 T14
0.1U_0402_16V4Z USB_PHY_1.8V_2 VSS_77
E16 USB_PHY_1.8V_3 VSS_78 T15
C350 1 2 E17 T16
5.2mA USB_PHY_1.8V_4 VSS_79
VSS_80 T17
+VCCP C30 CPU_PWR VSS_81 T18
C345 1 2 10U_0805_10V4Z~N T19
VSS_82
AG6 V5_VREF VSS_83 U12
C349 1 2 0.1U_0402_16V4Z U13
C348 1 AVDD_CK VSS_84
2 0.1U_0402_16V4Z A24 AVDDCK VSS_85 U14
C351 1 2 0.1U_0402_16V4Z B24 U15
AVSSCK VSS_86
VSS_87 U16
A4 VSS_1 VSS_88 U17
5.5mA A8 U18
VSS_2 VSS_89
A29 VSS_3 VSS_90 U19
0.054mA +1.8VS B28 V14
R191 1 V5_VREF VSS_4 VSS_91
+5VS 2 1K_0402_5% C1 VSS_5 VSS_92 V15
1

2 2 E5 VSS_6 VSS_93 V16


E8 VSS_7 VSS_94 V17
C352 C353 FBM-10-201209-260-T_0805 E11 W14
1U_0603_10V4Z VSS_8 VSS_95
0.1U_0402_16V4Z E12 VSS_9 VSS_96 W15
1 1 L50
+3VS 2 1 E15 VSS_10 VSS_97 W16
E18 W17
2

CH751H-40_SC76 D16 VSS_11 VSS_98


C354 1 2 10U_0805_10V4Z~N
218S4EASA32G_BGA564_SB400
C355 1 2 1U_0603_10V4Z

C356 1 2 0.1U_0402_16V4Z
+1.8VALWSB +1.8VALW
1

R1034
1K_0402_5% R1035
@ 1K_0402_5%
@
2

Compal Electronics, Inc.


Reserved for timing between +3VALW AND +1.8VALW Title
SCHEMATIC, M/B LA-2642P
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
401380 B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: 星期五, 七月 29, 2005 Sheet 20 of 48
5 4 3 2 1

+3VALW +3VS +3VALW +3VS +3VS +3VS +3VS +3VS +3VS +3VS +3VS +3VS +1.8V +3VS

1
R193 R194 R195 R196 R197 R198 R199 R200 R201 R202 R1027 R203 R204 R205
10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 4.7K_0402_5% 1K_0402_5%
10K_0402_5% 4.7K_0402_5%
@ 10K_0402_5% 10K_0402_5% @ 10K_0402_5% 10K_0402_5% 10K_0402_5% @ 10K_0402_5% @ @
@ @

2
17 AUTO_ON#
AC_SDOUT
18,29 AC_SDOUT
RTC_CLK
17 RTC_CLK
SPDIF_OUT
D 18 SPDIF_OUT D
PCI_CLK3
17 PCI_CLK3
PCI_CLK4
17 PCI_CLK4
PCI_CLK5
17 PCI_CLK5
PCI_CLK6
17 PCI_CLK6
PCI_CLK7
17 PCI_CLK7
PCI_CLK8
17 PCI_CLK8
PCI_CLK2
17 PCI_CLK2
SB_BMREQ#
9,17 SB_BMREQ#
MEM_STRAP
10 MEM_STRAP
STRAP_EEPROM
11,42 STRAP_EEPROM

1
R206 R207 R208 R209 R210 R211 R212 R213 R214 R217 R218
@ 10K_0402_5% @ 10K_0402_5% @ 10K_0402_5% R1028 R216 1K_0402_5% 4.7K_0402_5%
10K_0402_5% 10K_0402_5% @ 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 4.7K_0402_5% @ @
@ 10K_0402_5%

2
REQUIRED STRAPS
R997
10K_0402_5%

AUTO_ON# AC97_SDOUT RTC_CLK SPDIF_OUT PCI_CLK3 PCI_CLK4 PCI_CLK5 PCI_CLK6 PCI_CLK7 PCI_CLK8 SB_BMREQ# MEM_STRAP STRAP_EEPROM

PULL MANUAL USE INTERNAL SIO 24MHz USB PHY Use internal PCIE_CM CPU I/F = AMD ROM TYPE
HIGH PWR ON DEBUG RTC PWRDOWN PLL for 48MHZ SET LOW
H,H = PCI ROM 1.8V DDR EEPROM STRAP
C STRAPS DISABLE C
DE FAULT DE FAULT H,L = PMC LPC ROM
DE FAULT

PULL AUTO IGNORE EXTERNAL SIO 48MHz USB PHY 48MHz XTAL PCIE_CM CPU I/F = INTEL
LOW PWR DEBUG RTC (NOT PWRDOWN MODE SET HIGH L,H = NORMAL LPC ROM 0= NORMAL
(Default) 2.5V DDR MEM CHANNEL
ON STRAPS SUPPORTED ENABLE DE FAULT DE FAULT DE FAULT
DE FAULT W/ IT8712 ) DE FAULT DE FAULT L,L = FWH ROM

+3VS SB_BMREQ#&HSYNC&VSYNC: FSB CLK SPEED

1
R220
4.7K_0402_5%
000:100MHZ 001:133MHZ

2
11,15 CRT_VSYNC# 1 2 1 2 CPU_BSEL0 7,16
R222 4.7K_0402_5% R223 @ 0_0402_5%

1
C
1 2 Q11 2 1 2
11,15 CRT_HSYNC# R224 4.7K_0402_5% PMBT3904_SOT23 B R226 2K_0402_5%
E

3
B B

U32-->please close to SB400(U16)


+3VS
1

+3VS
R498
100K_0402_5% C359 0.1U_0402_16V4Z +3VS
C1015
14

14

14

14

14

14
1 2
2

U31A U31B U31C U31D U31E U31F


R227 R228

5
U53
P

P
0.1U_0402_16V4Z
1 2 3 4 1 2 5 6 9 8 1 2 11 10 13 12 2

P
41 VGATE I O I O I O I O I O I O B
330K_0402_5% 330K_0402_5% 4
Y SB_PWRGD 18
G

G
1 1 1 A

G
C357 SN74LVC14APWR_TSSOP14~N
7

7
1

SN74LVC14APWR_TSSOP14~N SN74LVC14APWR_TSSOP14~N C358 NC7SZ08P5X_NL_SC70-5

3
SN74LVC14APWR_TSSOP14~N 0.1U_0402_10V6K~N SN74LVC14APWR_TSSOP14~N 0.47U_0603_10V7K SN74LVC14APWR_TSSOP14~N
R499 2 2
1M_0402_5%
2

CLK_OK CLK_OK
CLK_OK 16,18 NB_PWRGD 9 SB_PWRGD# 11

A A

Compal Electronics, Inc.


Title
SCHEMATIC, M/B LA-2642P
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
401380 B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: 星期五, 七月 29, 2005 Sheet 21 of 48
5 4 3 2 1
+5VS +5VHDD
Q48

D
B+_BIAS 6 F3

S
5 4 +5VS_HDD 1 2
+3VS 2 SI3456BDV-T1-E3_TSOP6
1 2A_6VDC_1812SMD200

1
0_1206_8P4R_5%

G
IDE_PDD7 RP41
1 8 PD_D7 R480
HDD CONNECTOR

3
1
IDE_PDD8 2 7 PD_D8 470K_0402_5%
IDE_PDD6 3 6 PD_D6 R993
IDE_PDD9 4 5 PD_D9 10K_0402_5%

2
RP42 0_1206_8P4R_5%
IDE_PDD5 1 8 PD_D5 D41 1

1
IDE_PDD10 PD_D10 JHDD1 D
2 7
IDE_PDD4 3 6 PD_D4 1 2 1 2 2 Q49 C904
31 PIDERST# 1 2 31 HDD_EN# 0.1U_0603_50V4Z
IDE_PDD11 4 5 PD_D11 PD_D7 3 4 PD_D8 G 2N7002_SOT23
RP43 0_1206_8P4R_5% PD_D6 3 4 PD_D9 2
5 6 S

3
IDE_PDD3 PD_D3 RB751V_SOD323 PD_D5 5 6 PD_D10
1 8 7 7 8 8
IDE_PDD12 2 7 PD_D12 PD_D4 9 10 PD_D11
IDE_PDD2 PD_D2 PD_D3 9 10 PD_D12
3 6 11 11 12 12
IDE_PDD13 4 5 PD_D13 PD_D2 13 14 PD_D13
RP44 0_1206_8P4R_5% PD_D1 13 14 PD_D14
15 15 16 16
IDE_PDD1 1 8 PD_D1 PD_D0 17 18 PD_D15
IDE_PDD14 PD_D14 17 18
IDE_PDD0
2 7
PD_D0 PD_PDDREQ
19 19 20 20
+5VHDD
Placea caps. near HDD
3 6 21 21 22 22
IDE_PDD15 4 5 PD_D15 PD_PDIOW# 23 24 CONN.
RP46 0_1206_8P4R_5% PD_PDIOR# 23 24
25 25 26 26
IDE_PDDREQ 1 8 PD_PDDREQ PD_PDIORDY 27 28 PCSEL 1 R231 2
19 IDE_PDDREQ IDE_PDIOW# PD_PDIOW# PD_PDDACK# 27 28 470_0805_5%
19 IDE_PDIOW# 2 7 29 29 30 30 1 1 1
IDE_PDIOR# 3 6 PD_PDIOR# PD_IRQ14 31 32 C362 C366
19 IDE_PDIOR# 31 32
IDE_PDDACK# 4 5 PD_PDDACK# PD_PDA1 33 34 C363 C364 C365
19 IDE_PDDACK# 33 34
RP45 0_1206_8P4R_5% PD_PDA0 35 36 PD_PDA2 1000P_0402_50V7K~N 10U_0805_10V4Z~N 10U_0805_10V4Z~N 1U_0603_10V4Z 0.1U_0402_16V4Z
IDE_PDA1 PD_PDA1 PD_PDCS1# 35 36 PD_PDCS3# 2 2 2
19 IDE_PDA1 1 8 37 37 38 38
IDE_PDA0 2 7 PD_PDA0 PHDD_LED# 39 40
19 IDE_PDA0 39 40
IDE_PDA2 3 6 PD_PDA2 41 42
19 IDE_PDA2 +5VHDD 41 42 +5VHDD
IDE_PDCS1# 4 5 PD_PDCS1# 1 2 43 44
19 IDE_PDCS1# +5VHDD R233 100K_0402_5% 43 44
45 46 +3VS
IDE_PDCS3# PD_PDCS3# GNDGND PD_D7
19 IDE_PDCS3# 1 2 47 GNDGND 48 1 2

2
R232 0_0402_5% R251 10K_0402_1%
SUYIN_200021FB044G219ZL_RV R246 @
@ 4.7K_0402_5% 2 1 PD_PDDREQ
R253 5.6K_0603_1%
@

1
1 2 PD_PDIORDY
IDE_PDD[0..15] 19 IDE_PDIORDY R248 0_0402_5%
19 IDE_PDD[0..15]
INT_IRQ14 1 2 PD_IRQ14
19 INT_IRQ14 R234 0_0402_5%

1 2
R235 8.2K_0402_5% B+_BIAS
@ +5VS +5VODD
Q50

D
+3VS 6 F4

S
1
5 4 +5VS_ODD 1 2
R481 2 SI3456BDV-T1-E3_TSOP6

1
470K_0402_5% 1 3A_6VDC_2920SMD300
1

G
5
U55 R1009

3
ODD_LED# 2 C905 100K_0402_5%

P
B 0.1U_0402_16V4Z
4

2
PHDD_LED# Y IDE_LED# 32 2
1 A

1
D
1
NC7SZ08P5X_NL_SC70-5 2 Q51
18 ODD_EN#

3
G 2N7002_SOT23 C906
S 0.1U_0603_50V4Z

3
2

IDE_SDD7 1 8 SD_D7
IDE_SDD6 2 7 SD_D6
IDE_SDD5 3 6 SD_D5
IDE_SDD4 4 5 SD_D4 IDE_SDD[0..15]
19 IDE_SDD[0..15]
RP47 0_1206_8P4R_5%
IDE_SDD3 1 8 SD_D3 +5VODD
IDE_SDD2 2 7 SD_D2
IDE_SDD1 SD_D1 JODD1
3 6
IDE_SDD0 4
RP48
5 SD_D0
0_1206_8P4R_5% SD_D0
STORAGE +5VODD C367 C368
1
C370 C371
B10 HD00 VBPOWER A1
IDE_SDIOW# 1 8 SD_SDIOW# SD_D1 A10 A2 +5VS C369
19 IDE_SDIOW# HD01 VBPOWER
IDE_SDA1 2 7 SD_SDA1 SD_D2 B9 B1 R500 1000P_0402_50V7K~N 4.7U_0805_10V4Z 1U_0603_10V4Z 4.7U_0805_10V4Z
19 IDE_SDA1 HD02 VBPOWER 2
IDE_SDA0 3 6 SD_SDA0 SD_D3 A9 B2 10K_0402_5%
19 IDE_SDA0 HD03 VBPOWER
IDE_SDA2 4 5 SD_SDA2 SD_D4 B8 A28 0.1U_0402_16V4Z
19 IDE_SDA2 HD04 VBPOWER

1
RP49 0_1206_8P4R_5% SD_D5 A8 B28 R501 Place component's closely MODULE CONNECTOR.
SD_D6 HD05 VBPOWER 10K_0402_5%
B7 HD06
IDE_SDD9 1 8 SD_D9 SD_D7 A7 R502
IDE_SDD10 SD_D10 SD_D8 HD07 10K_0402_5% R503 10K_0402_5%
2 7 B6 HD08
IDE_SDCS1# 3 6 SD_SDCS1# SD_D9 A6
19 IDE_SDCS1#

2
IDE_SDCS3# SD_SDCS3# SD_D10 HD09 BAY_TYPE
19 IDE_SDCS3# 4 5 B5 HD10 BAYDET1 B22 BAY_TYPE 31
RP50 0_1206_8P4R_5% SD_D11 A5 B21 BAY_ID1 +3VS
IDE_SDD11 SD_D11 SD_D12 HD11 BAYID1 BAY_ID2 BAY_ID1 18
1 8 B4 HD12 BAYID2 A21 BAY_ID2 18

2
IDE_SDD12 2 7 SD_D12 SD_D13 A4 A20 BAY_ID3
IDE_SDD13 SD_D13 SD_D14 HD13 BAYID3 BAY_ID3 18 R247
3 6 B3 HD14
IDE_SDD14 4 5 SD_D14 SD_D15 A3 A25 @ 4.7K_0402_5%
RP51 0_1206_8P4R_5% HD15 AUXR
AUXL B25 1
IDE_SDD15 1 8 SD_D15 2 1 B15

1
IDE_SDDREQ SD_SDDREQ R239 470_0805_5% CSEL C1017 SD_SDIORDY
19 IDE_SDDREQ 2 7 B14 CSEL# 19 IDE_SDIORDY 1 2
IDE_SDIOR# 3 6 SD_SDIOR# SD_SDCS1# A13 A22 1000P_0402_50V7K~N R249 0_0402_5%
19 IDE_SDIOR# CS0 NC 2
IDE_SDDACK# 4 5 SD_SDDACK# SD_SDCS3# B12
19 IDE_SDDACK# CS1
RP52 0_1206_8P4R_5% A11
SD_SDA0 GND
A14 SA0 GND B11
IDE_SDD8 1 2 SD_D8 SD_SDA1 A15 A23
R240 0_0402_5% SD_SDA2 SA1 GND SD_D7
B13 SA2 GND B23 1 2
CSE- H: Master, L/NC:Slave A27 R250 10K_0402_5%
GND
GND B27 @
1 2 ODD_LED# A12 A29 2 1 SD_SDDREQ
+5VS R236 8.2K_0402_5% SD_IRQ15 DASP GND R252 5.6K_0603_1%
A16 IRQ GND B29
+3VS B16 A30
PDIAG GND @
INT_IRQ15 1 2 SD_IRQ15 SD_SDIORDY A17 B30
19 INT_IRQ15 R241 0_0402_5% SD_SDIOR# IOCHRDY GND
A18 IOR
1

SD_SDIOW# A19 A24


R992 IOW AGND
1 2 B17 IOCS16 AGND B24 1
R242 8.2K_0402_5% 10K_0402_5% SD_SDDACK# B18 A26
SD_SDDREQ DMACK AGND C1018
@ B19 DMARQ AGND B26 BAY TYPE- 0:Storage Device
D42 B20 1 1000P_0402_50V7K~N
1:2nd BATT or No pack
2

RESET# 2

18 ODD_RST# 1 2 USB
D2 USBDET1 TVPOWER12 D1
2 C1019
MODE BAY_ID3/2/1
RB751V_SOD323 1000P_0402_50V7K~N
TVPOWER5 C3 Not Used 000
VBPOWER C1
C7 USBP0+ VBPOWER C2 CD-ROM 001 IDE
C9 USBP0-
GND C6 CD-RW 010 IDE
GND C8
GND C10 Combo 011 IDE
C4 NC GND D6
C5 NC GND D7 DVD-ROM 100 IDE
D3 NC GND D8
D4 NC GND D9 DVD-RAM 101 IDE
D5 NC GND D10
2nd HDD 110 IDE
TYCO_1827257-1~N
Reserved 111 IDE
Compal Electronics, Inc.
Title
SCHEMATIC, M/B LA-2642P
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401380 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: 星 薑? 七月 29, 2005 Sheet 22 of 48
+USB_BS=60 mils
+5VS +USB_AS L37
L36 JUSBP1
0.1U_0402_16V4Z 4 3 1 5 2 1
4 3 USB_P0- VCC VCC USB_P1- 2 1
1 1 18 USBP0- 2 D0- D1- 6 USBP1- 18
U15 USB_P0+ 3 7 USB_P1+
80 mils 1 GND OUT 8 + C377 C381 + 18 USBP0+
1 1 2 2 4
D0+ D1+
VSS VSS 8 3 3 4 4
USBP1+ 18
2 IN OUT 7 150U_D2_6.3VM
3 6 C379 WCM2012F2S-900T04_0805 10 9 WCM2012F2S-900T04_0805
SUSP IN OUT 2 2 G2 G1
1 33,39,40 SUSP 4 EN# OC# 5 12 G4 G3 11
C380
TPS2061DGNG4_MSOP8~N @ 150U_D2_6.3VM SUYIN_020122MR008G570ZL~N
0.1U_0402_16V4Z
2 C384 C385 C382 C383
@ 2.2P_0402_50V8C @ 2.2P_0402_50V8C
1 2 USB_OC0# 18
R1000
1 0_0402_5%
2
R999 0_0402_5% USB_OC1# 18
@ 2.2P_0402_50V8C
@ 2.2P_0402_50V8C

1
R46 +USB_BS
30K_0402_5%

L45 JUSBP3

2
4 4 3 3 1
USB_P3-
18 USBP3- 2

1
D USB_P3+
18 USBP3+ 3
SUSP 2 Q4 1 2 1 1
G 2N7002_SOT23 1 2 4
S WCM2012F2S-900T04_0805 @C393 @ C394 SUYIN_020133MR004S529ZL~N

3
2.2P_0402_50V8C 2.2P_0402_50V8C
2 2

+USB_BS

+5VS +USB_BS
0.1U_0402_16V4Z
1 1 L44 JUSBP2
U16 1 1 2
80 mils 1 GND OUT 8 + C387 + @C386 C388
18 USBP2-
2 USB_P2- 1
2
2 7 150U_D2_6.3VM USB_P2+
IN OUT 18 USBP2+ 3
3 6 150U_D2_6.3VM 4 3 1 1
SUSP IN OUT 2 2 4 3 4
1 4 EN# OC# 5
C390 WCM2012F2S-900T04_0805 @C391 @C392 SUYIN_020133MR004S529ZL~N
TPS2061DGNG4_MSOP8~N 2.2P_0402_50V8C 2.2P_0402_50V8C
0.1U_0402_16V4Z 2 2
2
1 2 USB_OC2# 18
R1001
1 0_0402_5%
2
R1002 0_0402_5% USB_OC3# 18

1
R1
30K_0402_5%

FINGERPRINT

2
1
D +5VS
SUSP 2 Q12 F5 1.1A_6VDC_FUSE JP19
G 2N7002_SOT23 1 2 +5VS_FP 1 1
S 18 USBP4- 2

3
2
18 USBP4+ 3 3
4 4
JST_BM04B-SRSS~N

BLUETOOTH

200mA
JP10
1
2
31 BT_EXIST# 3
4
5
6
24 BT_ACTIVE 7
31 BT_DIS# 8
9
10
11
12
13
14
15
18 USBP6+ 16
18 USBP6- 17
24 WL_ACTIVE 18
19
+3VS 1 2 +3VS_BT 1 2 BT_PWR 20
L26 1
BLM11A601S_0603 F6 1.1A_6VDC_FUSE ACES_87151-2007L~N
C395
0.1U_0402_16V4Z
2

Compal Electronics, Inc.


Title
SCHEMATIC, M/B LA-2642P
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
401380
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: 星期五, 七月 29, 2005 Sheet 23 of 48
+3VS

1 2 WLAN_SKILL#
@ R1021 10K_0402_5%
1 2 WLAN_LINK
R1020 10K_0402_5%
1 2 WLAN_ACT
@R1019 10K_0402_5%
PCI_AD[0..31]
PCI_AD[0..31] 17,27

JP11
TIP 1 2
1 2 RING
3 3 4 4
5 5 6 6
LAN RESERVED 7 8
D18 CH751H-40_SC76 7 8 LAN RESERVED
9 9 10 10
WLAN_LINK 11 12 WLAN_ACT
32 WLAN_LINK WLAN_SKILL# 11 12 WLAN_ACT 32
31,32 WL_OFF# 1 2 13 13 14 14
15 15 16 16
17 18 W=30mils
17,27 PCI_PIRQG# W=40mils 17 18 +5VS
+3VS 19 19 20 20 PCI_PIRQF# 17,27
21 21 22 22
23 23 24 24 +3V
CLK_PCI_MINI 25 26
17 CLK_PCI_MINI 25 26 PCIRST_MINI# 17 W=40mils
27 27 28 28 +3VS
17 PCI_REQ#3 29 29 30 30 PCI_GNT#3 17
31 31 32 32
PCI_AD31 33 34
PCI_AD29 33 34 WLAN_PME# 31
35 35 36 36 0_0402_5% @R238
BT_ACTIVE 23
37 38 PCI_AD30
PCI_AD27 37 38
39 39 40 40
PCI_AD25 41 42 PCI_AD28
@R237 0_0402_5% 41 42 PCI_AD26
23 WL_ACTIVE 43 43 44 44
45 46 PCI_AD24
17,27 PCI_C/BE#3 45 46
PCI_AD23 47 48 MINI_IDSEL1 2 PCI_AD18 IDSEL : PCI_AD18
47 48 R262 100_0402_1%
49 49 50 50
PCI_AD21 51 52 PCI_AD22
PCI_AD19 51 52 PCI_AD20
53 53 54 54
55 55 56 56 PCI_PAR 17,27
PCI_AD17 57 58 PCI_AD18
57 58 PCI_AD16
17,27 PCI_C/BE#2 59 59 60 60
17,27 PCI_IRDY# 61 61 62 62
63 63 64 64 PCI_FRAME# 17,27
17,27,31 PCI_CLKRUN# 65 65 66 66 PCI_TRDY# 17,27
17,27 PCI_SERR# 67 67 68 68 PCI_STOP# 17,27
69 69 70 70
17,27 PCI_PERR# 71 71 72 72 PCI_DEVSEL# 17,27
17,27 PCI_C/BE#1 73 73 74 74
PCI_AD14 75 76 PCI_AD15
75 76 PCI_AD13
77 77 78 78
PCI_AD12 79 80 PCI_AD11
PCI_AD10 79 80
81 81 82 82
83 84 PCI_AD9
PCI_AD8 83 84
85 85 86 86 PCI_C/BE#0 17,27
CLK_PCI_MINI PCI_AD7 87 88
87 88 PCI_AD6
89 89 90 90
1

PCI_AD5 91 92 PCI_AD4
R263 91 92 PCI_AD2
93 93 94 94
10_0402_5% PCI_AD3 95 96 PCI_AD0
W=30mils 95 96
+5VS 97 97 98 98
PCI_AD1 99 100
2

99 100
101 101 102 102
1 103 103 104 104
105 105 106 106
C396 107 108
22P_0402_25V8K 107 108
109 109 110 110
2
111 111 112 112
113 113 114 114
115 115 116 116
117 117 118 118
119 119 120 120
121 121 122 122
W=30mils 123 124 W=20mils
+5VS 123 124 +3V
2
125 GND GND 126
C397
AMP_1470484-1 0.1U_0402_16V4Z
1

+5VS
2 2 1
C399 C400 C402

0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z


1 1 2

+3VS Compal Electronics, Inc.


2 2 2 2 2 1 1 1
C403 C404 C405 C406 C407 Title

0.047U_0402_16V4Z 0.047U_0402_16V4Z 0.047U_0402_16V4Z 0.047U_0402_16V4Z 0.047U_0402_16V4Z


C408 C1003
0.047U_0402_16V4Z
C1004
0.047U_0402_16V4Z SCHEMATIC, M/B LA-2642P
1 1 1 1 1 2 2 2 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
401380
0.047U_0402_16V4Z B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: 星期五, 七月 29, 2005 Sheet 24 of 48
5 4 3 2 1

MMJT9435
C
2 Layout Notice : 3.3V filter. Place as close Layout Notice : 1.2V filter. Place as close
Layout Notice : Place as close chip as possible. chip as possible.
chip as possible.
B C E +3VS +1.2VLAN
+3VALW Q42 L27 +3VLAN +3VLAN
1 4 3 +3VLAN

D
6 FBM-L11-321611-260-LMT_1206

1_1210_5%

0.1U_0402_16V4Z

4.7U_0805_10V4Z
5 4 +3V_LAN 1 2

4.7U_0805_6.3V6K
R264

4.7U_0805_10V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
2 SI3456BDV-T1-E3_TSOP6 2 2

C414

C415
4.7U_0805_10V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
1 2 2 2 2 1 2 2 2 2 2 2 2 2 2 2
2 2 2 2
G

C416

C417

C418

C419

C420

C421

C422

C423

C424

C425

C426

C427

C428

C429

C430
D D
3

1
1 1

C409

C410

C411

C412

C413
1 1 1 1 2 1 1 1 1 1 1 1 1 1 1

Z4011
33 EN_WOL 1 1 1 1

3
Q13
+3VLAN
REGCTL_PNP 1
+1.2VLAN
+3VLAN
MMJT9435T1G_SOT223

2
4
R265 1 2 30K_0402_5% R_CLK_PCI_LAN Pin L9, if TPM supported, Pull down +1.2VLAN
+1.2VLAN Notice : 4.7u 6.3V capactor Thickness 1.25mm

10U_0805_10V4Z~N
R267 1 2 30K_0402_5% R_LPC_AD0 via 4.7K resister. L09 floating to

0.1U_0402_16V4Z
R266 1 2 30K_0402_5% R_LPC_AD1
disable TPM function.
R268 1 2 30K_0402_5% R_LPC_AD2 2 2 Layout Notice : Filter place as close

C432

C431
chip as possible. +1.2VLAN U17B
Pin L06:Low Power Mode
R270 1 2 30K_0402_5% R_LPC_AD3
Driven High-IDDQ Mode(less than 20mA)
Driven Low-Normal Mode
1 1 +2.5VLAN B8 VDDC_0
BCM5751M
R269 1 2 30K_0402_5% R_LPC_FRAME# E5 B4
R271 30K_0402_5% R_PLT_RST# VDDC_1 VSS_0
1 2 E6 VDDC_2 VSS_1 B7
R272 1 2 30K_0402_5% R_SIRQ E7 B12
VDDC_3 VSS_2

0.1U_0402_16V4Z

0.1U_0402_16V4Z
U17A E8 E2
VDDC_4 VSS_3
E9 F6
BCM5751M 2 2 VDDC_5 VSS_4

C435

C433
E10 VDDC_6 VSS_5 F7
R_CLK_PCI_LAN K10 E13 LAN_TX3+ F5 F8
LCLK TRD3+ LAN_TX3+ 26 VDDC_7 VSS_6
R_LPC_AD0 M11 E14 LAN_TX3- F10 F9
LAD0 TRD3- LAN_TX3- 26 1 1 VDDC_8 VSS_7
BroadSAFE

R_LPC_AD1 L11 D13 LAN_TX2+ G4 G5


LAD1 TRD2+ LAN_TX2+ 26 VDDC_9 VSS_8
R_LPC_AD2 LAN_TX2-
Media
K9 LAD2 TRD2- D14 LAN_TX2- 26 J5 VDDC_10 VSS_9 G6
R_LPC_AD3 L5 LAD3 TRD1+ C13 LAN_RX1+
LAN_RX1+ 26 Layout Notice : Place as close J10 VDDC_11 VSS_10 G7
C R_LPC_FRAME# LAN_RX1- C
R_PLT_RST#
H11 LFRAME TRD1- C14
LAN_TX0+
LAN_RX1- 26 chip as possible. K5 VDDC_12 VSS_11 G8
M9 LRESET TRD0+ B13 LAN_TX0+ 26 K6 VDDC_13 VSS_12 G9
R_SIRQ L8 B14 LAN_TX0- K7 G10
SERIRQ TRD0- LAN_TX0- 26 +2.5VLAN VDDC_14 VSS_13
1 2 L9 EXPORT K8 VDDC_15 GND VSS_14 H5
@ R273 J11 K4 H6
+3VLAN 4.7K_0402_5% BSAFE_GPIO0 VDDC_16 VSS_15
N13 BSAFE_GPIO1 LOW_PWR L6 LAN_LOW_PWR 31 J4 VDDC_17 VSS_16 H7
@ R274 H8
VSS_17

0.1U_0402_16V4Z

22U_1206_10V4Z

22U_1206_10V4Z

22U_1206_10V4Z
4.7K_0402_5%
Control

1 2 VMAIN_ON N14 +3VLAN D11 VDDIO_0 VSS_18 H9


Layout Notice : Filter place as close
Power

VAUX_ON M13 2 2 2 2 G11 VDDIO_1 VSS_19 H10

C436

C434

C437

C438
@ R275
chip as possible. K12 VDDIO_2 VSS_20 J6
1 2 0_0402_5% G12 GPIO0_TST_CLKOUT PERST C2 NB_RST# 9,17,18,42 VSS_21 J7
H13 GPIO1 1 1 1 1 Digial power VSS_22 J8
SMBus to support ASF G13 +2.5VLAN A7 J9
GPIO2 +3VS VDDIO-PCI_0 VSS_23
D10 K14 +3VLAN B3 K2
26 LAN_SMBCLK SMB_CLK REGSUP12 VDDIO-PCI_1 VSS_24
Msic

D9 J13 REGCTL 1 2 REGCTL_PNP 2 1 XTALVDD C5 N1


26 LAN_SMBDATA SMB_DATA REGCTL12 VDDIO-PCI_2 VSS_25
R277 0_0402_5% +1.2VLAN L28 FBM-L11-160808-601LMT_0603
Regulator

K11 EECLK REGSEN12 J14 2 E1 VDDIO-PCI_3 VSS_26 N9


Control

1 2 L10 EEDATA E4 VDDIO-PCI_4 VSS_27 P9


R276 5751_SI E12 C439 G1
@ 4.7K_0402_5% SCLK SI 0.1U_0402_16V4Z VDDIO-PCI_5
E11 M14 K3
5751_SO F11
SCLK REGOUT25 +2.5VLAN 1
L4
VDDIO-PCI_6
CS# SO +3VLAN VDDIO-PCI_7
C12 CS REGSUP25 L14 +3VLAN P2 VDDIO-PCI_8 NC_0 K13
NC_1 L7
2 1 +LAN_AVDD +2.5VLAN A8 VDDP_0 NC_2 L12
C440 L29 FBM-L11-160808-601LMT_0603
2 D5 L13
VDDP_1 NC_3

0.1U_0402_16V4Z

4.7U_0805_10V4Z
0.1U_0402_16V4Z P13 M10
PCIE_MRX_C_LTX_N0 1 C441 VDDP_2 NC_4
PCIE_TXDN P6 2 PCIE_MRX_LTX_N0 9 2 2 NC_5 N11
Support
Hot Plug

C443

C444
+3VS 0.1U_0402_16V4Z XTALVDD H14 P11
PCIE_MRX_C_LTX_P0 1 1 XTALVDD NC_6
H2 PWR_IND PCIE_TXDP N6 2 PCIE_MRX_LTX_P0 9 +3VLAN M12 WOL_VAUX

1
J2 C442 P14 @ R1030
R278 1 ATTN_IND 1 1 WOL_INRSH_ON
2 4.7K_0402_5% A2 ATTN_BTTN PCIE_RXDN N10 0.1U_0402_16V4Z
PCIE_MTX_C_LRX_N0 9 PCIE_SDS_VDD M6 PCIE_SDS_VDD
4.7K_0402_5%
PCI-E

PCIE_RXDP P10 PCIE_MTX_C_LRX_P0 9 2 1 +LAN_AVDD1 DC_0 A3


B L30 FBM-L11-160808-601LMT_0603 B
2 AVDDL F12 A4

2
AVDDL_0 DC_1
WAKE A6 PCIE_PME# 18,31 F13 AVDDL_1 Analog DC_2 A5
P8 C445 +LAN_AVDD A13 B1
REFCLK- CLK_PCIE_LAN# 16 AVDD_0 power DC_3
N8 0.1U_0402_16V4Z +LAN_AVDD1 F14 B2 +3VS
REFCLK+ CLK_PCIE_LAN 16 1 AVDD_1 DC_4
A11 LINKLED DC_5 B5
B11 J12 LAN_AUXPWR 1 2 +1.2VLAN M8 B6
SPD100LED VAUXPRSNT +3VLAN PCIE_PLLVDD PCIE_PLLVDD DC_6
A12 D8 R279 G14 PLL C1
SPD1000LED TST GPHY_PLLVDD GPHY_PLLVDD DC_7
LED

B10 4.7K_0402_5% 2 1 AVDDL C3


TRAFFICLED L31 FBM-L11-160808-601LMT_0603 DC_8
2 2 DC_9 C4
1
4.7K_0402_5%

+3VS P1 VESD1 DC_10 C6


R280

A9 D7 C446 C447 G2 C7
WL_ACTIVITY TCK 4.7U_0805_6.3V6K 0.1U_0402_16V4Z VESD2 DC_11
B9 WL_LINK5G TDI H12
1 1
A1 VESD3 Clamp DC_12 C8
TEST

C10 WL_LINK2.4G TDO D6 DC_13 C9


C11 L3 D1
2

TMS DC_31 DC_14


TRST D12 M1 DC_32 DC_15 D2
2 1 GPHY_PLLVDD M2 DC_33 DC_16 D3
2
4.7K_0402_5%

L32 FBM-L11-160808-601LMT_0603
2 2 M3 D4
DC_34 DC_17
R281

XTALI P12 M4 E3
XTALI DC_35 DC_18
Clock

XTALO N12 C448 C449 T8 PAD M5 F1


XTALO 4.7U_0805_6.3V6K 0.1U_0402_16V4Z DC_36 DC_19
M7 DC_37 DC_20 F2
R282 1 1
Bias

A10 N2 F3
1

RDAC +2.5VLAN PAD DC_38 DC_21


+3VS 1 2 F4 REFCLK_SEL N3 DC_39 Don't care DC_22 G3
+3VLAN N4 H1
4.7K_0402_5% DC_40 DC_23
2

4.7K_0402_5%

2 1 PCIE_PLLVDD T7 N5 H3
DC_41 DC_24

1
R283 @

1.24K_0402_1%

L33 FBM-L11-160808-601LMT_0603
2 2 N7 H4
DC_42 DC_25
2

BCM5751MKFBG_FPBGA196 P3 J1
DC_43 DC_26
1K_0402_5%
R284

C451 L34 P4 J3
DC_44 DC_27
1K_0402_5%

C450 0.1U_0402_16V4Z FBM-L11-160808-601LMT_0603 P5 K1


1

DC_45 DC_28
1
1

1 1
Layout Notice : No high 4.7U_0805_6.3V6K P7 DC_46 DC_29 L1
R285

R287

speed signal should be L2


1

2
R286 LAN_VBIAS A14 DC_30
routed near RDAC or on BIASVDD BIAS
200_0603_1% +3VLAN 2 1 PCIE_SDS_VDD 1
A
2 1 XTALO adjacent layer to RDAC U18 L55 FBM-L11-160808-601LMT_0603
1 2
A
2
2

5751_SI 8 1 5751_SO C454 BCM5751MKFBG_FPBGA196


SO SI
0.1U_0402_16V4Z

XTALI 7 2 SCLK @ C452 C453 @ 0.1U_0402_16V4Z


Y4 GND SCK 4.7U_0805_6.3V6K 0.1U_0402_16V4Z 2
6 VCC RESET# 3 +3VLAN 2 1
27P_0402_50V8J

27P_0402_50V8J

1 2 5 4 CS#
WP# CS#
2
C457

2 25MHZ_16P_XSL025000FK1H 2 AT45DB011B-SU_SO8~N
Compal Electronics, Inc.
C455

C456

No CIS Symbol
1 Title
1 1
SCHEMATIC, M/B LA-2642P
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
401380
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: 星期五, 七月 29, 2005 Sheet 25 of 48
5 4 3 2 1
5 4 3 2 1

D D

+2.5VLAN 1 2 V_DAC
R289
0_0805_5%

T6 RP53
C458 1 2 0.1U_0402_16V4Z V_DAC 1 24 1 8 C461
TCT1 MCT1 1000P_1206_2KV7K
2 7
LAN_TX3+ 2 1:1 23 RJ45_TX3+ 3 6
25 LAN_TX3+ TD1+ MX1+
4 5 2 1

75_1206_8P4R_5%

LAN_TX3- 3 22 RJ45_TX3-
25 LAN_TX3- TD1- MX1-
C459 1 2 0.1U_0402_16V4Z V_DAC 4 21
TCT2 MCT2
LAN_TX2+ 5 1:1 20 RJ45_TX2+
25 LAN_TX2+ TD21+ MX2+

LAN_TX2- 6 19 RJ45_TX2- JLAN1


25 LAN_TX2- TD2- MX2-
C RJ45_TX0- 2 C
C460 1 V_DAC PR1-
2 0.1U_0402_16V4Z 7 TCT3 MCT3 18
RJ45_TX0+ 1
LAN_RX1+ 1:1 PR1+
25 LAN_RX1+ 8 TD3+ MX3+ 17 RJ45_RX1+
RJ45_RX1+ 3 PR2+
RJ45_TX2+ 4 PR3+
LAN_RX1- 9 16 RJ45_RX1- RJ45_TX2- 5
25 LAN_RX1- TD3- MX3- PR3-
C462 1 2 0.1U_0402_16V4Z V_DAC 10 15 RJ45_RX1- 6
TCT4 MCT4 PR2-
LAN_TX0+ 11 1:1 14 RJ45_TX0+ RJ45_TX3+ 7
25 LAN_TX0+ TD4+ MX4+ PR4+
SHLD1 9
RJ45_TX3- 8 10
PR4- SHLD2
ALLTO_C10091-108A4-L~N
LAN_TX0- 12 13 RJ45_TX0-
25 LAN_TX0- TD4- MX4-
24HST1041A-3-LF_24P
Layout Note
24HST1041A-3 pls close to conn.

R293 49.9_0402_1%C463 0.1U_0402_16V4Z


LAN_TX0+ +3VLAN
1 2 1 2 10K_0402_5%

10K_0402_5%
1 1 2

1
R294 49.9_0402_1%
LAN_TX0- 1 2 C464 0.1U_0402_16V4Z
B B
R295

R296
1 2 1 2
R297 49.9_0402_1%C466 0.1U_0402_16V4Z R476 0_0402_5%
2

2
LAN_RX1+ 1 2 1 2 Q14 @ @ C465 0.1U_0402_16V4Z
S

@ 2N7002_SOT23 3 1 LAN_SDATA
13,14,16,18 SB_SMDATA LAN_SMBDATA 25
R298 49.9_0402_1% 1 2
LAN_RX1- 1 2
C467 0.1U_0402_16V4Z
G
2

R299 49.9_0402_1%C468 0.1U_0402_16V4Z +3VS 1 2


LAN_TX2+ 1 2 1 2
C469 0.1U_0402_16V4Z
2
G

R300 49.9_0402_1%
LAN_TX2- 1 2 Q15
@ 2N7002_SOT23 3 1 LAN_SCLK
13,14,16,18 SB_SMCLK LAN_SMBCLK 25
R301 49.9_0402_1%C470 0.1U_0402_16V4Z
S

LAN_TX3+ 1 2 1 2

R302 49.9_0402_1% 1 2
LAN_TX3- 1 2 0_0402_5%
R475

All 49.9 ohm + 0.1 uF


termination components close
to BCM5751M

A A

Compal Electronics, Inc.


Title
SCHEMATIC, M/B LA-2642P
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401380 B

Date: 星期五 , 七月 29, 2005 Sheet 26 of 48


5 4 3 2 1
5 4 3 2 1

CBS_BCAD[0..31] CBS_ACAD[0..31]
CBS_BCAD[0..31] 28 CBS_ACAD[0..31] 28
+3V U19A

CBS_BCAD31 N6 C18 CBS_ACAD31


CBS_BCAD30 BCAD31/D10 ACAD31/D10 CBS_ACAD30
M2 BCAD30/D9 ACAD30/D9 D19
+3VS

10U_0805_10V4Z~N

0.01U_0402_16V7K

0.01U_0402_16V7K

0.01U_0402_16V7K
CBS_BCAD29 M3 D18 CBS_ACAD29
Z3008 CBS_BCAD28 BCAD29/D1 ACAD29/D1 CBS_ACAD28
M5 BCAD28/D8 ACAD28/D8 D17
U19B 1 1 1 1 CBS_BCAD27 L1 E18 CBS_ACAD27
BCAD27/D0 ACAD27/D0

1
C471

C472

C473

C474

5.1K_0402_1%
R254 56.2_0603_1%
W7 F7 CBS_BCAD26 L3 F18 CBS_ACAD26
+3V VCC_PCI1 VCC_3V4 BCAD26/A0 ACAD26/A0

56.2_0603_1%
P10 J19 1 CBS_BCAD25 L6 F15 CBS_ACAD25
VCC_PCI2 VCC_3V3 BCAD25/A1 ACAD25/A1

1
1 2 P11 K19 CBS_BCAD24 K2 G18 CBS_ACAD24
VCC_PCI3 VCC_3V2 2 2 2 2 BCAD24/A2 ACAD24/A2

R256
10U_0805_10V4Z~N C632 F8 C374 CBS_BCAD23 K5 G15 CBS_ACAD23
VCC_3V1 270P_0402_50V7K~N CBS_BCAD22 BCAD23/A3 ACAD23/A3 CBS_ACAD22
1 2 M6 J1 H18

2
0.01U_0402_16V7K C631 VCC_RIN1 2 CBS_BCAD21 BCAD22/A4 ACAD22/A4 CBS_ACAD21
F19 VCC_RIN2 VCC_MD A8 J3 BCAD21/A5 ACAD21/A5 H15
+2.5V_CORE H1 CBS_BCAD20 J6 J18 CBS_ACAD20

2
D VCC_ROUT1 BCAD20/A6 ACAD20/A6 D
G14 E11 CBS_BCAD19 H3 J17 CBS_ACAD19
VCC_ROUT2 AVCC_PHY1/NC +3V_PHY BCAD19/A25 ACAD19/A25

R255
R303 2 1 E19 E13 CBS_BCAD18 H2 J15 CBS_ACAD18
100K_0402_5% REG_EN# AVCC_PHY2/NC CBS_BCAD17 BCAD18/A7 ACAD18/A7 CBS_ACAD17
AVCC_PHY3/NC A18 H5 BCAD17/A24 ACAD17/A24 J14
B18 CBS_BCAD16 D2 N15 CBS_ACAD16
PCI_AD31 AVCC_PHY4/NC CBS_BCAD15 BCAD16/A17 ACAD16/A17 CBS_ACAD15
V3 AD31 C1 BCAD15/IOWR# ACAD15/IOWD# N19
PCI_AD30 W3 CBS_BCAD14 B1 P19 CBS_ACAD14
PCI_AD29 AD30 IEEE1394_TPBIAS0 CBS_BCAD13 BCAD14/A9 ACAD14/A9 CBS_ACAD13
U4 AD29 TPBIAS0/NC C13 IEEE1394_TPBIAS0 C2 BCAD13/IORD# ACAD13/IORD# N18
PCI_AD[0..31] PCI_AD28 V4 A14 IEEE1394_TPBN0 CBS_BCAD12 A2 P18 CBS_ACAD12
17,24 PCI_AD[0..31] AD28 TPBN0/NC IEEE1394_TPBN0 28 BCAD12/A11 ACAD12/A11
PCI_AD27 W4 B14 IEEE1394_TPBP0 CBS_BCAD11 A3 P17 CBS_ACAD11
PCI_AD26 AD27 TPBP0/NC IEEE1394_TPAN0 IEEE1394_TPBP0 28 CBS_BCAD10 BCAD11/OE# ACAD11/OE# CBS_ACAD10
U5 AD26 TPAN0/NC A13 IEEE1394_TPAN0 28 B3 BCAD10/CE2# ACAD10/CE2# R19
PCI_AD25 V5 B13 IEEE1394_TPAP0 CBS_BCAD9 C3 R18 CBS_ACAD9
PCI_AD24 AD25 TPAP0/NC IEEE1394_TPAP0 28 CBS_BCAD8 BCAD9/A10 ACAD9/A10 CBS_ACAD8
W5 AD24 B4 BCAD8/D15 ACAD8/D15 R17

1
PCI_AD23 V6 C11 CBS_BCAD7 B5 T17 CBS_ACAD7
+2.5V_CORE PCI_AD22 AD23 TPBIAS1/NC R257 R258 CBS_BCAD6 BCAD7/D7 ACAD7/D7 CBS_ACAD6

PCI / MISC / 1394_OHCI PORTION


W6 AD22 TPBN1/NC A12 C5 BCAD6/D13 ACAD6/D13 U19
0.01U_0402_16V7K

0.47U_0603_10V7K

0.47U_0603_10V7K

PCI_AD21 P7 B12 56.2_0402_1% 56.2_0402_1% CBS_BCAD5 A5 U18 CBS_ACAD5


AD21 TPBP1/NC BCAD5/D6 ACAD5/D6
0.01U_0402_16V7K

1 PCI_AD20 R7 A11 CBS_BCAD4 E5 V19 CBS_ACAD4


PCI_AD19 AD20 TPAN1/NC +3V_PHY CBS_BCAD3 BCAD4/D12 ACAD4/D12 CBS_ACAD3
1 1 1 U7 B11 C6 W18

CARDBUS / MEDIA CARD PORTION


2

2
AD19 TPAP1/NC BCAD3/D5 ACAD3/D5
C476

C477

C478

C479

PCI_AD18 V7 CBS_BCAD2 E6 V18 CBS_ACAD2


PCI_AD17 AD18 CBS_BCAD1 BCAD2/D11 ACAD2/D11 CBS_ACAD1
P8 AD17 CPS/NC C12 F6 BCAD1/D4 ACAD1/D4 W17
2 PCI_AD16 CBS_BCAD0 CBS_ACAD0
2 2 2
R8 AD16 1 1 0.33U_0603_10V7K E7 BCAD0/D3 ACAD0/D3 U17
PCI_AD15 R11 C14 2 1 C376
PCI_AD14 AD15 VREF/NC C480 0.01U_0402_16V7K CBS_BCCBE3# CBS_ACCBE3#
U11 AD14 28 CBS_BCCBE3# K1 BCCBE3#/REG# ACCBE3#/REG# G19 CBS_ACCBE3# 28
PCI_AD13 V11 B15 2 1 CBS_BCCBE2# H6 K18 CBS_ACCBE2#
AD13 REXT/NC 2 2 28 CBS_BCCBE2# BCCBE2#/A12 ACCBE2#/A12 CBS_ACCBE2# 28
PCI_AD12 W11 R304 10K_0603_1% CBS_BCCBE1# D3 N14 CBS_ACCBE1#
AD12 28 CBS_BCCBE1# BCCBE1#/A8 ACCBE1#/A8 CBS_ACCBE1# 28
PCI_AD11 P12 A15 1 2 CBS_BCCBE0# A4 T19 CBS_ACCBE0#
AD11 FIL0/NC 28 CBS_BCCBE0# BCCBE0/CE1# ACCBE0#/CE1# CBS_ACCBE0# 28
PCI_AD10 R12 C481 C1002
PCI_AD9 AD10 0.01U_0402_16V7K 0.01U_0402_16V7K CBS_BCPAR CBS_ACPAR
U12 AD9 28 CBS_BCPAR D1 BCPAR/A13 ACPAR/A13 M14 CBS_ACPAR 28
PCI_AD8 V12 2 1 +3V
PCI_AD7 AD8 R305 100K_0402_5% CBS_BCFRAME# CBS_ACFRAME#
P13 AD7 28 CBS_BCFRAME# G3 BCFRAME#/A23 ACFRAME#/A23 K17 CBS_ACFRAME# 28
PCI_AD6 R13 P6 PCM_SPK# PCM_SPK# 30 CBS_BCTRDY# G6 K14 CBS_ACTRDY#
AD6 SPKROUT 28 CBS_BCTRDY# BCTRDY#/A22 ACTRDY#/A22 CBS_ACTRDY# 28
PCI_AD5 U13 CBS_BCIRDY# G5 K15 CBS_ACIRDY#
AD5 28 CBS_BCIRDY# BCIRDY#/A15 ACIRDY#/A15 CBS_ACIRDY# 28
PCI_AD4 V13 N1 CBS_BCSTOP# F3 L15 CBS_ACSTOP#
AD4 HWSPND# CBS_SPND# 31 28 CBS_BCSTOP# BCSTOP/A20 ACSTOP#/A20 CBS_ACSTOP# 28
PCI_AD3 W13 2 1 +3V CBS_BCDEVSEL# G1 L18 CBS_ACDEVSEL#
C AD3 28 CBS_BCDEVSEL# BCDEVSEL#/A21 ACDEVSEL#/A21 CBS_ACDEVSEL# 28 C
PCI_AD2 U14 R1 R306 10K_0402_5% SERIRQ 17,31 CBS_BCBLOCK# E1 M18 CBS_ACBLOCK#
AD2 UDIO0/SRIRQ# 28 CBS_BCBLOCK# BCBLOCK#/A19 ACBLOCK#/A19 CBS_ACBLOCK# 28
PCI_AD1 V14 CBS_BCPERR# E2 M17 CBS_ACPERR#
AD1 28 CBS_BCPERR# BCPERR#/A14 ACPERR#/A14 CBS_ACPERR# 28
PCI_AD0 W14 R2 CBS_BCSERR# K6 H19 CBS_ACSERR#
AD0 UDIO1 28 CBS_BCSERR# BCSERR#/WAIT# ACSERR#/WAIT# CBS_ACSERR# 28
SPKROUT: Pull-up disable Serial EEPROM. CBS_BCREQ# K3 G17 CBS_ACREQ#
28 CBS_BCREQ# BCREQ#/INPACK# ACREQ#/INPACK# CBS_ACREQ# 28
PCI_AD20 1 2 CBS_IDSEL U6 R3 CBS_BCGNT# F5 L14 CBS_ACGNT# CBS_ACGNT# 28
IDSEL UDIO2 28 CBS_BCGNT# BCGNT#/WE# ACGNT#/WE#
R307 100_0402_5% CBS_BCSTSCHNG L2 E17 CBS_ACSTSCHNG
28 CBS_BCSTSCHNG BCSTSCHG/BVD1_STSCHG# ACSTSCHG/BVD1_STSCHG# CBS_ACSTSCHNG 28
R6 R5 1 2 CBS_BCCLKRUN# N5 C19 CBS_ACCLKRUN#
17,24 PCI_C/BE#3 C/BE3# UDIO3 28 CBS_BCCLKRUN# BCCLKRUN#/WP ACCLKRUN#/WP CBS_ACCLKRUN# 28
U8 R308 10K_0402_5% 2 1 CBS_BCCLK_INTERNAL G2 L19 CBS_ACCLK_INTERNAL 2 1 CBS_ACCLK 28
17,24 PCI_C/BE#2 C/BE2# 28 CBS_BCCLK BCCLK/A16 ACCLK/A16
W10 P1 1 2 R310 22_0402_5% R311 22_0402_5%
17,24 PCI_C/BE#1 C/BE1# UDIO4
W12 R309 10K_0402_5% CBS_BCINT# F2 L17 CBS_ACINT#
17,24 PCI_C/BE#0 C/BE0# 28 CBS_BCINT# BCINT#/RDY_IREQ ACINT#/RDY_IREQ CBS_ACINT# 28
UDIO5 P2
PCI_PAR V10 CBS_BCRST# J2 H17 CBS_ACRST# CBS_ACRST# 28
17,24 PCI_PAR PAR 28 CBS_BCRST# BCRST#/RESET ACRST#/RESET
C482
+3V PCI_FRAME# V8 A17 R5C841XI 2 1 CBS_BCAUDIO L5 F17 CBS_ACAUDIO
17,24 PCI_FRAME# FRAME# XI/NC 28 CBS_BCAUDIO BCAUDIO/BVD2_SPKR# ACAUDIO/BVD2_SPKR# CBS_ACAUDIO 28
PCI_IRDY# W8
17,24 PCI_IRDY# IRDY#
PCI_TRDY# P9 B17 R5C841XO 16P_0603_50V8J CBS_BCRSV3/D2 M1 C17 CBS_ACRSV3/D2
17,24 PCI_TRDY# TRDY# XO/NC 28 CBS_BCRSV3/D2 BCRSV3/D2 ACRSV3/D2 CBS_ACRSV3/D2 28
1

PCI_DEVSEL# R9 CBS_BCRSV2/A18 E3 M15 CBS_ACRSV2/A18


17,24 PCI_DEVSEL# DEVSEL# 28 CBS_BCRSV2/A18 BCRSV2/A18 ACRSV2/A18 CBS_ACRSV2/A18 28

2
R312 PCI_STOP# U9 N2 Y5 CBS_BCRSV/D14 C4 T18 CBS_ACRSV/D14
17,24 PCI_STOP# STOP# TEST 28 CBS_BCRSVD/D14 BCRSV1/D14 ACRSV1/D14 CBS_ACRSVD/D14 28
100K_0402_5% PCI_PERR# R10 A10 24.576MHZ_16P_XSL024576FG1H
17,24 PCI_PERR# PCI_SERR# PERR# AGND1/GND CBS_BCCD1#_INTERNAL CBS_ACCD1#_INTERNAL
17,24 PCI_SERR# U10 SERR# AGND2/GND B10 C7 BCCD1/CD1# ACCD1/CD1# V17
C10 CBS_BCCD2#_INTERNAL N3 B19 CBS_ACCD2#_INTERNAL
2

AGND3/GND 1 BCCD2#/CD2# ACCD2/CD2#


CBS_GRST# W2 A16 C484 CBS_BCVS1 B2 N17 CBS_ACVS1
17 PCI_REQ#2 REQ# AGND4/GND 28 CBS_BCVS1 BCVS1/VS1# ACVS1/VS1# CBS_ACVS1 28
1 V2 B16 16P_0603_50V8J CBS_BCVS2 J5 H14 CBS_ACVS2
17 PCI_GNT#2 GNT# AGND5/GND 28 CBS_BCVS2 BCVS2/VS2# ACVS2/VS2# CBS_ACVS2 28
17 PCI_PIRQH# U3 INTD# AGND6/GND C15 2 1
C483 T1 B6 V16
17,24 PCI_PIRQG# INTC# BUSBDP AUSBDP
1U_0603_10V4Z 17,24 PCI_PIRQF# T2 INTB# GND1 F1 A6 BUSBDM AUSBDM W16
2
17 PCI_PIRQE# T3 INTA# GND2 V9
GND3 W9 28 BVPPEN1 P14 BVPPEN1 AVPPEN1 U16 AVPPEN1 28
CBS_GRST# P3 M19 R14 W15
GBRST# GND4 28 BVPPEN0 BVPPEN0 AVPPEN0 AVPPEN0 28
U1 PCIRST# GND5 K9 28 BVCC5EN# R15 BVCC5EN# AVCC3EN# V15 AVCC3EN# 28
PCIRST_CB# V1 PCICLK K10 P15 U15
17 PCIRST_CB# GND6 28 BVCC3EN# BVCC3EN# AVCC5EN# AVCC5EN# 28
CLK_PCI_CB K11
17 CLK_PCI_CB GND7

2
31 CB_PME# P5 RI_OUT#/PME# GND8 J10 A7 MDIO00 MDIO10 E10
B 1 2 U2 CLKRUN# L10 B7 F10 R452 B
17,24,31 PCI_CLKRUN# GND9 MDIO01 MDIO11
R314 0_0402_5% B8 F11 10K_0402_5%
MDIO02 MDIO12
1 2 C8 MDIO03 MDIO13 E12
@ R315 10K_0402_5% R5C842-CSP265P_CSP265 E8

1
MDIO04
B9 MDIO05 MDIO14/NC F12
INTA# : Card Socket A Please apply shield GND for TPAx0 and TPBx0 Separately; A9 MDIO06 MDIO15/NC F13
INTB# : Card Socket B MDIO16/NC E14
+3VS INTC# : IEEE1394 C9 F14
MDIO07 MDIO17/NC
E9 MDIO08 MDIO18/NC E15
F9 C16
========================================== GND MDIO09 MDIO19/NC
10U_0805_10V4Z~N

10U_0805_10V4Z~N

0.01U_0402_16V7K

0.01U_0402_16V7K

------------------------------------------ TPBN0
R5C842-CSP265P_CSP265
1 1 1 1
------------------------------------------ TPBP0 CBS_ACD2#
CBS_ACD2# 28
C485

C486

C487

C488

CLK_PCI_CB ========================================== GND CBS_ACD1#


CBS_ACD1# 28

2
0_0402_5%
------------------------------------------ TPAN0
1

R316
2 2 2 2 R318 R317
------------------------------------------ TPAP0
10_0402_5% 0_0402_5%
========================================== GND

1
CBS_ACCD1#_INTERNAL
2

Layout Note: Shield GND for CBS_ACCD2#_INTERNAL


CBS_BCCLK 2 2
CLK_PCI_CBS_TERM

CBS_ACCLK C491 C492


+3V L35 +3V_PHY Layout Note: 270P_0402_50V7K~N
270P_0402_50V7K~N
CHB1608B121_0603 1 1
Y5,C482, C484
1 2
Should close to U22
1000P_0402_50V7K~N

1000P_0402_50V7K~N
0.1U_0402_16V4Z

0.1U_0402_16V4Z
22U_1206_6.3V6M

Layout Note: Shield GND for CBS_BCD2#


CBS_BCD2# 28
VREF (PIN C12 of U12) CBS_BCD1#
CBS_BCD1# 28

2
0_0402_5%
C493

1 1 1 1 1 1 REXT (PIN C14 of U12)

R319
C494

C495

C496

C497

A C498 FIL0 (PIN A15 of U12) R320 A


22P_0402_25V8K Layout Note: C480, R304 and C481 0_0402_5%
2 2 2 2 2 2
need be closed to PAD.
1

1
CBS_BCCD1#_INTERNAL
Layout Note:CLK_PCI_CB SHOULD BE CBS_BCCD2#_INTERNAL
GND SHIELDING. 2 2
Layout Note: CBS_ACCLK and C499 C500
CBS_BCCLK should be shielded GND. 270P_0402_50V7K~N
270P_0402_50V7K~N
1 1 Compal
Title
Electronics, Inc.
SCHEMATIC, M/B LA-2642P
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401380 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: 星期五, 七月 29, 2005 Sheet 27 of 48
5 4 3 2 1
5 4 3 2 1

D D
CBS_ACAD[0..31]
CBS_ACAD[0..31] 27 CBS_BCAD[0..31]
CBS_BCAD[0..31] 27
JCBS1
150 GND GND 75
149 GND GND 74
CBS_AVCC 27 CBS_ACD1# 148 ACCD1#/CD1# BCCD1#/CD1# 73 CBS_BCD1# 27
CBS_ACAD0 147 72 CBS_BCAD0
ACAD0/D3 BCAD0/D3
+3V CBS_ACAD2 146 ACAD2/D11 BCAD2/D11 71 CBS_BCAD2
CBS_ACAD1 145 70 CBS_BCAD1
ACAD1/D4 BCAD1/D4

10U_0805_10V4Z~N
CBS_ACAD4 144 69 CBS_BCAD4
ACAD4/D12 BCAD4/D12

0.01U_0402_16V7K
1 U20 CBS_ACAD3 143 68 CBS_BCAD3
ACAD3/D5 BCAD3/D5
0.1U_0402_16V4Z

1U_0603_10V6K

+5V 1 1 142 GND GND 67

C507
1 10 7 CBS_ACAD6 141 66 CBS_BCAD6
AVCC3IN AVCCOUT ACAD6/D13 BCAD6/D13
C503

C504

C508
6 AVCC5IN 8 CBS_AVPP CBS_ACAD5 140 65 CBS_BCAD5
2
1 Slot A AVCCOUT 27 CBS_ACRSVD/D14
CBS_ACRSV/D14 139
ACAD5/D6 BCAD5/D6
64 CBS_BCRSV/D14
CBS_BCRSVD/D14 27
2 2 ARFU/D14 BRFU/D14
0.1U_0402_16V4Z

1U_0603_10V6K

1 AVCC3EN# 2 Power 9 CBS_ACAD7 138 63 CBS_BCAD7


2 27 AVCC3EN# AVCC3_EN AVPPOUT ACAD7/D7 BCAD7/D7
C506

0.01U_0402_16V7K
27 AVCC5EN#
AVCC5EN# 1 AVCC5_EN Supply +5V CBS_ACAD8 137 ACAD8/D15 BCAD8/D15 62 CBS_BCAD8
C505

0.1U_0402_16V4Z
R322 0_0402_5% 1 1 CBS_ACCBE0# 136 61 CBS_BCCBE0#
2 27 CBS_ACCBE0# ACCBE0#/CE1# BCCBE0#CE1# CBS_BCCBE0# 27

C501

C509
AVPPEN0 2 1 4 5 CBS_ACAD10 135 60 CBS_BCAD10
2 27 AVPPEN0 AEN0 TST ACAD10/CE2# BCAD10/CE2#
AVPPEN1 2 1 3 134 59
27 AVPPEN1 AEN1 GND GND
CBS_ACAD9 133 58 CBS_BCAD9
2 2 ACAD9/A10 BCAD9/A10
+3V R323 0_0402_5%
27 CBS_ACVS1
CBS_ACVS1 132 ACVS1/VS1# BCVS1/VS1# 57 CBS_BCVS1
CBS_BCVS1 27
CBS_ACAD11 131 56 CBS_BCAD11
ACAD11/OE# BCAD11/OE#
11 BVCC3IN BVCCOUT 13 CBS_BVCC CBS_ACAD13 130 ACAD13/IORD# BCAD13/IORD# 55 CBS_BCAD13
1 15 14 CBS_ACAD12 129 54 CBS_BCAD12
BVCC5IN BVCCOUT ACAD12/A11 BCAD12/A11
0.1U_0402_16V4Z

1U_0603_10V6K

+5V CBS_ACAD15 128 ACAD15/IOWR# BCAD15/OWR# 53 CBS_BCAD15


1 BVCC3EN# 19 Slot B 12 CBS_ACAD14 127 52 CBS_BCAD14
27 BVCC3EN# BVCC3_EN BVPPOUT ACAD14/A9 BCAD14/A9
C510

C511

10U_0805_10V4Z~N
2 27 BVCC5EN#
BVCC5EN# 20 BVCC5_EN Power CBS_BVPP 126 GND GND 51

0.01U_0402_16V7K
1 R325 0_0402_5% Supply CBS_ACAD16 125 50 CBS_BCAD16
ACAD16/A17 BCAD16/A17
1U_0603_10V6K

BVPPEN1 2 1 18 16 1 1 CBS_ACCBE1# 124 49 CBS_BCCBE1#


2 27 BVPPEN1 BEN0 GND 27 CBS_ACCBE1# ACCBE1#/A8 BCCBE1#/A8 CBS_BCCBE1# 27
0.1U_0402_16V4Z

C502

0.01U_0402_16V7K

C515
BVPPEN0 2 1 17 CBS_ACRSV2/A18 123 48 CBS_BCRSV2/A18
27 BVPPEN0 BEN1 27 CBS_ACRSV2/A18 ARFU/A18 BRFU/A18 CBS_BCRSV2/A18 27

0.1U_0402_16V4Z

C516
1 1 1 CBS_ACPAR 122 47 CBS_BCPAR
2 27 CBS_ACPAR ACPAR/A13 BCPAR/A13 CBS_BCPAR 27
C512

C513

C514
R324 0_0402_5% CBS_ACBLOCK# 121 46 CBS_BCBLOCK#
C 2 2 27 CBS_ACBLOCK# ACBLOCK#/A19 BCBLOCK#/A19 CBS_BCBLOCK# 27 C
R5534V-E2-FB_SSOP20~N CBS_ACPERR# 120 45 CBS_BCPERR#
27 CBS_ACPERR# ACPERR#/A14 BCPERR#/A14 CBS_BCPERR# 27
CBS_ACSTOP# 119 44 CBS_BCSTOP#
2 2 2 27 CBS_ACSTOP# ACSTOP#A20 BCSTOP#/A20 CBS_BCSTOP# 27
118 GND GND 43
CBS_ACGNT# 117 42 CBS_BCGNT#
27 CBS_ACGNT# CBS_ACDEVSEL# ACGNT#/WE# BCGNT#/WE# CBS_BCDEVSEL# CBS_BCGNT# 27
27 CBS_ACDEVSEL# 116 ACDEVSEL#/A21 BCDEVSEL#/A21 41 CBS_BCDEVSEL# 27
27 CBS_ACINT# 115 ACINT#/READY BCINT#/READY 40 CBS_BCINT# 27
CBS_AVCC 114 VCC VCC 39 CBS_BVCC
113 NC NC 38
CBS_AVPP 112 VPP VPP 37 CBS_BVPP
27 CBS_ACCLK 111 ACCLK/A16 BCCLK/A16 36 CBS_BCCLK 27
CBS_ACTRDY# 110 35 CBS_BCTRDY#
27 CBS_ACTRDY# ACTRDY#/A22 BCTRDY#/A22 CBS_BCTRDY# 27
CBS_ACIRDY# 109 34 CBS_BCIRDY#
27 CBS_ACIRDY# ACIRDY#/A15 BCIRDY#/A15 CBS_BCIRDY# 27
108 GND GND 33
CBS_ACFRAME# 107 32 CBS_BCFRAME#
27 CBS_ACFRAME# ACFRAME#/A23 BCFRAME#/A23 CBS_BCFRAME# 27
CBS_ACCBE2# 106 31 CBS_BCCBE2#
27 CBS_ACCBE2# ACCBE2#/A12 BCCBE2#/A12 CBS_BCCBE2# 27
CBS_ACAD17 105 30 CBS_BCAD17
CBS_ACAD18 ACAD17/A24 BCAD17/A24 CBS_BCAD18
104 ACAD18/A7 BCAD18/A7 29
CBS_ACAD19 103 28 CBS_BCAD19
CBS_ACAD20 ACAD19/A25 BCAD19/A25 CBS_BCAD20
102 ACAD20/A6 BCAD20/A6 27
CBS_ACVS2 101 26 CBS_BCVS2
27 CBS_ACVS2 ACVS2/VS2# BCVS2/VS2# CBS_BCVS2 27
100 GND GND 25
CBS_ACAD21 99 24 CBS_BCAD21
ACAD21/A5 BCAD21/A5
27 CBS_ACRST# 98 ACRST#/RESET BCRST#/RESET 23 CBS_BCRST# 27
CBS_ACAD22 97 22 CBS_BCAD22
CBS_ACSERR# ACAD22/A4 BCAD22/A4 CBS_BCSERR#
27 CBS_ACSERR# 96 ACSERR#/WAIT# BCSERR#/WAIT# 21 CBS_BCSERR# 27
CBS_ACAD23 95 20 CBS_BCAD23
CBS_ACREQ# ACAD23/A3 BCAD23/A3 CBS_BCREQ#
27 CBS_ACREQ# 94 ACREQ#/INPACK# BCREQ#/INPACK# 19 CBS_BCREQ# 27
CBS_ACAD24 93 18 CBS_BCAD24
ACAD24/A2 BCAD24/A2
92 GND GND 17
CBS_ACCBE3# 91 16 CBS_BCCBE3#
27 CBS_ACCBE3# ACCBE3#/REG# BCCBE3#/REG# CBS_BCCBE3# 27
CBS_ACAD25 90 15 CBS_BCAD25
ACAD25/A1 BCAD25/A1
27 CBS_ACAUDIO 89 ACAUDIO/SPKR# BCAUDIO/SPKR# 14 CBS_BCAUDIO 27
CBS_ACAD26 88 13 CBS_BCAD26
B CBS_ACSTSCHNG ACAD26/A0 BCAD26/A0 CBS_BCSTSCHNG B
27 CBS_ACSTSCHNG 87 ACSTSCHG/STSCHG# BCSTSCHG/STSCHG# 12 CBS_BCSTSCHNG 27
CBS_ACAD27 86 11 CBS_BCAD27
CBS_ACAD28 ACAD27/D0 BCAD27/D0 CBS_BCAD28
85 ACAD28/D8 BCAD28/D8 10
84 GND GND 9
CBS_ACAD29 83 8 CBS_BCAD29
CBS_ACAD30 ACAD29/D1 BCAD29/D1 CBS_BCAD30
82 ACAD30/D9 BCAD30/D9 7
JP1 CBS_ACRSV3/D2 81 6 CBS_BCRSV3/D2
27 CBS_ACRSV3/D2 ARFU/D2 BRFU/D2 CBS_BCRSV3/D2 27
TPBN0 1 CBS_ACAD31 80 5 CBS_BCAD31
27 IEEE1394_TPBN0 1 ACAD31/D10 BCAD31/D10
TPBP0 2 CBS_ACCLKRUN# 79 4 CBS_BCCLKRUN#
27 IEEE1394_TPBP0 2 27 CBS_ACCLKRUN# ACCLKRUN/WP BCCLKRUN/WP CBS_BCCLKRUN# 27
TPAN0 3 78 3
27 IEEE1394_TPAN0 3 27 CBS_ACD2# ACCD2#/CD2# BCCD2#CD2# CBS_BCD2# 27
TPAP0 4 77 2
27 IEEE1394_TPAP0 4 GND GND
76 GND GND 1
5 GND1
6 GND2
151 GND GND 152
FOX_UV31413-WR50D-7F~N 153 154
GND GND

CBS_ACRST#
FOX_331-0100-1CA84501-TC_150P 1
C517
0.01U_0402_16V7K
2
4 1

CBS_BCRST#
2
C518
0.01U_0402_16V7K
1: TPB# 1

A 2: TPB A

3: TPA#
4: TPA

Title
Compal Electronics, Inc.
SCHEMATIC, M/B LA-2642P
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
401380
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: 星期五, 七月 29, 2005 Sheet 28 of 48
5 4 3 2 1
5 4 3 2 1

MDC CONN.
JP12
+5VS
Adjustable Output +VDDA 1 MONO_OUT/PC_BEEP AUDIO_PWDN 2
U21 3 4
GND MONO_PHONE
4 VIN VOUT 5 5 AUXA_RIGHT Bluetooth Enable 6
4.7U_0805_10V4Z

0.1U_0402_16V4Z

7 AUXA_LEFT GND 8

4.7U_0805_10V4Z

0.1U_0402_16V4Z
2 DELAY SENSE or ADJ 6 9 CD_GND +5V 10
D
R326 11 12 D
CD_RIGHT USB Data+

0.01U_0402_16V7K
7 1 30.1K_0402_1% 1 13 14
C519 C520 ERROR CNOISE CD_LEFT USB Data-
15 GND PRIMARY DN 16 2 1 +3VS
8 3 17 18 R329 10K_0402_5%

1
SD GND +3V 3.3Vaux 5Vd
19 GND GND 20
SI9182DH-AD-T1-E3_MSOP8~N 2 MDC_SYNC R332 1
21 3.3Vmain AC97_SYNC 22 2 22_0402_5% AC_SYNC 18
1 R330 2 22_0402_5% MDC_SDOUT 23 24 SDIN1 1 2 R334 1 2 22_0402_5%
18,21 AC_SDOUT AC97_SDATA_OUT AC97_SDATA_IN1 AC_SDIN1 18

1
1 2 22_0402_5% MDC_RST# 25 26 SDIN0R331 1 2 0_0402_5%
R327 18 AC_RST# R333 AC97_RESET# AC97_SDATA_IN0 @ R1050 0_0402_5%
27 GND GND 28

C522

C1005
10K_0603_1% 29 30
+5VS AC97_MSTRCLK AC97_BITCLK

GND1
GND2
GND3
GND4
GND5
GND6
C521
MDC_BITCLK 1 2 AC_BITCLK 18

2
R335 22_0402_5%
1 2 1
R1003 10K_0402_5% ACES_88021-3001L~N C524

31
32
33
34
35
36
+3V
@ 15P_0402_50V8J
2
1 1
C525 C526
1U_0603_10V4Z 0.1U_0402_16V4Z
2 2

C C

+AVDD_AC97 L51 +3VS


+3VS_DVDD 1 2
AC97 Codec CHB2012U121_0805

L38 CHB2012U170_0805 10U_0805_10V4Z~N


1 2 0.1U_0402_16V4Z
+VDDA
1
C552 1 C531 C532
C551 C533
0.1U_0402_16V4Z 0.1U_0402_16V4Z 10U_0805_10V4Z~N
C530 2
2
25

38

34

43

U22
@ C534 1000P_0402_50V7K~N
AVDD1

AVDD2

AVDD4

AVDD3

DVDD1

DVDD2

0.1U_0402_16V4Z
@C535 1000P_0402_50V7K~N

14 35 LINEL 1 2
AUX_L LINE_OUT_L R341 0_0603_5% AMP_LEFT 30
15 36 LINER 1 2
AUX_R LINE_OUT_R @ C537 1000P_0402_50V7K~N R342 0_0603_5% AMP_RIGHT 30
1 2 16 JS1 MONO_OUT 37
R728 2.2K_0402_5% @ C539 1000P_0402_50V7K~N
1 2 17 39 HP_LOUT 1 2
R729 2.2K_0402_5% JS0 HP_LOUT_L R453 0_0603_5% HP_LEFT 30
23 41 HP_ROUT 1 2
LINE_IN_L HP_LOUT_R HP_RIGHT 30
B 1 2 R355 0_0603_5% B
24 @ C542 27P_0402_50V8J
LINE_IN_R
BIT_CLK 6 1 2 AC_BITCLK 18
18 R343 22_0402_5%
CD_L
SDATA_IN 8 1 2 AC_SDIN0 18
20 R345 22_0402_5%
CD_R
XTL_IN 2 1 2 CLK_AC97_14M 16
2

19 R347 0_0402_5%
CD_GND R350 Y6 Place very close to U30.2
1 2 C_MIC1 21 @ 24.576MHZ_16P_1BX24576EE1B
30 MIC1 MIC1
C544 1U_0603_10V6K @ 1M_0402_5%
1 2 C_MIC2 22 3 1 2 1
30 MIC2
1

C545 1U_0603_10V6K MIC2 XTL_OUT C549


13
1
C548 +AUD_VREF Reserved for TEST
PHONE @ 22P_0402_50V8J
28 @ 22P_0402_50V8J 2
VREFOUT +AUD_VREF 2
1 2
27 VREF R497 0_0805_5%
R352 2 VREF
18 AC_RST# 1 11 RESET# 1 1 1 2
22_0402_5% R496 0_0805_5%
R353 1 2 10 29 AFILT1 1 2 C547 C1007 C1006 1 2
18 AC_SYNC SYNC AFILT1 270P_0402_50V7K~N
22_0402_5% 30 AFILT2 @ 0.1U_0402_16V4Z @4.7U_0805_10V4Z R495 0_0805_5%
R354 1 AFILT2 AFILT3 2 2
18,21 AC_SDOUT 2 5 SDATA_OUT AFILT3 31 1 2 C475 1 2
22_0402_5% 32 AFILT4 270P_0402_50V7K~N 1 1 R493 0_0805_5%
AFILT4
45 ID0 1 2 C490
270P_0402_50V7K~N C641 C640
46 ID1
12 1 2 C489 1U_0603_10V4Z 0.1U_0402_16V4Z GND AGND
NC 270P_0402_50V7K~N 2 2
30 EAPD 1 2 47 EAPD NC 42
L56 FBM-L10-160808-301
48 SPDIFO AVSS1 26
AVSS2 40
2

A 4 44 AGND A
R358 R356 DVSS1 AVSS3
7 DVSS2 AVSS4 33
10K_0402_5% 10K_0402_5%
AD1981BJSTZ_LQFP48~N
1

DGND AGND
Compal Electronics, Inc.
Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND SCHEMATIC, M/B LA-2642P
Add ID table TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev

401380
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE B
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: 星期五, 七月 29, 2005 Sheet 29 of 48
5 4 3 2 1
A B C D E

Speaker Connector
+5VS
JSPK1
W=40Mil INTSPK_R1 1
INTSPK_R2 1
1 1 2 2
INTSPK_L1 3
C557 C558 INTSPK_L2 3
4 4
0.1U_0402_16V4Z 10U_0805_10V4Z~N
2 2 U23 +5VS MOLEX_53398-0419~N

16
15
6
R360 1 2 10K_0402_5%

PVDD1
PVDD2
VDD
@ R359 1 2 10K_0402_5%
4
MICROPHONE IN JACK 4
C561 1 2 7 2 R361 1 2 10K_0402_5%
0.47U_0603_16V4Z RIN+ GAIN0 3K_0402_5% R371 JP16
3 @ R362 1 2 10K_0402_5% 2 1 +AUD_VREF 5
GAIN1
2 1
C559 1 2 AMP_R 17 3K_0402_5% R732 4
29 AMP_RIGHT RIN-
0.47U_0603_16V4Z 18 SPK_R1 1 2 INTSPK_R1
ROUT+ R489 0_0603_5% MIC-2
29 MIC2 1 2 3
L47 CHB2012U170_0805 6
14 SPK_R2 1 2 INTSPK_R2 1 2 MIC-1 2
C560 1 ROUT- R490 0_0603_5% 29 MIC1 L41 CHB2012U170_0805
2 9 LIN+ 1
0.47U_0603_16V4Z 1 1
4 SPK_L1 1 2 INTSPK_L1 FOX_JA6333L-B1ST-7F~N
LOUT+ R491 0_0603_5% C567
C562 1 2 AMP_L 5 220P_0402_50V7K C570
29 AMP_LEFT LIN- 2 2
0.47U_0603_16V4Z 8 SPK_L2 1 2 INTSPK_L2
LOUT- R492 0_0603_5%
220P_0402_50V7K

NC 12

10
19 SHUTDOWN
BYPASS HEADPHONE OUT JACK
1 0.47U_0603_16V4Z +3VS
C563

GND1
GND2
GND3
GND4

1
2
+3VS TPA6017A2PWPRG4_TSSOP20~N R731
20
13
11
1 10K_0402_5%
3 3
C996

2
1

0.1U_0402_16V4Z JP15
R1004 2 1 5
100K_0402_5%
NBA_PLUG# 4
R1006 47_0402_5%
2

HP_OUTR 1 2 HP_R 1 2 H PR 3
R1005 47_0402_5% L39 CHB2012U170_0805 6
GAIN0 GAIN1 GAIN HP_OUTL 1 2 HP_L 1 2 HPL 2
L40 CHB2012U170_0805 1
1

2 2
1

1
D R1036 D FOX_JA6333L-B1ST-7F~N
EC_MUTE
2 Q55 10K_0402_5% NBA_PLUG# 2 Q57 0 0 6dB R472 C901 C900
31 EC_MUTE 470P_0402_50V7K
G 2N7002_SOT23 G 2N7002_SOT23 R471 @ 1K_0402_5% 470P_0402_50V7K
S S @ 1K_0402_5% 1 1
3

2
EAPD 0 1 10dB
29 EAPD

1 0 15.6dB +3VS

+3VS

5
1 1 21.6dB U52
NBA_PLUG# 1 2 2

P
Buzzer need to support ICH/PCM_SPK/Battery_low and WL_on/off R1013 0_0402_5%B 4 HP_MUTE# Reserve the 0 ohm resistor.
Y

1
EAPD 1 2 1
0_0402_5% A for voltage filtering

G
R1014 R985
NC7SZ08P5X_NL_SC70-5 0_0603_5%

3
2 1 2 2

2
C1001 1U_0603_10V4Z

+5VS

19

10
U35
31 BUZR_OFF
1

+3VS

PVDD

SVDD
R313 HP_MUTE# 14 11 HP_OUTR
EC Beep C1016
56.2_0603_1% SHDNR# OUTR
2 1 18 9 HP_OUTL
SHDNL# OUTL
14

2
1

U54A
0.1U_0402_16V4Z
OE#
P

1 2 2 3 C569 R981
31 BEEP# I O
R375 1U_0805_50V4Z 6.8K_0603_5% 4
NC-4
G

0_0402_5%
29 HP_RIGHT 1 2 HP_INR 1 2 HPINR 15
2

SN74LVC125APWLE_TSSOP14 C997 2.2U_0603_6.3V4Z INR


6
7

NC-6
29 HP_LEFT 1 2 HP_INL 1 2 HPINL 13 INL
BUR1 C998 2.2U_0603_6.3V4Z 8
BUZZER NC-8
1 2 1 + R982
R377 2 6.8K_0603_5% 12
@ 0_0402_5% - NC-12
CardBus Beep 31 BUZR_OFF
LET9040-03A_2P 1 C1P NC-16 16
4

U54B 1
1

PGND

SGND
C 3 20

PVss

SVss
OE#

BU ZR Q53 C999 C1N NC-20


27 PCM_SPK# 1 2 5 I O 6 2
R376 B 2SC2411K_SC59 1U_0603_10V4Z
0_0402_5% E 2 MAX4411ETP+T_TQFN20~N
3

17
1

SN74LVC125APWLE_TSSOP14 D19

R382
1 @ 10K_0402_5% @ CH751H-40_SC76 1 1
31 BUZR_OFF
2

C1000
ICH Beep 1U_0603_10V4Z
10

U54C 2
OE#

18 SPKR 1 2 9 I O 8
R381
0_0402_5% Compal Electronics, Inc.
SN74LVC125APWLE_TSSOP14 PROPRIETARY NOTE Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND SCHEMATIC, M/B LA-2642P
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev

401380
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE B
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: 星期五, 七月 29, 2005 Sheet 30 of 48
A B C D E
5 4 3 2 1

+3V_EC
+3VCCA_EC
L42
0.1U_0402_16V4Z 0.1U_0402_16V4Z 1 2
1 1 C577 1 1 2 2 FBM-L11-160808-800LMT_0603
C576 1
C578 C574 C579 C580
R288 1000P_0402_50V7K~N 1000P_0402_50V7K~N C583
PCI_CLKRUN# 1 EC_CLKRUN# 2 2 2 2 1 1
17,24,27 PCI_CLKRUN# 2
0_0402_5% 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z

+3VCCA_EC
2
R72 ECAGND
@ 1K_0402_5%

105
127
141
D D

11
26
37

75
U28 2 1 ECAGND
1 71 BATT_TEMP_A C584 0.01U_0402_16V7K

VCC
VCC

EC_AVCC / AVCC
VCC / EC VCC
VCC / EC VCC
VCC / EC VCC
VCC/ EC VCC
18 GATEA20 GA20/ GPIO00/GA20 BATTEMP/AD0/GPIO38 BATT_TEMPA 37
2 1 2 1 CLK_PCI_LPC 18 KBRST# 2 KBRST#/GPIO01/KBRST# BATT OVP/AD1/GPIO39 72 BATT_OVP 36
R385 10_0402_5% SERIRQ 3 73
17,27 SERIRQ SERIRQ ADP_I/AD2/GPIO3A ADP_I 36
C582 LPC_FRAME# 5 74 BATT_TEMP_B
17 LPC_FRAME# LPC_FRAME# / LFRAME# AD BID0/AD3/GPIO3B BATT_TEMPB 37
22P_0402_25V8K LPC_AD3 6 2 1 ECAGND
17 LPC_AD3 LPC AD3/LAD3
LPC_AD2 9 AD INtput or GPI C638 0.01U_0402_16V7K
17 LPC_AD2 LPC AD2/LAD2
C585 0.1U_0402_16V4Z LPC_AD1 10 Host
17 LPC_AD1 LPC AD1/LAD1 INTERFACE
2 1 LPC_AD0 12
17 LPC_AD0 LPC AD0/LAD0
CLK_PCI_LPC 14 76
17 CLK_PCI_LPC CLK_PCI_EC/PCICLK DAC_BRIG/DA0/GPIO3D DAC_BRIG 15
+3V_EC 2 1 ECRST# PCIRST_EC# 15 PWR 78
17 PCIRST_EC# PCIRST# EN DFAN1/DA1/GPIO3D EN_FAN1 8
R391 47K_0402_5% ECRST# 42 79
EC RST#/ ECRST# IREF2/DA2 IREF 36
18 EC_SCI# 24 EC SCI#/SCI#/GPIO0E EN DFAN2/DA3/ GPIO3F 80 EN_WOL# 33
EC_CLKRUN# 44
PM_CLKRUN#/ CLKRUN# DA output or GPO
FAN/PWM +5VALW
+3V_EC 25
KSI0 INVT_PWM/GPIO0F/PWM1 INVT_PWM 15
63 KSI0/GPIO30 BEEP#/GPIO10/PWM2 27 BEEP# 30 1 2
KSI1 64 30 C1010 0.1U_0402_16V4Z
KSI1/GPIO31 OUT BEEP/GPIO12/PWM3 PIDERST# 22
2

KSI2 65 31
R384 KSI3 KSI2/GPI032 ACOFF/GPIO18/PWM4 ACOFF 36
U50

20
66 KSI3/GPIO33 FAN SPEED1/GPIO14/FANFB1 32 FAN1_SPEED 8
10K_0402_5% KSI4 67 33
KSI4/GPIO34 FAN SPEED2/GPIO15/FANFB2 FINGERPRINT# 32
KSI5 68 ADB0 3 2

VCC
KSI6 KSI5/GPI035 ADB1 D0 Q0
69 4 5
1

KSI7 KSI6/GPIO36 BT_EXIST# +3VALW ADB2 D1 Q1 BUZR_OFF 30


70 KSI7/GPIO37 PSCLK1 91 BT_EXIST# 23 7 D2 Q2 6 EC_MUTE 30
1 2 key Matrix 92 ADB3 8 9
27 CB_PME# PSDAT1 TRICKE 37 D3 Q3
KSO0 47 scan 93 1 2 ADB4 13 12
32 KSI[0..7] KSO0/GPIO20 PSCLK2 MAIL# 32 D4 Q4
CH751H-40_SC76 D38 KSO1 48 PS2 interface 94 0.1U_0402_16V4Z C1009 ADB5 14 15
EC_PME# KSO2 KSO1/GPIO21 PSDAT2 NET# 32 ADB6 D5 Q5 AUX_S5EN 38
24 WLAN_PME# 1 2 49 KSO2/GPIO22 PSCLK3 95 TP_CLK 32 17 D6 Q6 16 W L_OFF# 24,32

5
KSO3 50 96 U51 ADB7 18 19
KSO3/GPIO23 PSDAT3 TP_DAT 32 D7 Q7
CH751H-40_SC76 D39 KSO4 51 KBA2 2

G Vcc
32 KSO[0..15] KSO5 KSO4/GPIO24 ADB0 B
1 2 52 125 4 11

GND
18,25 PCIE_PME# KSO5/GPIO25 ADB0/D0 Y CP
KSO6 53 126 ADB1 SELIO 1 1
CH751H-40_SC76 D40 KSO7 KSO6/GPIO26 ADB1/D1 ADB2 A MR
54 KSO7/GPIO27 ADB2/D2 128
KSO8 55 Data 130 ADB3 NC7SZ32P5X_NL_SC70-5 SN74HCT273PWR_TSSOP20~N

10
C KSO8/GPIO28 ADB3/ D3 C
KSO9 56 BUS 131 ADB4
KSO10 KSO9/GPIO29 ADB4/D4 ADB5 C1008
57 KSO10/GPIO2A ADB5/D5 132
KSO11 58 133 ADB6 +3VALW 1 2 1 2
KSO12 KSO11/GPIO2B ADB6/D6 ADB7 R1008 20K_0402_5% 1U_0603_10V6K
59 KSO12/GPIO2C ADB7/D7 134
KSO13 60 111 KBA0
KSO14 KSO13/GPIO2D KBA0/A0 KBA1 ADB[0..7]
61 KSO14/GPIO2E KBA1/A1 112 ADB[0..7] 32
KSO15 62 113 KBA2
KSO15/GPIO2F KBA2/A2 KBA3 KBA[0..19]
32 KBSEL0# 89 EC URXD/KSO16/GPIO48 KBA3/A3 114 KBA[0..19] 32
90 115 KBA4
32 KBSEL1# EC UTXD/KSO17/GPIO49 KBA4/A4
+3V_EC 116 KBA5
RP55 KBA5/A5 KBA6
KBA6/A6 117
1 8 MAIL# 6,37 EC_SMB_DA2 88 EC SMD2/ GPIO47/SDA2
Address
KBA7/A7 118 KBA7
2 7 NET# 6,37 EC_SMB_CK2 87 EC SMC2/GPIO46/SCL2
BUS
KBA8/A8 119 KBA8
3 6 LID_SW# 86 SM BUS 120 KBA9
32,37 EC_SMB_DA1 EC SMD1/GPIO44/SDA1 KBA9/A9
4 5 85 121 KBA10
32,37 EC_SMB_CK1 EC SMC1/GPIO44/SCL1 KBA10/A10
10K_1206_8P4R_5% 122 KBA11
KBA11/A11 KBA12
KBA12/A12 123
E51_TXD 34 124 KBA13
+3V_EC PCM_SPK#/EMAIL_LED#/ GPIO16 KBA13/A13 KBA14
32 PWR_STA2# 35 SB_SPKR/PWR_SUSP_LED#/ GPIO17 KBA14/A14 110
RP56 38 109 KBA15
32 PWR_STA1# PWRLED#/ GPIO19 KBA15/A15 KBA16
1 8 32 NUM_LED# 40 NUMLED#/ GPIO1A KBA16/A16 108
2 7 FRD# 99 107 KBA17
32 BAT1_LED# BATT CHGI LED#/ E51CS# KBA17/A17 KBA18 +3V_EC
3 6 32 BAT2_LED# 101 BATT LOW LED#/ E51MR0 KBA18/A18 106
4 5 FSEL# 100 98 KBA19
100K_1206_8P4R_5% 32 CAPS_LED# CAPS LED#/ E51TMR1 KBA19/A19
32 SCROL_LED# 102 ARROW LED#/ E51 INT0

2
33,38 SYSON 104 SYSON/GPIO56/ E51 INT1 SELIO2#/ GPIO43 84 CBS_SPND# 27
97 SELIO R386
+5VALW SELIO#/ GPIO50 @ 10K_0402_5%
18 EC_RSMRST# 4 EC_RSMRST#/ GPIO02 FRD#/RD# 135 FRD# 32
RP57 7 136
EC_SMB_CK1 15 BKOFF# BKOFF#/GPIO03 FWR#/WR# FW R# 32
1 8 18 PM_SLP_S3# 8 144

1
EC_SMB_DA1 PM SLP S3#/GPIO04 FSEL#/SELMEM# FSEL# 32 D20
2 7 18 EC_LID_OUT# 16 EC LID OUT#/GPIO06
3 6 EC_SMB_CK2 17 41
18 PM_SLP_S5# PM SLP S05#/ GPIO07 EC ON/ GPIO1B EC_ON 32,38
4 5 EC_SMB_DA2 18 43 2 1
18 EC_SMI# EC SMI#/GPIO08 AC IN/ GPIO1C ACIN 34,38
18 EC_SWI# 19 EC SWI#/GPIO09 ECTHERM#/GPIO11 29 A/B#USE 37
4.7K_1206_8P4R_5% 20 36 @ CH751H-40_SC76
32 LID_SW# LID SW#/ GPIO0A ONOFF/GPIO18 ON/OFF# 32
B
32,33,40 SUSP# 21 SUSP#/GPIO0B PCMRST#/GPIO1E 45 HDD_EN# 22 B
+5VS BAY_TYPE
18 PBTN_OUT# 22 PBTN_OUT#/GPIO0C WL OFF#/GPIO1F 46 BAY_TYPE 22 1 2
EC_PME# 23 R71 0_0402_5%
EC PME#/GPIO0D
ALI/MH#/GPIO40 81 BT_DIS# 23
2 1 TP_CLK FSTCHG/GPIO41 82 FSTCHG 36,37
4.7K_0402_5% R484 83
VR ON/ GPIO42 ENABLT VR_ON 41
GPIO57/GPIO57 137 ENABLT 11
2 1 TP_DAT C RY1 140 XCLKO GPIO58/GPIO58 142 NB_VCC_CNTL 42
AGND

4.7K_0402_5% R485 C RY2 138 143


GND
GND
GND
GND
GND
GND

XCLKI GPIO59/GPIO59 LAN_LOW_PWR 25


+3VS
139
129
103
13
28
39

77

KB910LQF A1_LQFP144~N JP33


LPC_AD0 LPC_FRAME#
BT_EXIST# L43 LPC_AD1 2 1
4 3 PCIRST_TPM# 17
10K_0402_5% R1053 ECAGND
2 1 LPC_AD2 SERIRQ
LPC_AD3 6 5 PCI_CLKRUN#
FBM-L11-160808-800LMT_0603 8 7
10 9
12 11
FOR LPC SIO DEBUG PORT For EC Tools
14
16
13
15
CLK_PCI_TPM 17
+5VS
+3VS 18 17
C RY1 1 R393 C RY2 JP32 +3VS 20 19
2 12mA
@ 20M_0603_5% 1
1
2 2
3 NAIS_AXK5S20045J~N
3
4 4
JP17
0.5A per each pin
5 5
6 6 CLK_LPC_14M 16 1 1 +3V_EC
7 LPC_AD0 2
7 LPC_AD1 2
8 8 3 3
1 1 9 LPC_AD2 4 E51_TXD
C587 C588 9 LPC_AD3 4
10 10 5 5
1

11 LPC_FRAME# 6
11 6
10P_0402_50V8J

10P_0402_50V8J

Y7 12 7
IN

OUT

A 2 2 12 PCIRST_EC# LPC_DRQ1# 17 7 A
13 13 8 8
14 PCI_CLKRUN# 9
14 9
15 15 1 2 CLK_PCI_LPC 10 10
SERIRQ @ R290 0_0402_5%
NC

NC

16 16
17 17
18 @ 96212-1011S
2

18
19 19
20 20

ACES_85201-2005 Compal Electronics, Inc.


32.768KHZ_12.5P_1TJS125DJ2A073 @
Title
JP32 Pin15 for CLK_PCI_LPC, not SCHEMATIC, M/B LA-2642P
reserve for PCI_CLK trance length THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
control. B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
401380
星期五 , 七月 29, 2005 Sheet 31 of 48
5 4 3 2 1
+5VALW
+5VALW
1MB Flash ROM U26
+3V_EC

1
C589 Debug Tool
1 2 0.1U_0402_16V4Z R401 KBA0 21 31
KBA1 A0 VCC0 JP18
20 A1 VCC1 30 1
100K_0402_5% KBA2 19 C590 KBA14 +3V_EC
U25 KBA[0..19] KBA3 A2 KBA13 1 2 FSEL#
31 KBA[0..19] 18

2
ADB[0..7] KBA4 A3 ADB0 0.1U_0402_16V4Z KBA12 3 4 FR D#
8 VCC A0 1 31 ADB[0..7] 17 A4 D0 25 5 6
KBA5 ADB1 2 KBA11 FWE#
7 WP A1 2 16 A5 D1 26 7 8
6 3 +3V_EC 1 2 FWE# KBA6 15 27 ADB2 KBA10 ADB7
31,37 EC_SMB_CK1 SCL A2 A6 D2 9 10
5 4 R1038 10K_0402_5% KBA7 14 28 ADB3 KBA9 ADB6
31,37 EC_SMB_DA1 SDA GND A7 D3 11 12
KBA8 8 32 ADB4 KBA8 ADB5
AT24C16AN-10SU-2.7_SO8~N KBA9 A8 D4 ADB5 KBA7 13 14 ADB4
7 A9 D5 33 15 16
+3VALW KBA10 36 34 ADB6 KBA6 ADB3
+3VALW KBA11 A10 D6 ADB7 +3V_EC KBA5 17 18 ADB2
6 A11 D7 35 19 20

1
KBA12 5 KBA4 ADB1
A12 21 22

1
R402 C591 R403 KBA13 4 KBA3 ADB0
100K_0402_5% 0.1U_0402_16V4Z 2 100K_0402_5% KBA14 A13 BIOS_RST# 1 KBA2 23 24 KBA19
1 SUSP# 31,33,40 3 A14 RP# 10 2 25 26
KBA15 2 11 R1007 10K_0402_5% KBA1 KBA18
A15 NC 27 28

2
Q19 KBA16 KBA0 KBA17

G
1 12

2
A16 READY/BUSY# 29 30

5
U27 2N7002_SOT23 KBA17 40 29 BIOS_RST# KBA16

2
KBA18 A17 NC0 31 32 KBA15
2 1 3 13 38

G Vcc
B EC_FLASH# 18 A18 NC1 33 34
FWE# 4 KBA19 37

S
Y A19 @ SUYIN_127212FA034G200ZX
A 1
FSEL# 22
31 FSEL# CE#
NC7SZ32P5X_NL_SC70-5 FR D# 24 23
31 FRD#

3
FWE# OE# GND0
9 WE# GND1 39
FWR# 31
1 2 SST39VF080-70-4C-EIE_TSOP40~N
@ R1037 0_0402_5%

31 KSO[0..15]

+5VS KSO15
KSO14
KEYBOARD CONN. RP58
0_1206_8P4R_5%
JSW1 JKB1
1 2 KSO13 KSI7 4 5 KBD24 1
1 2 IDE_LED# 22
PWR_BTN# 3 4 KSO12 KSI6 3 6 KBD23 2
3 4 NUM_LED# 31
5 6 KSO11 KSI5 2 7 KBD22 3
31 CAPS_LED# 5 6 SCROL_LED# 31 0_1206_8P4R_5%
7 8 KSO10 KSI4 RP59 1 8 KBD21 4
7 8 NET# 31 KSO9 KSI3 KBD20
31 MAIL# 9 9 10 10 4 5 5
11 12 KSO8 KSI2 3 6 KBD19 6
11 12 KSO7 KSI1 KBD18
2 7 7
ACES_87153-1241L~N KSO6 KSI0 RP60 1 8 0_1206_8P4R_5% KBD17 8
KSO5 KSO15 4 5 KBD16 9
KSO4 KSO14 3 6 KBD15 10
KSO3 KSO13 2 7 KBD14 11
KSO2 KSO12 RP61 1 8 0_1206_8P4R_5% KBD13 12
KSO1 KSO11 4 5 KBD12 13
OFF ON KSO0 KSO10 3 6 KBD11 14
SW1 KSO9 2 7 KBD10 15
0_1206_8P4R_5%
ON

PASSWORD# 1 16 KSO8 RP63 1 8 KBD9 16


18 PASSWORD# KSO7 KBD8
31 KSI[0..7] 4 5 17
2 15 KSO6 3 6 KBD7 18
KSI7 KSO5 2 7 KBD6 19
3 14 KSI6 KSO4 RP62 1 8 KBD5 20
KSI5 KSO3 4 5 0_1206_8P4R_5% KBD4 21
4 13 KSI4 KSO2 3 6 KBD3 22
KSI3 KSO1 2 7 KBD2 23
FINGERPRINT# 5 12 KSI2 KSO0 1 8 KBD1 24
31 FINGERPRINT# KSI1
KBSEL0# 6 11 KSI0 ACES_85203-2402
31 KBSEL0#
KBSEL1# 7 10
31 KBSEL1#
8 9

5
6
7
8

5
6
7
8

5
6
7
8

5
6
7
8

5
6
7
8

5
6
7
8
+3VS HPS608-E_16P CP1 CP2 CP3 CP4 CP5 CP6
RP66

1 8 FINGERPRINT#
2 7 KBSEL0#
3 6 KBSEL1#

4
3
2
1

4
3
2
1

4
3
2
1

4
3
2
1

4
3
2
1

4
3
2
1
4 5

10K_1206_8P4R_5%
100P_1206_8P4C_50V8 100P_1206_8P4C_50V8 100P_1206_8P4C_50V8
100P_1206_8P4C_50V8 100P_1206_8P4C_50V8
+3VS 1 2 PASSWORD# 100P_1206_8P4C_50V8
R1016 10K_0402_5% +3V_EC
2

R417
100K_0402_5%
Touch-Pad CONN.
1

C597
0.1U_0402_16V4Z
D32 1 2
3 ON/OFF# 31
PWR_BTN# 1 +5VS L46 MOUSEVDD
2 JPALM1
2 1 1 1 2 2
CHN202U_SC70 FBM-L11-321611-260-LMT_1206 3 4 MOUSECLK
@ 1000P_0402_50V7K~N 3 4 MOUSEDAT
5 5 6 6
7 7 8 8 PWR_STA1# 31
1

D33 9 10
31 PWR_STA2# 9 10 BAT1_LED# 31
C598
1

31 BAT2_LED# 11 11 12 12 WL_OFF# 24,31


24 WLAN_ACT 13 13 14 14 WLAN_LINK 24
+3VALW @ MMGZ5248B_LL34
2

31 LID_SW# 15 15 16 16
R1047 0_0603_5% +5V 17 18 +5VALW
2

MOUSECLK 17 18
31 TP_CLK 1 2 19 19 20 20
2

R421 1 2 MOUSEDAT ACES_87153-2041L~N


31 TP_DAT
10P_0402_50V8J

10P_0402_50V8J

@ 4.7K_0402_5% R1048 0_0603_5%


2 1 MAIL# 31
D43 @ CH751H-40_SC76 1 1
1

C595

C596

EC_ON 1 R422 2 2
31,38 EC_ON
2 1 NET# 31
@33K_0603_1% D44 @ CH751H-40_SC76
Q21 2 2
Compal Electronics, Inc.
3

@ DTC124EK_SC59
1

D Title
Q22
2
G @ 2N7002_SOT23 SCHEMATIC, M/B LA-2642P
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
S Size Document Number R ev
3

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
401380
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: 星期五, 七月 29, 2005 Sheet 32 of 48
A B C D E

+1.8VALW TO +1.8VS +1.8VALW TO +1.8V


B+_BIAS

2
+1.8VALW +1.8V
+1.8VALW +1.8VS 4.7U_0805_10V4Z R440
4.7U_0805_10V4Z 470K_0402_5%
1 1
1 1 Q47 C601 C602

1
470_0805_5%
Q23 C599 C600 8 1
D S 25 EN_WOL

2
470_0805_5%
8 D S 1 7 D S 2

1
2 2 R424 D
7 D S 2 6 D S 3
2 2 R423 Q39
6 D S 3 5 D G 4 2 EN_WOL# 31
1 5 4 1U_0603_10V4Z 2N7002_SOT23
G 1
D G 1U_0603_10V4Z SI4362DY_SO8 SUSON
1 2 S

3
4.7U_0805_10V4Z

0.1U_0603_50V4Z
AO4422L_SO8~N 1 2 RUN_ON 1 1 R1040 220K_0402_5%

1
4.7U_0805_10V4Z

0.1U_0603_50V4Z

1 1 R1039 30K_0402_1%

1
C605 D

1
C603 D C606 SYSON# Q26
2
C604 SUSP Q25 2 2 G 2N7002_SOT23
2
2 2 G 2N7002_SOT23 S

3
S

3
+3VALW TO +3VS +3VALW TO +3V
+3VALW +3VS +3VALW +3V
4.7U_0805_10V4Z 4.7U_0805_10V4Z

1 1 1 1
Q27 C607 C608 470_0805_5% Q28 C609 C610

470_0805_5%
8 D S 1 8 D S 1
2

2
7 2 1U_0603_10V4Z 7 2 1U_0603_10V4Z
D S 2 2 R425 D S 2 2 R426
6 D S 3 6 D S 3
5 D G 4 5 D G 4

AO4422L_SO8~N 1 2 RUN_ON AO4422L_SO8~N 1 2 SUSON


1

1
4.7U_0805_10V4Z

0.1U_0603_50V4Z

4.7U_0805_10V4Z

0.1U_0603_50V4Z
1 1 R1041 10K_0402_5% 1 1 R1042 47K_0402_5%
1

1
2 C611 D C613 D 2
C612 SUSP 2 Q29 C614 SYSON# 2 Q31
2 2 G 2N7002_SOT23 2 2 G 2N7002_SOT23
S S
3

3
+5VALW TO +5VS +5VALW TO +5V
+5VALW +5VS +5VALW +5V
4.7U_0805_10V4Z 4.7U_0805_10V4Z

1 1 1 1
Q32 C615 C616 Q44 C642 C633
470_0805_5%

470_0805_5%
8 D S 1 8 D S 1
2

2
7 D S 2 7 D S 2
2 2 R428 2 2 R443
6 D S 3 6 D S 3
5 D G 4 5 D G 4
1U_0603_10V4Z 1U_0603_10V4Z FD20 FD22 FD18
SI4362DY_SO8 RUN_ON 1 R431 2 B+_BIAS AO4422L_SO8~N SUSON 1 R441 2 B+_BIAS 1 1 1
1

1
4.7U_0805_10V4Z

0.1U_0603_50V4Z

4.7U_0805_10V4Z

0.1U_0603_50V4Z

1 1 20K_0402_5% 1 1 22K_0402_5%
FIDUCIAL MARK FIDUCIAL MARK FIDUCIAL MARK
1

1
C617 D D C644 D D
C618 2 SUSP 2 Q34 C643 2 SYSON# 2 Q40 FD23 FD21 FD19 FD24
2 2 2N7002_SOT23
G G 2N7002_SOT23 2 2 2N7002_SOT23
G G 2N7002_SOT23 1 1 1 1
S Q33 S S Q43 S
3

3
3 FIDUCIAL MARK FIDUCIAL MARK FIDUCIAL MARK FIDUCIAL MARK 3

FD9 FD14 FD10


1 1 1

FIDUCIAL MARK FIDUCIAL MARK FIDUCIAL MARK

H1 H2 H3 H4 H9 FD15 FD13 FD11 FD16


@ HOLEA@ HOLEA@ HOLEA@ HOLEA@ HOLEA 1 1 1 1

FIDUCIAL MARK FIDUCIAL MARK FIDUCIAL MARK FIDUCIAL MARK


+5VALW +5VALW FD1 FD2 FD3 FD4

1
1 1 1 1
+0.9VS
2

+1.2VS FIDUCIAL MARK FIDUCIAL MARK FIDUCIAL MARK FIDUCIAL MARK


470_0805_5%

R432 R433 H10 H11 H12 H13 H14


2

470_0805_5%

100K_0402_5% 100K_0402_5% HOLEA@ HOLEA@ HOLEA@ HOLEA@ HOLEA FD5 FD6 FD7 FD8
2

R430 1 1 1 1
R429
1

SUSP SYSON# FIDUCIAL MARK FIDUCIAL MARK FIDUCIAL MARK FIDUCIAL MARK

1
23,39,40 SUSP
1
1

D D
1

2 Q38 2 Q37
31,32,40 SUSP# 31,38 SYSON
1

G 2N7002_SOT23 G 2N7002_SOT23 D
2

D
S S 2 SUSP
Q36 H15 H18 H20 H24 H5 H6 H7 H8
3

2N7002_SOT23
G Q35
2 SUSP @ HOLEA@ HOLEA HOLEA @ HOLEA @ HOLEA@ HOLEA@ HOLEA @ HOLEA
R434 R435 S 2N7002_SOT23
G
3

S
3

10K_0402_5% 10K_0402_5%
1

1
4 4

H25 H26 H27


@ H_c236D118 H_c157D118 @ H_O138X107D118X87
For CPU

Compal Electronics, Inc.


1

Title
SCHEMATIC, M/B LA-2642P
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
401380
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: 星期五, 七月 29, 2005 Sheet 33 of 48
A B C D E
5 4 3 2 1

Detector
Vin Detector Threshold:
Low > High: 13.757V
High > Low: 13.160V

VIN
D PC167 D
ADPIN PL1 0.1U_0402_10V6K PR249
PJP1 PF1 FBMA-L18-453215-900LMA90T_1812 4.7K_0402_5%
10A_65VDC_451010 1 2 1 2
1 1 1 2 ADPIN 1 2 PR4
1K_0402_5%
PR1 1 2
1M_0402_1% ACIN 31,38
2
2 1 2

1000P_0402_50V7K

1
VL VIN

1000P_0402_50V7K
VIN

1
PC2

PC4

0.01U_0402_25V7Z
3 3 PC1 PC3 PR256

1
@ 1K_0402_5%

1
100P_0402_50V8J PR2 PR3

1
PC5
4 4 100P_0402_50V8J 60.4K_0402_1% 10K_0402_5%

2
2

2
SINGA_2WA-8291T041 PR5

2
8
22K_0402_1%
1 2 3

P
+ PACIN
O 1 PACIN 36,37

20K_0402_1%
100P_0402_50V8J
2 -

G
1

1
PC6

PR6
PU1A

4
PC7 LM393M_SO8 PR7
1000P_0402_50V7K PD29 10K_0402_5%

2
MMPZ5229BPT_SC76

2
PR8
10K_0402_5%
2 1
C RTCVREF C

3.3V
VIN
CHGRTCP

PD1
2

2 1 PD2 VS
VMBA PR9
RB751V_SOD323 1 2
1N4148_SOD80 B+
PD3 PQ57 1K_1206_5%
1

2 1 TP0610K-T1-E3_SOT23
VMBB
PR235
RB751V_SOD323 CHGRTCP PR11
1 2 3 1 N3 1 2
1

RTCVREF
0.1U_0603_25V7K

1K_1206_5%
47_1206_5%
470K_0402_5%

470K_0402_5%
PR18 PC9
1

PR15 PR16
2

2
3.3V
PU2 G920AT24U_SOT89 200_0603_5% PR13 47K_0402_5% 1M_0402_1%
PR19 PR20
1 2 VL 1 2 2 1
2

PR247

PR241
1 2 1 2 3 2 B+
+CHGRTC

2
OUT IN 1K_1206_5%
1

560_0603_5% 560_0603_5% PC10 PD5


1

1
1

GND RB715F_SOT323

1
470K_0402_5%
PC11 1U_0805_50V4Z 2
2

10U_0805_10V4Z 1 6,18,35,38,40 MAINPWON PR17


1
2

2
3 287K_0402_1%
36,37 ACON
PR242

PU1B

2
8
B LM393M_SO8 B
2 5

P
1

37 GA +

100P_0402_50V8J~N
1 7 O

287K_0402_1%
37 GB 3 - 6
1

1
162K_0402_1%
0.1U_0603_25V7K

1
PR21

PR22

PC12
PD6

4
1

PC13
RB715F_SOT323

2
2 2

2
36 ACOFF##

PQ61 PQ58
DTC115EUA_SC70 DTC115EUA_SC70
3

1
PC168 D PR23
4.7U_0805_6.3V6K 2 1 2 PACIN
G 47K_0402_5%
1

1
PJP16 PQ2
Case 1: ACIN pre-chg threshold. S

3
PC169 @ JUMP_43X118
4.7U_0805_6.3V6K 1 1 2N7002_SOT23
2 2
2

+1.2VS PJP2 +3VALW


+1.2VMVCORE @ JUMP_43X118
Low > High: 13.393V 2
+1.2VSP 1 1 2 2 +1.2VS High > Low: 11.980V PQ3
PJP17
@ JUMP_43X118 DTC115EUA_SC70

3
+1.2VMVCORE 1 1 PJP4
2 2 +1.2VMVCOREP @ JUMP_43X118

+VCCPP
1 1 2 2 +VCCP Case 2: BATT pre-chg threshold.
PJP3 PJP6
@ JUMP_43X118 @ JUMP_43X118 2 PR183 1
Low > High: 7.547V
A +1.8VALWSB A
+3VALWP 1 1 2 2 +3VALW 1 1 2 2
0_0402_5% High > Low: 6.134V
PJP5 PJP8
@ JUMP_43X118 @ JUMP_43X118
1 1 +1.8VALWP
2 2 1 1 2 2 +1.8VALW

PJP7 Compal Electronics, Inc.


@ JUMP_43X118 PJP9 Title
+5VALWP 1 1 2 2 +5VALW +0.9VSP
@ JUMP_43X118 SCHEMATIC, M/B LA-2642P
1 1 2 2 +0.9VS THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401380 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: 星期五, 七月 29, 2005 Sheet 34 of 48
5 4 3 2 1
5 4 3 2 1

D D

PH1 under CPU botten side :


CPU thermal protection at 86 +-3 degree C
Recovery at 51 +-3 degree C

C C

VL VL
1

2
PC15
1

@ 0.1U_0402_10V6K PC16 6,18,34,38,40 MAINPWON


2

PH1 0.1U_0603_25V7K
CPU

1
100K_0603_1%_TH11-4H104FT
VL
2

PR25
499K_0402_1%

2
1 2
1

PR26
PR27 499K_0402_1%

RHU002N06_SOT323
0_0402_5%
PR28

1
8

200K_0402_1% PU7A
2

8
D PU7B
1 2 3
P

PQ4
1 2 5

P
O G +
VL 1 2 2 - O 7
1

PR29 S 6

3
-

G
100K_0402_1% LM393M_SO8
4

LM393M_SO8

4
PR30
1

B 20K_0402_1% B
2
1

PC17 PR31
0.22U_0603_16V7K 100K_0402_1%
2

2
2

PC18
1000P_0402_50V7K

A A

Compal Electronics, Inc.


Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
SCHEMATIC, M/B LA-2642P
PROPRIETARY NOTE TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom 401380 B

Date: 星期五, 七月 29, 2005 Sheet 35 of 48


5 4 3 2 1
A B C D

PQ5
Iadp=0~4A AO4407L_SO8~N
P2 P3 B+ 1 S D 8
PQ7 PR32 2 7
PQ6 S D
0.015_2512_1% PL12 3 S D 6
AO4407L_SO8~N AO4413L_SO8~N 5
D

G
VIN 8 D S 1 1 S D 8 2 1 1 2 B++

0.1U_0603_25V7K

2200P_0402_50V7K
7 2 2 7 FBM-L11-322513-151LMAT_1210

4
D S S D

2
6 D S 3 3 S D 6 4 3

PC23
5 5 PC19 PC20 PC21 PR33
D D

PC22
4.7U_1206_25V6K 470K_0402_5%

2
1
PC154 4.7U_1206_25V6K 4.7U_1206_25V6K

2
1

1
1 0.01U_0402_25V7Z 1

1
PR194 PR36
4.7K_0603_5% BATT+
PR34 4.7K_0402_5%

2
@ 39K_0402_5%

2
PR35 2
2

2
1M_0402_1%
PQ60
1 2

1
PR37 PU4 DTC115EUA_SC70

3
22K_0402_5% 31 ADP_I VIN
1 -INC2 +INC2 24

3
2
1
1

C PR39 PQ8 PR244

S
S
S
2 2 1 2 23 AO4407L_SO8~N 2 1
OUTC2 GND

RLZ16B_LL34
100K_0402_5%
B 100K_0402_1% PC24 4 G ACOFF 31

2
E 0.022U_0402_16V7K~N 220K_0402_5%
3

1
PR38
PQ9 3 22 CS7 1 2
PMBT2222_SOT23 +INE2 CS PD7
2
PC25

2
D
D
D
D
PD9 4 21 1 2 PD10

1
-INE2 VCC(o)

1
34 ACOFF##

1SS355_SOD323
PR40 ACOFF#

5
6
7
8

1SS355_SOD323
1N4148_SOD80 PC26 PR42 0.1U_0603_25V7K

2
34.8K _0402_1% 1 2 1 2FB8 5 20 DH7 2 1 HG7 PD8
1

PC27 PR41 10K_0402_5% FB2 OUT PR245


1 2

1
1
10K_0402_1% 1500P_0402_50V7K PC28 PR197 47K_0402_5%

2
PR43 6 19 1 2 0_0603_5%

1
2.2K_0402_5% 0.1U_0402_16V7K VREF VH

1
1

1
PC30 PR44 0.1U_0603_25V7K PC31 C PQ59
PC29 1 2 1 2FB7 7 18 1 2 2 2
0.1U_0402_16V7K 1K_0402_5% FB1 VCC LX7 B

2
2 1000P_0402_50V7K 0.1U_0603_25V7K E PMBT3904_SOT23 PQ10 2

3
8 -INE1 RT 17 1 2
PR45 DTC115EUA_SC70

3
PR46 68K_0402_5% PR47
PD11 PD31 1 2 9 16 PL2 0.02_2512_1% BATT+
31 IREF +INE1 -INE3
ACOFF# 1 2 1 2 10UH_D104C-919AS-100M_4.5A_20%
PQ11 143K_0402_1% PR49 PC32 1 2 1 2
1

DTC115EUA_SC70 2 1 10 15 FB91 2 1 2
RB751V_SOD323 RB751V_SOD323
1
PR48 10K_0402_5% OUTC1 FB3 47K_0402_5% 3 4

1
PR50 1500P_0402_50V7K

1
PR51 100K_0402_1% PC33 11 14 PD12 PD13
OUTD CTL FSTCHG 31,37

1
PACIN1 2 1 2 2 0.1U_0402_16V7K PC35
34,37 PACIN
2

CTL pin = 0 > EC31QS04 EC31QS04 PC34 PC36


2
2

3.3K_0402_5% PR204 12 13 4.7U_1206_25V6K


>Charger Shutdown.

2
47K_0402_5% PC170 -INC1 +INC1 4.7U_1206_25V6K 4.7U_1206_25V6K

2
470P_0402_50V8J
1

ACON MB3887_SSOP24
34,37 ACON

IREF=1.0288*Icharge
IREF=0.6V~3.21V
Ciss <>50pF. PR52
4.2V PR53
Turn-On <> 130nS. 2 1 2 1
(PR3 (10K) + PR45 (3K) to 100pF) 150K_0603_0.1% 300K_0603_0.1%

3
CC=0.6~3.3A 3

CV=12.6V(6 CELLS LI-ION)


Vadp=15V
OVP voltage : LI
BATT+ PR198
3S2P : 13.5V--> BATT_OVP= 1.5V PQ44
B+ 1 2 3 TP0610K-T1-E3_SOT23
1 B+_BIAS
(BAT_OVP=0.1112 *BATT+)

0.1U_0805_25V7M
470K_0402_5%
100_0805_5%

1
PR54
I limit: 3.72A

2
VIN 340K_0402_1% +5VALW PD30

PR205
0.01U_0402_25V7Z
PC147
RLZ18B_LL34

1 2

1
2

2
1
PC210

1
1

1SS355_SOD323
220K_0402_5%
PR55
D.A.C.A. (C.P.) on 60W adaptor: Take PR41= 10K

2
499K_0402_1%

PR206
4A*0.015*20 = 5*PR41/(PR41+PR40)<> PR40<>34.8KK
8

PU5A

PD36

PQ45
2N7002_SOT23
LM358NOPB_SO8 3
P

2
+
1 0

1
31 BATT_OVP

1
D
Fast charge current <> 3.3A, - 2
G

0.01U_0402_25V7Z
2
1

0.1U_0603_16V7K
PR56 G
3.3A*0.02*20/[(3.21V- 3.3A*0.02*20)/PR46] <> PR50
4

PC37

220K_0402_5%
PR57 S

3
2
PR46 <> 143K

1
PC171

PR207
105K_0402_1%

2
4 2.2K_0402_5% 4
2

1
Trickle charge current <> 0.6A, PU5B
LM358NOPB_SO8
0.6A*0.02*20/[(0.6V- 0.6A*0.02*20)/PR46] <> PR50 7 0
+ 5

PR46 <> 143K - 6 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY Compal Electronics, Inc.
OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE Title
SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE SCHEMATIC, M/B LA-2642P
CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS
AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR Size Document Number Rev
THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY 401380 B
THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,
INC. Date: 星期五, 七月 29, 2005 Sheet 36 of 48
A B C D
5 4 3 2 1

Ciss<3000pF. Ciss<3000pF.
Qg<>40nC. Qg<>40nC.
PC38 PC39 Battery Selector

1
1000P_0402_50V7K VMBA P5 BATT+ P4 VMBB 1000P_0402_50V7K
PQ12 PQ13 PQ14 PQ15
PF6 AO4407L_SO8~N AO4413L_SO8~N AO4413L_SO8~N AO4407L_SO8~N PF7

2
PBJ1 12A_65VDC_451012 PL3 8 PL4 12A_65VDC_451012 PBJ2
D S 1 1 S D 8 8 D S 1 1 S D 8
1 1 2 1 1 2 7 D S 2 2 S D 7 7 D S 2 2 S D 7 2 1 2 1 1 1
2 FBMA-L18-453215-900LMA90T_1812 6 FBMA-L18-453215-900LMA90T_1812
2 AB/I D S 3 3 S D 6 6 D S 3 3 S D 6
BB/I
2 2
3 3 5 D D 5 5 D D 5 3 3

G
39K_0402_5%
4 TSA TSB 4 4
4
5 5 5

4
5

2
39K_0402_5%
0.01U_0402_25V7Z

0.01U_0402_25V7Z
D D
6 6 6 6

1
PR59
7 7 7 7

PC40

PR61

PC41
PR58 PR60
SUYIN_250233MR007GX26ZU 1K_0603_5% 1K_0603_5% SUYIN_250233MR007GX26ZU

2
1 . B AT + @
1

1
@
2.ID

2
3 .B/I 1 2 1 2
4. TS PR62 PR63
22K_0402_5% 22K_0402_5%
5.SMD 2 1 +3VALWP 1 . B AT +

1
6.S MC PR64
C C
2.ID
2 2 1 2
7.GND 6.49K_0402_1% B B
+3VALWP
3 .B/I
E E PR65
4. TS

3
2

6.49K_0402_1%

2
PQ16 PQ17
5.SMD
2

2
PR68 PR69 PR66 PMBT2222_SOT23 PMBT2222_SOT23
100_0402_5% 100_0402_5% 1K_0402_5%
PD14 PD15
PR67
1K_0402_5%
6.S MC
7.GND
1

1N4148_SOD80 1N4148_SOD80

1
1

1
BATT_TEMPA 31
2 1 2 1
PR70
31 BATT_TEMPB

1
2.2K_0402_5% PR71
2.2K_0402_5%
EC_SMB_DA1 31,32

2
EC_SMB_CK1 31,32 GB PR72 PR73
34 GB 2
100_0402_5% 100_0402_5%

2200P_0402_50V7K
34 GA 2

1
C PQ19 C

1
2

1
2200P_0402_50V7K

PC172
DTC115EUA_SC70 EC_SMD2

3
GA PQ18 PD32 6,31 EC_SMB_DA2
2

RB751V_SOD323
PC173

PD33 DTC115EUA_SC70
3

2
EC_SMC2

2
RB751V_SOD323 6,31 EC_SMB_CK2
2

1
PR75
PR74 10K_0402_5%
1

10K_0402_5%

0.01U_0402_25V7Z
VL VL VMBB
Turn-On Delay PU6
7

<> (10K + 3K + 100K) * (100pF+50pF) VL 74HC253 {Vbatt_max *[499K/(499K+649K)]+V_dischg}


* {1- exp^[-ǻt/(R*C)]}
1Y

2Y

GND

<> 4uS.
2

2
Turn-Off < 2uS. > {Vbatt_max *[499K/(499K+649K)] +V_dischg}

PC42
16 PR76
VCC 100K_0402_5% PR77 -RTCVREF +V_hysteresis

2
PU3B PR79 649K_0402_1%
1EN
2EN

8
1C0
1C1
1C2
1C3

2C0
2C1
2C2
2C3

LM393M_SO8 100K_0402_5%
S0
S1

1
1

5 2 1 Sense Delay Time by hysteresis and R/C

P
PC43 +
2 1 7 is about 24.8uS.
6
5
4
3

10
11
12
13

14
2
1
15

2
PR78 0.1U_0402_16V7K 6
2

1
1 2 PR208 PR80
34,36 ACON
27K_0402_1% 27K_0402_5% 4 PR81 PC44
100K_0402_5% 499K_0402_1% 47P_0402_50V8J
2nd B Battery Detector

2
1 2

1
2 1
High:8.117V
100P_0402_50V8J

PR82 Low :7.36V


2

5.6M_0603_5%
PC45

B RTCVREF B
1

2
1

PQ20 VL VMBA
DTC115EUA_SC70
PQ46
2

DTC115EUA_SC70 PR85
3

2
2 10K_0402_5%
31,36 FSTCHG
PR86 PU3A
100K_0402_5% LM393M_SO8 PR87
PR83 PR88 649K_0402_1%
1
8

1 2 100K_0402_5%
3

1
100K_0402_1% 3 2 1
Main A Battery Detector
P

+
2 1 1 O
1 PR84 2 - 2 2 High:8.117V
G

1
PR89
1

100K_0402_1% 27K_0402_5% PR90 PC46 Low :7.36V


4
1

PC47 499K_0402_1% 47P_0402_50V8J

2
100P_0402_50V8J
2

A/B#USE 2 1
High: Main Battery (A) 31 A/B#USE 2
PR91
Low : Second Battery (B) 5.6M_0603_5%
PQ21 TRICKLE EC Override time:
DTC115EUA_SC70
<> 3* (R-C) charging time
3

PR92
<> 3* (1K * 1000pF)
1

D 47K_0402_5%
<> 3uS. 2 1 2 PACIN 34,36 When in Trickle charge, battery
PQ22 G
is selected by EC "A/B#USE" pin
S0 S1 nC0 nC1 nC2 nC3 nOE nY RHU002N06_SOT323 S
3

PD17
A X X X X X X H Z 2 1 TRICKE 31
A

L L L X X X L L 1N4148_SOD80
L L H X X X L H
H L X L X X L L
H L X H X X L H
L H X X L X L L Compal Electronics, Inc.
L H X X H X L H Title
H H X X X L L L SCHEMATIC, M/B LA-2642P
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
H H X X X H L H AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401380
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: 星期五, 七月 29, 2005 Sheet 37 of 48
5 4 3 2 1
5 4 3 2 1

B+ +3.3V/+5V

2
PF3
10A_65VDC_451010

1
FBM-L11-322513-151LMAT_1210
D D
1
1

PC166
4.7U_1206_25V6K

2
2

PC155 @
2

PL13

PL5
0.01U_0402_25V7Z PC48
PR95 PR96
PC49 4.7U_#892NAS-4R7M=P3_5.6A_20%
1 2 1 2 2 1 1 2 1 2
1

0.1U_0402_16V7K
0.1U_0402_16V7K 0_0603_5% 0_0603_5%
B+++

3
B+++

DAP202U_SOT323
PQ23 PR93 PD18
1 8 HG2 1 2 VS

1
D1 G1
2 D1 S1/D2 7
3 6 0_0603_5%
G2 S1/D2

5
6
7
8
4 S2 S1/D2 5 PR94 I-thermal=0.05A, PQ24
SI4810BDY-T1-E3_SO8

D
D
D
D
I-OCP=0.1A.
0.1U_0603_25V7K

SI4914DY-T1-E3_SO8 10_1206_5%
VL
1

PC50 PC52

G
S
S
S
PC53
4.7U_1206_25V6K
2

4
3
2
1
2
PC51

4.7U_1206_25V6K PC56
@ 2200P_0603_50V7K

0.1U_0603_25V7K
HG1 4.7U_1206_25V6K

1
PD19

DH2

1
1SS355_SOD323 PC54 PC58

PC57
4.7U_0805_6.3V6K PC55

2
C LX2 4.7U_1206_25V6K C

2
5
6
7
8
@ 2200P_0603_50V7K

1
1
DL2 PC60 PQ25 PC61
PC62 PC59 100P_0402_50V8J AO4704L_SO8~N 47P_0402_50V8J

2
100P_0402_50V8J @

2
1U_1206_25V4Z 4
1 2

2
PR97
1

1.1K_0402_1% PR98

3
2
1
PL6 0_0603_5%

22

21
1

PR99 PU8

1
4.7U_#892NAS-4R7M=P3_5.6A_20% PC64 1K_0402_1% BST2 25 4

V+

VL
BST3 COMP3

1
47P_0402_50V8J 5
2

COMP5 BST1 PR100


@ 27 18
2

PC65 DH3 BST5 DH1 @ 2M_0402_1%


DH5 16
2 1 26 17 LX1
PHASE3 PHASE5 DL1
24 19

2
DL3 DL5
Use DCR * 1.3 0.47U_0603_16V7K
PGND 20
@ 1M_0402_1%

14 CS1+ 2 1
to calculate O.C.P. CSH5
2

PR103 CS2+ 1 13
CS2- CSH3 CSL5 PR101
1 2 2 CSL3 FB5 12
PR102

+3VALWP 0_0402_5% 3 15 1.62K_0402_1%


FB3 SEQ

1
10 9 2.5VREF PC66
PSAVE# REF
23 6 PR104
1

FB2 SHDN# SYNC 0.47U_0603_16V7K


11

2
RESET# 715_0402_1%
SKUL30-02AT_SMA

0.022U_0402_16V7K~N

7 ON5
3.57K_0402_1%

31,34 ACIN 1 2 Use DCR * 1.3

2
2

1
PD20

28
GND

ON3 to calculate O.C.P.


1

1
PR107

PC69

PC68 1 PC67 PR106


1

1
100P_0402_50V8J 10K_0402_5% PR255
2

1
150U_D_6.3VM_R18M

B + 15K_0402_5% PC213 SC1403ITSTR_TSSOP28 PC70 CS1- B


+5VALWP
2

PR108 0.1U_0402_16V7K 4.7U_0805_6.3V6K


1

2
@ 300K_0402_5%
2

2
f=300KHz
2

1
VL

150U_D_6.3VM_R18M
PR237 PR232 VL
2

0_0402_5% 0_0402_5% PC71


2 1 2 1 0.1U_0402_16V7K PC72 1
MAINPWON 6,18,34,35,40

2
1

1
CHGRTCP

10.2K_0402_1%
PR111
1

1
PD21 +
PR233 220K_0402_5% PC73
1

PR109
0_0402_5% 100P_0402_50V8J SKUL30-02AT_SMA

2
2

2
200K_0402_5%

PR112 PR234 @ PU16


2

2
2

3
200K_0402_5%

(3V*5%)/5.3A=28.3mOhm ESR PR110 47K_0402_5%


2

2
10K_0402_1% 1
G

I1 MAINPWON 6,18,34,35,40
PR105

4
2

O
2 AUX_S5EN 31 (5V*5%)/7.8A=32mOhm ESR
1

I0
P

FB1
1

TC7SH32FU_SSOP5
5

@ @ PR200
@ PC75
2
1

1
PC76 @ 0.47U_0603_10V7K PC153 @ 220K_0402_5%
2
SYSON

PC148 @ 0.01U_0402_25V7Z PR113 delta I= (Vin-Vo)*D/L*f=[(15-5)*(5/15)]/4.7u*300K=2.364


EC_ON

0.047U_0603_25V7M 31,32 2 1 10K_0402_1%


2

@ VL delta Vripple=deltaI*ESR=2.364*25m=59.1mV
@ 0.1U_0603_25V7K

2
CSH5-CSL5=48mV, OCP=7.8A, DCR=18mOhm
31,33,39

CSH3-CSL3=48mV, OCP=5.3A, DCR=18mOhm VL


Rsens=48mv/7.8A=6.15mOhm
Rsens=48mv/5.3A=9mOhm
1

C*R1=L/Rsens<> 0.47UF*PR100=4.7UH/6.15mOhm
C*R1=L/Rsens<> 0.47UF*PR96=4.7UH/9mOhm<> PR97=1.1K Ohm PC74
0.1U_0402_16V7K <> PR101=1.62K Ohm
2

A
R2=R1*Rsens/(Iload*DCR)-Rsens A

R2=R1*Rsens/(Iload*DCR)-Rsens
PR99=PR96*Rsens/(Iload*DCR*1.3)-Rsens
PR104=PR100*Rsens/(Iload*DCR*1.3)-Rsens
PR99=1.13K*48mV/{(5.3A*15mOhm*1.3)-48mV}=976Ohm
PR104=1.62K*48mV/{(7.8A*18mOhm*1.3)-48mV}=576 Ohm
delta I= (Vin-Vo)*D/L*f=[(15-3)*(3/15)]/4.7u*300K=1.7
delta Vripple=deltaI*ESR=1.7*25m=42.5mV
Title
Compal Electronics, Inc.
SCHEMATIC, M/B LA-2642P
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401380 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: 星期五, 七月 29, 2005 Sheet 38 of 48
5 4 3 2 1
A B C D

1 B++++ 1

PL14
PF4
FBM-L11-322513-151LMAT_1210
2 1 2 1 B+

7A_24VDC_429007.WRML

2200P_0402_50V7K

2200P_0402_50V7K
1

1
+5VALW

0.1U_0603_25V7K
PC77
PC78 PC79 PC80 PC83

1
PC156

2
PC81

PC82
0.1U_0603_25V7K PC84 0.01U_0402_25V7Z

2
4.7U_1206_25V6K 4.7U_1206_25V6K 4.7U_1206_25V6K

2
4.7U_1206_25V6K

1
PC85 @

5
6
7
8
4.7U_0805_6.3V6K

8
7
6
5
PD28

D
D
D
D
2
RB717F_SOT323 PQ27

D
D
D
D
PQ26
RSS090N03_SO8

G
S
S
S
RSS090N03_SO8

3
G
S
S
S
+1.2VS

4
3
2
1
+1.2VSP +1.8VALWP

1
2
3
4
1.5uH_SIL104-1R5_10A_30% PC88 MAX8743_VCC PC89
PL7 0.1U_0402_16V7K PR116 0.1U_0402_16V7K PL8
1 2 2 1 1 2 PC87 PR115 1 2 2 1 LX4 1 2
PR114 1U_0603_10V6K 1 2
0_0603_5% 0_0603_5% 2.7u_SIQHB1250-2R7PF_12A_20%

BST3

1
2 PC86 20_0603_5% 2
2

8
7
6
5

5
6
7
8
0_0402_5%

0.1U_0603_25V7K
2
PR250

PQ29

2
PR251 AO4704L_SO8~N
10_0402_5% PC93

22
4

9
@ PU9 @ 220U_D2_4VM_R15

BST4
1

4 25 21 4 1 1

UVP
VCC
V+
1

BST1 VDD

1
10U_0805_6.3V6M

1 PC136
AO4704L_SO8~N
1
PC135

PC94 PD24 DH3 26 19 @ 10U_0805_6.3V6M + +


DH1 BST2
1

1
220U_D2_4VM_R15 + PQ28 18 DH4
PR117 LX3 DH2 PR118
27 17
1
2
3

3
2
1
@ SKS10-04AT-G_TSMA 2.05K_0402_1% LX1 LX2 DL4 PC92 2 2
24 20
2

2
2 DL3 DL1 DL2 8.06K_0402_1% PD23 220U_D2_4VM_R15
16
2

CS2 @ SKS10-04AT-G_TSMA
28
1

1
CS1
1 OUT1 OUT2 15
@ 14 FB4
FB3 FB2
2 FB1 ON2 12 2 1 +5VALW
7 PR119
PGOOD

2
+5V PR120
TON 5 0_0402_5% (1.8V*5%)/11.7A=7.69mOhm ESR
1 2 11 PR121
ON1
1

13 10K_0402_1%
PR122 0_0402_5% ILIM2
3

SKIP
GND
OVP

REF
ILIM1
2

(1.2V*5%)/9.8A=6mOhm ESR 10K_0402_1%

1
PR220
100K_0402_5% MAX8743EEI+T_QSOP28~N
2

23

10
2 PR123
1
1

12.7K_0402_1%
SUSP_DLY# 42 2 PR124 1 Use Rds(on) * 1.5
to calculate O.C.P.(9.83A~14.14A)
1

1
PR222 D 61.9K_0402_1%

1
1 2 2 PR126
3
23,33,40 SUSP 3

47K_0402_5%
G
PQ50
PC98
0.22U_0603_16V7K
PR125 100K_0402_1%
For 1.8V output
S
3

2
Use Rds(on) * 1.5 2N7002_SOT23 39.2K_0402_1% Iimit=(VILM2*0.1)/Rds(on) +1/2DeltaI Delta I2=2.3A

2
to calculate O.C.P.(8.43A~12.23A)
1

PC185
VILM2=1.77V Rds(on) typ=10.5mOhm , max=13mOhm
0.1U_0603_16V7K Iimit Min=(1.77*0.1)*0.85/(13m*1.3)+1/2*2.3= 10.05A
2

For 1.2V output


Iimit Max=(1.77*0.1)*1.1/(10.5m*1.3)+1/2*2.3= 15.41A
Iimit=(VILM1*0.1)/Rds(on) Delta I1=2.13A
VILM1=0.775V Rds(on) typ=10.3mOhm , max=13mOhm Rds_ls=13mOhm , R125=39.2KOhm , VREF=2V,Iload=5.5A Rds_ls=13mOhm , R126=100KOhm , VREF=2V,Iload=11.5A delta Vripple=deltaI*ESR=3*7.5m=22.5mV
Iimit Min=(0.775*0.1)*0.85/(13m*1.3)+1/2*2.13= 4.963A delta I1=(Vin-Vo)*D/L*f=[(15-1.2)*(1.2/15)]/1.5u*345K=2.13A delta I2=(Vin-Vo)*D/L*f=[(15-1.8)*(1.8/15)]/2.7u*255K=2.3A
Iimit Max=(0.775*0.1)*1.1/(13m*1.3)+1/2*2.13= 5.947A [Iload-(0.5*delta I1)]*Rdson*1.5=VREF*[PR125/(PR124+PR125)]*0.1 [Iload-(0.5*delta I2)]*Rdson*1.5=VREF*[PR126/(PR123+PR126)]*0.1
[5.5-(0.5*2.13)]*13m*1.3=2*[39.2K/(PR124+39.2K)]*0.1 [11.5-(0.5*2.3)]*13m*1.3=2*[100K/(PR123+100K)]*0.1
delta Vripple=deltaI*ESR=2.2*7.5m=16.5mV
PR125=61.9K PR123<>12.7K

4 4

Compal Electronics, Inc.


Title
SCHEMATIC, M/B LA-2642P
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
B 401380 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: 星期五, 七月 29, 2005 Sheet 39 of 48
A B C D
5 4 3 2 1

0.9VSP/VCCP

PU13
+1.5VS
+3VALW 2 PR184 1 1 IN OUT 5

1
0_0402_5%
PC137 4
4.7U_0805_6.3V6K BYP

1
D D
3 SHDN GND 2
PC138
+1.2VS 4.7U_0805_6.3V6K

2
1
+5VS PR185 G914G_SOT23-5
PJP14 2 1 PC144
31,32,33 SUSP#

1U_0603_10V6K
0_0402_5% 0.01U_0402_25V7Z

2
2

2
+1.2VS @ JUMP_43X118

PC99
PR186

2
100K_0402_5%

1
1K_0402_5%

1
1

1
PR127

1
PR128 PC100
@ 1K_0402_5% 10U_0805_6.3V6M
2

1.05V +-5% @3.1A

2
2

6
PU10 6A current limit @125 degree C
5

VCNTL
VIN
+VCCP_PWRGD 7 POK
VOUT 3 +VCCPP

316_0402_1%
VOUT 4 1

10U_0805_6.3V6M
1

PC103
8 2 + PC101
EN FB

PR129
220U_D2_4VM_R15
GND

9 @ PR199 PU17

2
VIN 2
PR130 APL5912-KAC-TRL_SO8~N 0_0402_5% +3V_EC
31,32,33 SUSP# 1 2 PC102 VL 2 1 1 5
1

2
0.01U_0402_25V7Z IN OUT
0_0402_5%
This output capacitor is @ 4 BYP
1

C @ C

1
PR257 PC104
in parallel with H/W capacitor. 3 SHDN GND 2

1K_0402_1%
1 2 0.1U_0402_16V7K PC149 PC150
31 VR_ON
2

@ 0_0402_5% @ 4.7U_0805_6.3V6K @ 4.7U_0805_6.3V6K

2
1
PR131
G914C_SOT23-5
PC151
@ 0.01U_0402_25V7Z @

2
VL @
+3V_EC +3VALW
PJP20

2
2 1
PR201
200K_0402_5% PAD-OPEN 2x2m
@
@ PQ42

1
AOS3414_SOT23

D
3 1
@

G
2
PU14
@
PR236 +2.5VS
1

+1.8V D
+3VALW 2 PR187 1 1 IN OUT 5

1
1 2 2 0_0402_5%
6,18,34,35,38 MAINPWON
G @ PC139 4
1M_0402_5% S PQ43 4.7U_0805_6.3V6KBYP
3

2
1

1
@ 3 SHDN 2
PC152 2N7002_SOT23 @ GND PC140
2

B 0.47U_0603_10V7K 4.7U_0805_6.3V6K B
2

2
@ PR188 G914E_SOT23-5 @
2

1
PJP15 2 1 @
31,32,33 SUSP#
@ JUMP_43X118 0_0402_5% PC145

2
1

@ 0.01U_0402_25V7Z

2
PR189 @
1

PU11 100K_0402_5%
1 6 +5VS @
VIN VCNTL

1
1U_0603_10V6K

2 GND NC 5
1

2
1

PC106

PC105 3 7
VREF NC
10U_0805_6.3V6M PR132 0.9V +-40mV@2A
2

10K_0402_1% 4 8
VOUT NC
2.6A current limit @125 degree C
9
2

TP PU15
APL5331KAC-TR_SO8 +1.8VALWSB
+3VALW 2 PR190 1 1 IN OUT 5 2 PR191 1

1
@ 0_0402_5% @ 0_0402_5%
1

PR133 D PC141
+0.9VSP 4
1 2 2 PQ30 PC107 4.7U_0805_6.3V6KBYP
23,33,39 SUSP

1
220U_D2_4VM_R15

G 2N7002_SOT23 PR134 0.1U_0402_16V7K 1 @ 3 2


2

SHDN GND
PC108
10U_0805_6.3V6M

0_0402_5% S 10K_0402_1% PC142


3
1

+ 4.7U_0805_6.3V6K
2

2
PC110

PC109 PR192 G914H_SOT23-5 @

1
0.1U_0402_16V7K 2 1 @
6,18,34,35,38 MAINPWON
2

2 @ 0_0402_5% PC146

2
0.01U_0402_25V7Z

2
PR193 @
@ 100K_0402_5%
@
A A

1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY Compal Electronics, Inc.
OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE Title
SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE
CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS
SCHEMATIC, M/B LA-2642P
AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR Size Document Number Rev
THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY Custom 401380 B
THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,
INC. Date: 星期五, 七月 29, 2005 Sheet 40 of 48
5 4 3 2 1
5 4 3 2 1

delta I= (Vin-Vo)*D/L*f=[(15-1.308)*(1.308/15)]/(.56u*300K)=7.1A
CPU CORE B+
CPU_B+
+5VS
OCP=41A(TYP), DCR=1.4mOhm PL9
PF5

PR135 10_0402_5%
FBM-L11-322513-151LMAT_1210
Ilimit(min) per phase=41/2-7.1/2=16.95A 1 2 2 1

2200P_0402_50V7K
0.1U_0603_25V7K
16.95A*1.4mOHM(DCR)*1.3(temperature factor)*20=VLLIM(TYP)=0.61698V 7A_24VDC_429007.WRML

220U_25V_M
1

1
PC114

PC115
Take PR156=200K, PR158=90.9K PC111 PC112

PC113
+
VILIM=VREF*PR158/(PR158+PR156)=0.625(TYP) PC157

2
4.7U_1206_25V6K 0.01U_0402_25V7Z

2
2
VILIM/20=Ilimit*DCR*1.3 4.7U_1206_25V6K

5
6
7
8
D D

OCP(TYP)=(0.625/20/1.3/1.4mOHM+delta I/2)*2=41A

2
PC116

0.01U_0402_25V7Z
OCP(min)=((0.625/20-2mV)/1.3/1.4mOHM+delta I/2)*2=38.83A PC117

2
1U_0603_10V6K 2.2U_0603_6.3V6K PQ31

1
OCP(max)=((0.625/20+2mV)/1.3/1.4mOHM+delta I/2)*2=43.23A PU12 4 C*R>=L/DCR<> 0.47UF*PR147=0.56UH/1.4mOhm

0.22U_0603_16V7K
PC118
IRF7821PBF_SO8~N
<> PR147=851Ohm<>866 Ohm

1
2

PC119
1532VCC 10 30
VCC VDD PL10 +CPU_CORE

3
2
1
2 PR136
1 24 36 PR144
7 CPU_VID0 0_0402_5% D0 V+ .56UH_MPC1040LR56_ 23A_20% 0.001_2512_5%
2 PR137
1 23 26 BST5 1 PR138 2
7 CPU_VID1 0_0402_5% D1 BSTM
1532VCC 1 PR139 2 2.2_0603_5% 1 2 1 2
@ 0_0402_5% 2 PR140
1 22 28 DH5 1 PR141 2 HG5
7 CPU_VID2 D2 DHM

866_0603_1%
IRF7832PBF_SO8~N
0_0402_5% 0_0603_5% 3 4

IRF7832PBF_SO8~N
1532REF 1 PR142 2 2 PR143
1 21 27 LX5
7 CPU_VID3 D3 LXM

5
6
7
8

5
6
7
8

PR152 10_0402_5%
@ 0_0402_5% 0_0402_5%
2 PR145
1 20 29 DL5
7 CPU_VID4 0_0402_5% D4 DLM
1 PR146 2

2
0_0402_5% 2 PR147
1 19 31
7 CPU_VID5 0_0402_5% D5 PGND

PR149
1 PR148
2 25 37 CS5+ 4 4
21 VGATE VROK CMP

499_0402_1%

499_0402_1%
0_0402_5% PC121

@ 1000P_0402_50V7K
4 38 CS5-

1
S0 CMN

2
PR153 3K_0402_1%
1 2

PC120
1532VCC 1 PR151 2 5 17 OAIN+ @

3
2
1

3
2
1
S1 OAIN+

PQ32
PR154 0_0402_5%

1
2
PQ33
1 2 6 16 OAIN- 0.47U_0603_16V7K
31 VR_ON

2
0_0402_5% PC214 PR156 SHDN# OAIN-

1
PR150

PR160
1 2 2 1 TIME 1 15 FB5
30.1K_0402_1% TIME FB
C @ 0.1U_0402_16V7K PC1221 PR157 820_0402_5% C
2 12 14 1 2

1
PR158 CCV CCI PC123 470P_0402_50V8J 1 2
1 2 270P_0402_50V7K 2 35 BST6
200K_0402_1% TON BSTS
1 2 1532REF 8 33 DH6
REF DHS

2
PR161 1 PR159 2
1 2 PC124 0.22U_0603_16V7K 9 34 LX6 3K_0402_1% PR202
90.9K_0402_1% ILIM LXS
+5VS 0_0402_5%
FB5 1 2 7 32 DL6 PD26
PR162 OFS DLS BST5 PR163
2

1
10.7K_0402_1%

100K_0402_1% 3 40 CS6+ 1 1 2 1 2
SUS CSP
2

3 0_0402_5%
VCCSENSE 7
PR164

PC126 18 39 CS6- PC125


100P_0402_50V8J SKIP CSN RB717F_SOT323 0.022U_0402_16V7K~N PR165 PR203
2
1

D
RHU002N06_SOT323

470P_0402_50V8J
11 GND GNDS 13 1 2 1 2 VSSSENSE 7
1

2
D

1000P_0402_50V7K
6,16,17 H_DPSLP# 1 PR166 2 2
1

1
CPU_B+

2.2_0603_5%
PC127

0_0402_5% G 2 100_0402_5% 0_0402_5%

PR167 2

10_0402_5%
PC128
S G PR174
3

S MAX1532AETL_TQFN40 0_0603_5% CPU Remote -


3

2
PQ35

PQ34
+3VS 1 PR169 2 RHU002N06_SOT323 PR168 - Sensing Pairs.

HG62

0.01U_0402_25V7Z
@ 100K_0402_1%

1
5
6
7
8

2200P_0402_50V7K
PR170

0.22U_0603_16V7K
1 2 PQ36 PC130 PC131
6,17 H_DPRSLP

1
0_0402_5% IRF7821PBF_SO8~N

PC133

PC129

PC132
+3VS 2 PR171 1

2
100K_0402_1% LX5 4
1

4.7U_1206_25V6K
2

PR175 4.7U_1206_25V6K
PR176 100K_0402_1% PL11
RHU002N06_SOT323

100K_0402_1%

3
2
1
B .56UH_MPC1040LR56_ 23A_20% B
1 2
1

D
1 2
PQ38

2 PR195
G 100K_0402_1%
S @
3
1

5
6
7
8

5
6
7
8

2
OAIN+ PQ39
IRF7832PBF_SO8~N PR178
7 H_PSI# 2 866_0603_1%
1

PQ41 PR196 4 4 PC134

1
100K_0402_1% 1 2
DTC115EUA_SC70 @ PQ40
3

0.47U_0603_16V7K
2

@ IRF7832PBF_SO8~N

3
2
1

3
2
1
LX6

PR181
1 2
820_0402_5%

A OAIN+ A
1 2

PC211
@ 1000P_0402_50V7K

1 2 OAIN+

PC212
@ 1000P_0402_50V7K Compal Electronics, Inc.
Title
SCHEMATIC, M/B LA-2642P
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401380 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: 星期五, 七月 29, 2005 Sheet 41 of 48
5 4 3 2 1
A B C D

PR209
+5V 2 1 PL15
0_0603_5%
1.2_B+ 2 1 B++++
1 PR210 1

1 2 FBM-L11-322513-151LMAT_1210
PC177

1
20_0603_5% PD34 1U_0603_6.3V6M PQ47
RB751V_SOD323 8 1 PC174 PC176
PU18 G1 D1

1
7 2 0.1U_0603_25V7K 4.7U_1206_25V6K

2
PC178 S1/D2 D1
11 VCC VDD 10 6 S1/D2 G2 3
1U_0603_6.3V6M PR211 PC179 PR212 5 4

1
S1/D2 S2
14 SKIP BST 15 2 1 2 1 2 1
0_0603_5% 0_0603_5% SI4914DY-T1-E3_SO8
13 1 1.2DH 0.1U_0603_16V7K
V+ DH PL16 +1.2VMVCOREP
7 16 1.2LX 1 2
PGOOD LX
PR252 PR253

1
39 SUSP_DLY# 2 PR213 1 2 SHDN DL 9 1.2DL 2.0UH_SPC-07040-2R0 GP_6A_30% PD35 +1.2VMVCORE
2 1 2 1 1
0_0402_5% 5 ILIM EP10QY03 @ 10_0402_5% 0_0402_5% +
PC180

2
PR215 PC184
PR214 2
1 2 6 REF
60.4K_0402_1% 100P_0402_50V8J 10K_0402_1% 220U_D2_4VM_R15

2
1

12 TON OUT 4
1

PC181

1
PR216 8 3 FB
2

150K_0402_1% GND FB

0.22U_0402_10V4Z
MAX1714BEEE+T_QSOP16~N FB 1.0V
2

+5V

2
2 2

2
PR217
49.9K_0402_1% PR254
200K_0402_1%
@

1
3

1
PQ55

1
TP0610K-T1-E3_SOT23 D
2
2 G
9,17,18,25 NB_RST#
S PQ48

3
2N7002_SOT23

1
PR230
10K_0402_5%
PD40
11,21 STRAP_EEPROM 2 1 2 1

RB751V_SOD323

1
PC200
PD41
1000P_0402_50V7K

2
31 NB_VCC_CNTL 2 1
3 3

@ 1SS355_SOD323

2
PR231
100K_0402_5%

1
4 4

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY


OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE Title
Compal Electronics, Inc.
SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE
CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS SCHEMATIC, M/B LA-2642P
AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR Size Document Number Rev
THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY B B
THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, 401380
INC. Date: 星期五, 七月 29, 2005 Sheet 42 of 48
A B C D
5 4 3 2 1

Version Change List ( P. I. R. List ) Page 1/3


Request
Item Page# Title Date Owner Issue Description Solution Description Rev.
1 6 Pentium-M(1/3) Nov. 19th Compal Correct circuit. Add R1031 0.2

D D
2 9, 17, 25 RS400MD-FSB/A-PCIE(1/4) Nov. 19th Compal Correct net name Easy to identify net connection between RS400MD and SB400/BCM5751M 0.2
SB400-PCIE/PCI/LPC/RTC(1/4)
BCM5751M-GLAN

3 8 CPU Decoupling/FAN(3/3) Nov. 19th Compal U2.1 and U2.3 is short togather. Correct net name of U2.3 0.2

4 21 Hardware Trap Nov. 19th Compal Fix it to follow SB400 A31 request Change the status of PCI_CLK2 to low 0.2

5 24 MINI_PCI SLOT-WLAN Nov. 19th Compal Follow Compal standard design Change the IRQ routing to IRQF# and IRQG# 0.2

6 18 P18-SB400-USB/AC97/MISC.(2/4) Nov. 19th Compal Different power plane maybe cause some leakage. Correct Power plane from +3valw to +3v to match USB_PHY_1.8v plane 0.2

7 25 BCM5751M-GLAN Nov. 19th Compal For Debug Reserve Pull-up R1030. 0.2

8 31 ENE-KB910L/TPM Nov. 19th Compal Fix S5 boot function and sequence Correct AUXS5_EN# and VGATE and VGATE_EC control type 0.2

9 32 BIOS/EE-Prom/TP/KB/SW Nov. 19th Compal Re-assignt K/B ESD cap Deleted C592. 0.2
C C

10 33 DC TO DC Nov. 22th Compal Follow M/E requirement Deleted H16, H17, H23 0.2

11 11 RS400MD-DISPLAY(3/4) Nov. 22th Compal LCD Backlight can't function. Change the control signal from BLEN" U3.D7" to BLON" U3.A6. 0.2

12 22 IDE/CD_ROM Conn. Nov. 22th Compal correct the Poly-fuse spec for HDD requirement. Change the Poly-fuse from 1.1A to 1.8A 0.2

13 25 BCM5751M-GLAN Nov. 22th Compal Reserved GPIO of KB910L for other function Change the GLAN restet timing by A_RST# signal. 0.2
31 ENE-KB910L/TPM

14 29 AC97 Codec AD1981B/MDC Nov. 24th Compal MDC be changed. Correct pin definition 0.2

15 16 ClockGen ICS951413 Nov. 24th Compal ICS951411 will function fail with CPU Speedstep Change Clock Gen from ICS951411 to ICS951413 0.2

16 RS400MD & SB400 Nov. 24th Compal For Lead-free process Change RS400MD & SB400 to Lead-Free part. 0.2

17 30 AMP./Audio Jack Nov. 24th Compal To smooth the Cable routing Swap Left and Right sound signals.--JSPK1 0.2
B B

18 31 ENE-KB910L/TPM Nov. 24th Compal Separate TPM to Module type Removed TPM Chip and add JP23 0.2

19 23 USB/BlueTooth/FP Nov. 25th Compal Bluetooth be changed Correct connector" JP10" pin define and type. 0.2

20 32 BIOS/EE-Prom/TP/KB/SW Nov. 25th Compal For M/E Requirement Change the connecotr type" JPALM1" from Cable to FFC. 0.2

21 11 RS400MD-DISPLAY(3/4) Nov. 25th Compal Reserved EEPROM" U49" debugging Delete reserved circuit for PP phase 0.2

22 11 RS400MD-DISPLAY(3/4) Nov. 25th Compal Reserved R508 for debugging Delete R508 for PP phase 0.2

23 15 TV-OUT/LVDS/CRT Nov. 25th Compal Reservd Resistors for LCD EDID Update the R87, R88, R506, R507, R504 and R505 status for PP phase. 0.2
Delete R1032 and R1049 at page 11

24 Nov. 25th Compal Reserved for PWR consumption measurement. Delete R63, R189, JOPEN2, JOPEN3 and JOPEN4. 0.2

25 30 AMP./Audio Jack Nov. 25th Compal Beep function fail Correct Beep circuit 0.2
A A

26 15 TV-OUT/LVDS/CRT Nov. 25th Compal Lack of this part in vendor side Change C907 from 0.1U_0402_25V4K to 0.1U_0805_50V. 0.2

Compal Electronics, Inc.


Title
SCHEMATIC, M/B LA-2642P
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
401380
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: 星期五, 七月 29, 2005 Sheet 43 of 48
5 4 3 2 1
5 4 3 2 1

Version Change List ( P. I. R. List ) Page 2/3


Request
Item Page# Title Date Owner Issue Description Solution Description Rev.
27 22 IDE/CD_ROM Conn. Nov. 30th NEC For safety Add F4" Fuse" for ODD 0.2

D 28 15 TV-OUT/LVDS/CRT Dec. 1st Compal CRT Function abnormal Change the D12 to correct library 0.2 D

29 23 USB/BlueTooth/FP Dec. 6th NEC For Safety. Add Poly-Fuse for B/T and F/P. 0.2

Remove serial Resistors, Capacitor and Transtor. Change to Buffer


30 30 AMP./Audio Jack Dec. 6th Compal Correct Buzzer drive circuit to separate the signals and improve the driveing capacity. 0.2

Change R27 from 47k to 100k and fine-tune pwr sequnse between
31 6 Pentium-M(1/3) Dec. 7th Compal Correct Thermal trip timing +1.5vs and VCCP. 0.2

32 Dec. 8th EMI PCI Clock will cause EMI issue. Add AC-termination 10-ohm and 22pf for PCI Clocks. 0.2

1. Follow Buzzer voltage range' 2V ~ 4V' requirement 1. Change the pull-up power to +3VS.
33 30 AMP./Audio Jack Dec. 8th Compal 0.2
2. Follow NEC Audio team test result for HP signals. 2. Change R1005 & R1006 from 0-ohm to 47-ohm

34 31 ENE-KB910L/TPM Dec. 8th Compal Correct Extension IO control signal. Change the control signal of U51A from KBA1 to KBA2 0.2

35 29 AC97 Codec AD1981B/MDC Dec. 8th EMI EAPD will cause EMI issue with 197MHz Change Resistor' R494' to Bead' L56' 0.2

36 23 USB/BlueTooth/FP Dec. 9th EMI USB EMI problem Add Common Choke for USB port 0.2
C C

37 22 IDE/CD_ROM Conn. Dec. 9th EMI Pin A24 ~ A26 will over 10dB for EMI Add bypass capacitors' 1000p. 0.2

38 15 TV-OUT/LVDS/CRT Dec. 10th EMI Reserved R to measure pwr consumption Delete R488. 0.2

39 22 IDE/CD_ROM Conn. Dec. 13th NEC For ODD Module Safety Correct the Fuse with 3A for ODD 0.2

40 31 ENE-KB910L/TPM Dec. 13th Compal For Power Play function Reserved NB_VCC_CNTL for Power Play circuit. 0.2

41 22 IDE/CD_ROM Conn. Dec. 13th Compal Correct cap power rating for B+_BIAS Change cap from 0.1u_0402_16V to 0.1u_0805_50V. 0.2
33 DC TO DC

42 18 P18-SB400-USB/AC97/MISC.(2/4) Dec. 13th Compal Prevent leakage currect for EC_SI# and EC_SCI# signals. Change these signals pull-up from +3V to +3VLAW. 0.2

43 32 BIOS/EE-Prom/TP/KB/SW Dec. 30th Compal Update the Battery mode power-on circuit. Un-pop. R422, R421, Q22, Q21, D33, D43, D44 and C598. 0.3

45 6 Pentium-M(1/3) Jan. 11th Compal Improve thermal trip timing. Change R32 from 75 to 10-ohm. 0.3
B B

Swap AUX_S5EN and TRICKE signal.


46 31 ENE-KB910L/TPM Jan. 11th Compal Correct Extension buffer function Move HDD_EN# from extension buffer, U50, to KB910L. 0.3
Move A/B#USE signal to KB910L and delted EC_THERM.

47 31 ENE-KB910L/TPM Jan. 12th Compal To save space and cost. Change U51 from SN74LVC32APWR TSSOP14 to NC7SZ32P5X_NL SC70-5. 0.3

48 30 AMP./Audio Jack Jan. 13th Compal To solve Int. Speaker GAIN issue. Change the POWER source of R360 & R359 from +5VAMP to +5VS. 0.3
+5VAMP is single Power plane.
Change the pull-up R, R1021, from D18.1 to D18.2.
49 24 MINI_PCI SLOT-WLAN Jan. 13th Compal Correct net name for WL_OFF# signal. 0.3
Correct the net name for WL_OFF# to prevent confuse.

50 32 BIOS/EE-Prom/TP/KB/SW Jan. 14th Compal Follow NEC DPD R02 for DIP SW function Remove USBSEL and CONFIG signals. 0.3

51 30 AMP./Audio Jack Jan. 14th NEC To improve Audio Dolby quality. Change the C997 & C998 to 2.2U. 0.3

08 CPU Decoupling/FAN(3/3) To save cost for CPU Decoupling Caps. Depopulated C29.
52 22 IDE/CD_ROM Conn. Jan. 18th POWER To Save Power consumption for Battery life. Change R480 & R481 from 100k to 470k. 0.3
33 DC TO DC To Save Power consumption for Battery life. Change R440 from 100K to 470K
27 R5C842-PCI/CARD BUS/OHCI For Sn-Zn-Bi process. Change Y5 from SJ124P5M500 to SJ124P5MF00 for Sn-Zn-Bi process.
53 Jan. 19th Compal 0.3
A A

54 23 USB/BlueTooth/FP Jan. 20th Compal Solve USB leackage voltage problem. Add Dis-charge circuit R46, R1, Q4 and Q12. 0.3

Compal Electronics, Inc.


Title
SCHEMATIC, M/B LA-2642P
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401380 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: 星期五, 七月 29, 2005 Sheet 44 of 48
5 4 3 2 1
5 4 3 2 1

Version Change List ( P. I. R. List ) Page 3/3


Request
Item Page# Title Date Owner Issue Description Solution Description Rev.
27 23 USB/BlueTooth/FP Jan. 21th Compal For EMI Add Common Chock to solve the issue. 0.3

D 28 30 AMP./Audio Jack Jan. 24th Vendor To prevent leakage from +AUD_VREF Float JP16 pin6. 0.3 D

30 12 RS400MD-PWR/GND(4/4) Jan. 26th Compal improve the +1.2VSA and +1.2VMCOORE be stability. Add C1020 & C172 to solve +1.2VSA and +1.2VMCORE voltage drop issue. 0.3

31 08 CPU Decoupling/FAN(3/3) Jan. 26th Compal To improve Battery Life when S4/S5 status. Add Q56' SB570020000' and R68' SD028100100,Change Q52 to SB934430000. 0.3

32 18 SB400-USB/AC97/MISC.(2/4) Jan. 26th ATI Work around for CKE# Glitch. Add D21 & D22 with SC1H751H000. 0.3

33 8 RS400MD-FSB/A-PCIE(1/4) Jan. 27th NEC Work around for CKE# Glitch. Change R52 Value to 27K. 0.3

34 17 SB400-PCIE/PCI/LPC/RTC(1/4) Feb. 16th ATI To solve SB400-A32 boot fail with PCIE I/F. Change C263, C264, C265 and C266 from 0.1uf to 0.01uf. 1.0

35 31 ENE-KB910L/TPM Feb. 23th Compal To by pass the ACIN to the EC Add R71 and change D20 & R386 to @. 0.4

36 17 SB400-PCIE/PCI/LPC/RTC(1/4) Feb. 23th Compal To improve Battery Life when S4/S5 status. Change power source of U8.pin14 and R149.1 from +3VALW to +3VS 0.4

37 21 Hardware Trap Feb. 23th Compal To improve Battery Life when S4/S5 status. Change power source of U31F.pin14 and U53.pin5 from +3VALW to +3VS 0.4

38 31 ENE-KB910L/TPM Feb. 23th Compal To improve Battery Life when S4/S5 status. Change power source of R1053 from +3V_EC to +3VS 0.4

39 32 BIOS/EE-Prom/TP/KB/SW Feb. 23th Compal To improve Battery Life when S4/S5 status. Change power source of RP6 from +3V_EC to +3VS 0.4
C C
40 9 RS400MD-FSB/A-PCIE(1/4) Feb. 24th ATI To improve LAN performance. Change LAN port from GPP0 to GPP2 0.4

41 18 SB400-USB/AC97/MISC.(2/4) Feb. 24th ATI To improve LAN performance(For BIOS). Add pull H & L to U7.A27(GPIO). 0.4

42 21 Hardware Trap Feb. 25th ATI Strap on PCICLK5 has beed redefined Pop R212 to pull low and unpop R199 0.4

43 18 SB400-USB/AC97/MISC.(2/4) Feb. 25th NEC To improve LAN performance(For BIOS). Add pull H & L to U7.D23(GPIO). 0.4

44 18 SB400-USB/AC97/MISC.(2/4) Mar. 8th NEC To improve LAN performance(For BIOS-IRT). Pop R160 & R167, unpop R159 & R168 0.5

45 8 RS400MD-FSB/A-PCIE(1/4) Mar. 8th Compal Solve Fan noise Deleted C911 0.5

46 21 Hardware Trap Mar. 8th ATI Strap on PCICLK5 has beed redefined Pop R199 to pull low and unpop R212 0.5

47 12 RS400MD-PWR/GND(4/4) Mar. 8th Compal For voltage stable Add C172 0.5

48 06 Pentium-M(1/3) Apr. 7th Compal To solve S3 shut-down issue. Add Diod D40, RB521S-30, to discharge Base voltage when shut-down. 2.0

49 22 IDE/CD_ROM Conn. Apr. 28th NEC To solve ODDLED abnormal light. Change the R236 power source from +5VODD to +5VS. 2.0

1 18 SB400-USB/AC97/MISC.(2/4) May. 5th NEC To improve LAN performance(For BIOS). Change pull H R159 0.1
B B

2 17 SB400-PCIE/PCI/LPC/RTC(1/4) May. 5th Compal Change PCI_CLK trace for EMI Change R141, 142, 143, 1011 size from 0603 to 0402 0.1

3 31 ENE-KB910L/TPM May. 5th Compal Add CLKRUN Reserve 1K resistance pull down 0.1

4 22 IDE/CD_ROM Conn. May. 5th Compal To solve ODDLED abnormal light. Change R236 from 100K to 8.2K 0.1

5 6 Pentium-M(1/3) Jun. 16th Compal To solve can't boot after high loading test.. Change R227 power source from VCCP to CPUCORE 0.2

6 18 SB400-USB/AC97/MISC.(2/4) Jun. 16th NEC To meet ATi spec(USB_RCOMP) Change R169 from 10K to 11.8K 0.2

7 27 R5C842-PCI/CARD BUS/OHCI Jul. 21th Compal RICOH recommand Change R452 from 0 to 10K 1.0
1.Change R51 from 10K_0402_5% to 10K_0402_1%
8 9 RS400MD-FSB/A-PCIE(1/4) Jul. 21th ATI ATI recommand 1.0
2.Change R53 from 100_0402_1% to 82.5_0402_1%
3.Change R54 from 8.2K_0402_1% to 8.25K_0402_1%
5.Change C130,C132,C134,C136,C138,C140,C142,C144,C146,C148,C150,C151,
C152,C153,C154,C156,C157,C158,C159
from 0.1U_0402_16V4Z to 1U_0402_6.3V4Z

A A

Title
Compal Electronics, Inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-2642P
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
401380
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: 星期五, 七月 29, 2005 Sheet 45 of 48
5 4 3 2 1
5 4 3 2 1

Version Change List ( P. I. R. List ) Page 1/2


Request
Item Page# Title Date Owner Issue Description Solution Description Rev.
1 42 Optional VGA MVCORE Power Dec. 07th Compal In order to use ATI's new power saving feature of Power Play, Add optional PC174, PC176, PC177, PC178, PC179, PC180, 0.2
the VGA chip core Voltage has to to adjusted down to 1.0V. PC181, PC184, PD34, PD35, PL15, PL16, PQ47, PQ48,
D
A new power regulator circuit is added using MAX1714 to have high efficiency PQ49, PR209, PR210, PR211, PR212, PR213, PR214, PR215, D
at light load to make this feature able to prolong battery life. PR216, PR217, PR218, PR219, PU18.
Add PC168 , PC169 to replace PC143 (deleted). Add PJP16, PJP17.

Added PC167 (1000P_0402_50V7K). 0.2


2 34 PWR DCIN / Precharge Dec. 07th Compal To prevent adaptor plug in or plug out glitches.

0.2
3 34 PWR DCIN / Precharge Dec. 07th Compal To adjust adaptor input precharge Voltage and Battery input precharge Change PR17 to 127K 1%, PR21 to 340K 1%, PC14 to 0.1uF.
Voltage thresholds.

4 36 Charger Dec. 07th Compal Change adaptor isolation MOSFET turn-on turn-off delay time Change PQ11 to DTC115EUA. Add PD31, PR214, PC170. 0.2
for proper multiple power source hot swap.

5 36 Charger Dec. 07th Compal To prevent power on single time short duration LED flashing Add in PR205, PR206, PR207, PC171, PD36, PQ45, PQ44. 0.2
by introducing delay in V_BIAS.

0.2
6 37 Battery Select Dec. 07th Compal To provide proper multiple power source hot swap (main and second battery), Added PD33, PD32, PC173, PC172, PQ46, PC208.
component values are changed and extra components are added for extra delay Change PC44, PC46 to 47pF. Change PR79, PR88 to 100K 5%.
to do "Break" before "Make" function.
C C

7 39 +1.2VSP & +1.8VALWP Dec. 07th Compal Correct wrong pin connection. Change PQ28 pin 4 and pin 1,2,3 connection. 0.2

8 40 0.9VSP/VCCPP Dec. 07th Compal Correct wrong pin connection. Swap PQ42 pin 1 and pin 3 connection. 0.2

9 41 CPU_CORE Dec. 07th Compal Correct CPU Vcore load line. Change PR159 and PR153 from 3K to 2K 1%. 0.2

10 34 PWR DCIN / Precharge Dec. 10th Compal Change to horizontal intertion type on-board adaptor connector jack. Change PJP1 to use "SINGA_2WA-8291T041". 0.2

Change to use lower height Inductor to fit into low height area
11 38 3.3V/5V Dec. 10th Compal (5.5A rating is still > 4A requirement). Change PL8 to use TOKO part: "4.7UH_D104C-919AS-47M_5A_20%". 0.2

12 35, 36, 37 CPU OTP Page, Charger Page, Dec. 13th Compal To save power in S4, change PU3, PU5, and PU7 power to be powered Change PU3, PU5, and PU7 pin 8 to VL net. Add PC210 to VL net
and Battery Select Page. from +5VL (not Vs). close to PU5 pin 8. 0.2

13 42 Optional VGA MVCORE Power Dec. 13th Compal To change Voltage control pin active polarity on ATI Power Play. Add PR230, PR231, PQ50, PC200, PD40, and PD41. uninstall PD41.
B 0.2 B
Delete PQ49, PR218, PR219.

14 38 3.3V/5V Dec. 14th Compal Add option ckt to let +3VALW always on when batteries are in bay. Add PR232, PR233, PR234. Uninstall PC148, PR105, pr233, and PU16.
Add option ckt to let +5VALW to be independantly controlled by ECON signal. 0.2

15 34 PWR DCIN / Precharge Dec. 14th Compal Add option ckt to let +3VALW always on when batteries are in bay. Add PR235. Delete PC8, PR12, PR14, and PQ1. 0.2

16 34 PWR DCIN / Precharge Dec. 14th Compal Change pre-charge time to be shorter by use smaller value. Change PR9, PR11, PR13 to 1K. 0.2

0.2
17 40 0.9VSP/VCCPP Dec. 14th Compal With option ckt to let +3VALW always on when batteries are in bay, Uninstall PC152, PR201, PQ43, PQ42, PR199, PC149, PC15, PU17, PC150.
old circuit components should be uninstalled. Add PJP20. Add PR236, but uninstall it.

18 39 +1.2VSP & +1.8VALWP Dec. 22th Compal Add delay circuit requested by HW to form SUSP_DLY# signal for Add PR220, PR222, PC185, PQ50.
1.2V and 1.0/1.2V regualtors enable control. 0.2

19 36 Charger Dec. 22th Compal Add control signal to prevent Voltage droop when adaptor is inserted. Add PD43. Change PR43=33K 5%, and unpopulate PR34.
A 0.3 A
Change resistor value to slow down in-rush current.

20 34 PWR DCIN / Precharge Dec. 22th Compal Add control signal to prevent Voltage droop problem when adaptor is inserted. Added PR249=4.7k. Changed PC13=1000pF, PC167 = 0.1uF. 0.3

Compal Electronics, Inc.


Title
SCHEMATIC, M/B LA-2642P
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401380
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: 星期五, 七月 29, 2005 Sheet 46 of 48
5 4 3 2 1
5 4 3 2 1

Version Change List ( P. I. R. List ) Page 2/2


Request
Item Page# Title Date Owner Issue Description Solution Description Rev.
21 34 PWR DCIN / Precharge Dec. 30th Compal To provide full protection in wrong adaptor over-Voltage or Deleted PR10 , and added in PR241, PR242, PR247, PQ57, PQ58, 0.3
Battery charger over-Voltage conditions, A switch is inserted into and PQ61.
D
Pre-charge path to stop pre-charge during over-Voltage. D

0.3
22 36 Charger Dec. 30th Compal To provide better protection for wrong adaptor over-Voltage, a threshold Added PQ59, PQ60, PR244, PR245, and PR246.
protection circuit is added on ACOFF# control signal and PQ5 control signal. Changed PR36, and PR38. Changed PU5A pin8 to "VIN" net.

To improve shutdown mode quiescent current, change CPU OVP Changed PH1 to 100K (TH11-4H104FT), PR30, 0R28, PR29, PR31, PR25, 0.3
23 35 CPU OTP Dec. 30th Compal circuit resistors to have higher value. and PR26 value to larger values to reduce shutdown mode current.
Changed PQ4 to RHU002N06 and PC18 to 1000pF.

24 39 +1.2VSP & +1.8VALWP Dec. 30th Compal To correct the polarity of control signal for 1.0V/1.2V regualtor for VGA. Deleted PR221, PQ51. Changed "SUSP_DLY" connection to PQ50 pin1. 0.3

25 36 Charger Jan. 04th Compal To save more power in S3, S4, S5 modes and increase switching speed Depopulated PR34, PR59, and PR61. 0.3
during power source hot swaping. Changed PR43, PR70, and PR71 to 2.2K.

26 41 CPU_CORE Jan. 13th Compal Changed back CPU load line resistor value. Change PR159 and PR153 from 2K to 3K 1%. 0.3
C C

27 40 0.9VSP/VCCPP Jan. 14th Compal De-populate paralleled polymer capacitor on 1.05V rail (H/W has one already). De-populate PC101. 0.3

28 42 Optional VGA MVCORE Power Jan. 20th Compal North Bridge Chip Core Voltage on the lower band change to higher band. Changed PR217 to 44.2K 1%. 0.3

29 34 PWR DCIN / Precharge Jan. 20th Compal To save S4 mode current, Change PU1 pin8 power to VL. Changed PR22=330K 1%, PR21=169K 1%, PR17=287K 1%, 0.3
PR16=820K 1%, PR15 to 47K 5%. PU1 pin6 to pin2. PU1 pin8 to VL,
Deleted PR24, and PC14.

30 39 +1.2VSP & +1.8VALWP Jan. 24th Compal Add remote sense resistors. Added PR250, PR251. 0.3

31 42 Optional VGA MVCORE Power Jan. 24th Compal Add remote sense resistors. Added PR252, PR253. 0.3

32 41 CPU_CORE Jan. 24th Compal To prevent in-phase operation due to un-predicted noise problems. Added/reserved PC211, PC212, but not install them. 0.3

33 38 3.3V/5V Jan. 24th Compal To reduce temperature rise on NB skin. Changed PL5, PL6 to use TOKO inductors. 0.3

B 34 34 PWR DCIN / Precharge Jan. 24th NEC Add fuse at input trace for each DC/DC circuit and charger ouput trace. Changed PF1 to 12A and add PF2 for charger output trace, PF3 0.3 B
for 3V/5V, PF4 for 1.2VSP/1.8VALWP/1.2VMVCOREP, PF5forCPU_CORE.
38 3.3V/5V
39 +1.2VSP & +1.8VALWP
41 CPU_CORE
36 Charger

35 36 Charger Jan. 28th NEC Add fuse at batery input trace. Del PF2 and add PF6 and PF7 at PBJ1 pin 1 and PBJ2 pin 1. 0.3

36 39 +1.2VSP & +1.8VALWP System hang up at running 3DMark, chang +1.2VSP and +1.2VMVCOREP De-populate PR251 and in series with PR250 to +1.2VS .
Jan. 28th Compal to remote sense. De-populate PR252 and in series with PR253 to +1.2VMVCORE . 0.3
42 Optional VGA MVCORE Power

Reserve PR256 to as a volatagr divider with PR4. 0.4


37 34 PWR DCIN / Precharge Fab. 24th Compal To reduce power consumption at S4 mode.

38 38 3.3V/5V Fab. 24th Compal To change +3VALWP and +5VALWP sequence, let +3VALWP turns on after +5VALWP. Add PR255 and PC213 to delay the turn on sequence of +3VALWP. 0.4

A A

Compal Electronics, Inc.


Title
SCHEMATIC, M/B LA-2642P
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
401380
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: 星期五, 七月 29, 2005 Sheet 47 of 48
5 4 3 2 1
5 4 3 2 1

Version Change List ( P. I. R. List ) Page 2/2


Request
Item Page# Title Date Owner Issue Description Solution Description Rev.
39 34 PWR DCIN / Precharge Mar. 8th Compal To change RTC battery charger current to meet RTC battery spec. Change PR19 and PR20 to 560 Ohm. 0.4

D D
40 34 PWR DCIN / Precharge
Mar. 8th Compal To change 1.2VMVCORE nomial voltage level and add output capacitor Populate PC169 with 4.7U and change PR217 to 49.9K Ohm. 0.4
to meet spec.
42 Optional VGA MVCORE Power

41 35 PWR CPU OTP Mar. 8th Compal To change OTP triggle point at 86 degree C for thermal team request. Change PR28 to 200K Ohm. 0.4

42 36 PWR-CHARGER Mar. 8th Compal To faster the CP protection. Change PC26 to 1500PF. 0.4

43 38 PWR-+1.2VSP & +1.8VALWP Mar. 8th Compal To decreace +1.2VSP OCP point. Change PR124 to 61.9K Ohm and PR125 to 39.2K Ohm. 0.4

44 42 Optional VGA MVCORE Power Mar. 8th Compal To increace +1.2VMVCORE OCP point. Change PR126 to 150K Ohm. 0.4

45 42 Optional VGA MVCORE Power Mar. 11th Compal To increace +1.2VMVCORE 1.2V and 1.0V switch design margine. Change PD40 to RB751V and PR231 to 100K Ohm. 0.4

46 38 3.3V/5V Mar. 16th Compal To change +3VALWP and +5VALWP sequence, let +3VALWP turns on after +5VALWP. Change PR255 to 15K Ohm and PC213 to 0.1u F. 0.5

47 34 PWR DCIN / Precharge Mar. 29th Compal To solve can't power on when remove the AC outlet without battery Change PR16 to 1M Ohm , PR21 to 162K Ohm ,PR22 to 287K Ohm , 0.5
C C
PC13 to 0.1UF , PC12 to 100PF and PD21 to SKUL30-02AT.

38 3.3V/5V

48 37 Battery Select Mar. 29th Compal To solve can't power on when discharge battery to shut down mode Change PR81 to 499K Ohm , PR90 to 499K Ohm and PQ22 to RHU002N06. 0.5

49 37 Battery Select Mar. 29th Compal To solve can't charge when discharge battery to shut down mode Change PR80 to 27K Ohm and PR89 to 27K Ohm. 0.5

50 41 CPU_CORE Apr. 28th Compal To reserve VR_ON control signal for +VCCPP and change CPU_CORE enable signal Add PR257 and change PR155 to PC214 2.0
pull down resistor to capacitor.
40 0.9VSP/VCCPP

51 38 3.3V/5V May. 10th Compal To solve no Power issue on Lavie and VersaPro MP status. Change PC68 and PC72 to 150U 6.3V 18mOhm UD type 2.0
and change PQ24 to SI481-DY-T1-E3

B B

A A

Compal Electronics, Inc.


Title
SCHEMATIC, M/B LA-2642P
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
401380
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: 星期五, 七月 29, 2005 Sheet 48 of 48
5 4 3 2 1

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