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Switching Theory
Switching Theory
CSET 4650
Field Programmable Logic Devices
Dan Solarek
Logic Families
Logic Family : A collection of different ICs that
have similar circuit characteristics
The circuit design of the basic gate of each logic
family is the same
The most important parameters for evaluating and
comparing logic families include :
Logic Levels
Power Dissipation
Propagation delay
Noise margin
Fan-out ( loading )
Moores Law
In 1965, Gordon Moore predicted that the number of
transistors that can be integrated on a die would
double every 18 to 14 months
i.e., grow exponentially with time
From Intels 4040 (2300 transistors) to Pentium II (7,500,000 transistors) and beyond
BJT
transistor types
MOSFET
(NMOS, PMOS)
TTL
CMOS
8
Electrical Characteristics
TTL
faster (some versions)
strong drive capability
rugged
CMOS
lower power consumption
simpler to make
greater packing density
better noise immunity
I OH
VOH
Ground
I IH
VIH
11
Inputs are
connected to Vcc
instead of
Ground
Ground
OL
I IL
V OL
V IL
12
Electrical Characteristics
logic 1
indeterminate
input voltage
logic 0
13
5.0V
Logic 1
Logic 1
3.5V
2.5V
Indeterminate
Indeterminate
0.8V
1.5V
Logic 0
Logic 0
0V
0V
TTL
CMOS
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Noise Margin
Manufacturers specify voltage limits to represent the logical
0 or 1.
These limits are not the same at the input and output sides.
For example, a particular Gate A may output a voltage of 4.8V when it
is supposed to output a HIGH but, at its input side, it can take a
voltage of 3V as HIGH.
15
Noise Margin
If noise in the circuit is high enough
it can push a logic 0 up or drop a
logic 1 down into the indeterminate
or illegal region
The magnitude of the voltage
required to reach this level is the
noise margin
Noise margin for logic high is:
NMH = VOHmin VIHmin
logic 1
VOHmin
VIHmin
indeterminate
input voltage
logic 0
VILmax
VOLmax
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Noise Margin
Difference between the worst case output voltage of
one stage and worst case input voltage of next stage
Greater the difference, the more unwanted signal that
can be added without causing incorrect gate
operation
NMhigh = VOHmin - VIHmin
Worked Example
Given the following parameters, calculate the
noise margin of 74LS series.
Parameter
VIH(min)
VIL(max)
VOH(min)
VOL(max)
74LS
2V
0.8V
2.7V
0.4V
Solution:
High Level Noise Margin, VNH = VOH (min) - VIH (min)=2.7V-2.0V=0.7V
Low Level Noise Margin, VNL = VIL (max) - VOL (max)=0.8V-0.4V=0.4V
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Logic 1
VNH
VIH (min)
VIL (max)
VNL
VOL (max)
Logic 0
Output Voltage Ranges
Logic 0
Input Voltage Ranges
19
20
Fall Time
Time from 90% to 10% of signal, High to Low
rise time
10%
fall time
90%
90%
10%
21
50%
0
Output
0
tPHL
tPLH
22
Power Dissipation
Static
I2R losses due to passive components, no input signal
Dynamic
I2R losses due to charging and discharging capacitances
through resistances, due to input signal
23
Speed-Power Product
Speed (propagation delay) and power consumption
are the two most important performance parameters
of a digital IC.
A simple means for measuring and comparing the
overall performance of an IC family is the speedpower product (the smaller, the better).
For example, an IC has
an average propagation delay of 10 ns
an average power dissipation of 5 mW
the speed-power product = (10 ns) x (5 mW)
= 50 picoJoules (pJ)
24
26
5V 0.5 V
VIH = 2V
VIL = 0.8V
Electrical Characteristics
output voltage
(worst case)
max input currents
propagation delay
noise margins
Fan-out
5 Volt
Input
Range
for 1
VOH = 2.7V
VOL = 0.5V
IIH = 20A
IIL = -0.4mA
tpd = 15 nS
for a logic 0 = 0.3V
for a logic 1 = 0.7V
20 TTL loads
Output
Range
for 1
2.7
2.0
Input
Range
for 0
0.8
0.5
0 Volt
Output
Range
for 0
27
Fan-In
Number of input signals to a gate
Not an electrical property
Function of the manufacturing process
28
Fan-Out
A measure of the ability of the output of one gate to
drive the input(s) of subsequent gates
Usually specified as standard loads within a single
family
e.g., an input to an inverter in the same family
29
Low
IIH
Fan-Out
An illustration of fan-out and the associated source
and sink currents
31
Worked Example
How many 74LS00 NAND gate inputs can be driven
by a 74LS00 NAND gate outputs ?
Solution:
Refer to data sheet of 74LS00, the maximum values of
IOH = 0.4mA, IOL = 8mA, IIH = 20uA, and IIL = 0.4mA
Hence,
fan-out(high) = IOH(max) / IIH (max)=0.4mA/20uA=20
fan-out(low) = IOL(max) / IIL(max)=8mA/0.4mA=20,
the overall fan-out = fan-out(high) or fan-out(low) whichever is lower.
Hence, overall fan-out = 20
32
33
Wired-AND
Open collector outputs connected together to a common pullup resistor
Any collector can pull the signal line low
Logically an AND gate
34
Tri-State Logic
Both output transistors of totem-pole output are turned off
Usually used to bus multiple signals on the same wire
Gates not enabled present high-Z to bus and therefore do
not interfere with other gates putting signals on the bus
35
Tri-State Logic
Tri-state logic includes a switch at the output
In the figure below, the three states are illustrated:
a) Logic High output
b) Logic Low output
c) High impedance (Hi-Z) output
36
Acronym
Description
No Gates
Example
SSI
Small-scale integration
<12
4 NAND gates
MSI
Medium-scale integration
12 100
Adder
LSI
Large-scale integration
100 1000
6800
VLSI
1000 1M
68000
ULSI
80486/80586
37
SSI Devices
Each package contains a code identifying the package
N74LS00
Manufacturers Code
N = National Semiconductors
SN = Signetics
Specification
Family
L
LS
H
Member
00 = Quad 2 input NAND
02 = Quad 2 input Nor
04 = Hex Invertors
20 = Dual 4 Input NAND
38
40
42
43
44
2003
1960
45
Products considered to be
mature are about 2 decades
into their life cycle
High-volume production
Multiple suppliers
Low prices
46
47
1.6K
R2
130
R3
Q
Q2
A
B
D
D3
Y O/P
Q
1
D2
I CQ1
ICQ1
Q1
Q2
Q3
Q4
Y O/P
ON
OFF
OFF
ON
ON
OFF
OFF
ON
ON
OFF
OFF
ON
OFF
ON
ON
OFF
1K
R4
48
49
Q1
D
O/P
I/P
Q1
Q2
O/P
ON
OFF
OFF
ON
I/P
Q2
S
50
Metal-gate CMOS
TTL-compatible CMOS
High speed CMOS
Advanced CMOS -TTL compatible
51
52
vi
53
54
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