Importance of ADCs and Design

Introduction & Importance of ADCs

 Analog-to-Digital Converters (ADCs) play an important
role in ever-increasing Digital world.

 The advancements seen in Digital world continuously

pose challenges to improve and develop new ADC
architectures.

 High-end applications like Mobile systems, Image

recognition, Digital receivers, Cellular base stations and
Fast Ethernet require ADCs for processing natural
signals in digital domain.
 Pipeline ADCs
• The Low Power and High resolution ADCs can be
achieved by Pipelined architecture designed for high
sampling rates.

• This Pipelined architecture offers Power and Speed

advantages over Flash or Multistep approaches due
to concurrent processing of the analog signal.
General Block diagram of Pipeline ADC
architecture

Fig. Pipeline ADC architecture

• The pipelined architecture is known to be well suitable
choice for achieving good dynamic performances and
throughput as the underlying flash ADCs.

• The primary focus of this work is to investigate the

various design techniques required to implement
pipeline ADCs for Digital Video Broadcasting-
Handheld(DVB-H) applications.
 PROBLEM CHARACTERIZATION

• Digital Video Broadcasting (DVB) is classified into 3

transmission specifications : DVB-S (S for satellite), DVB-C
(C for cable) and DVB-T (terrestrial).

• DVB-H is an extension of DVB-T with advanced

algorithms to facilitate signal reception at very high
speeds, with less silicon implementation overhead and
low power consumption.
BLOCK DIAGRAM OF DVB-H RECEIVER SUBSYSTEM
• In DVB-H, the information is transmitted as IP datagrams
at defined time-slots

• The signals used in DVB-H are COFDM modulated and can

be used over 6, 7 and 8 MHz channel bandwidths

• The principal challenge in the design of DVB-H, DVB-T

receiver subsystems is minimization of the power
consumption of ADC
 System Level Specifications

Resolution 10 bit

Speed 50 MS/s

Power <30 mW

DNL <.4 LSB

INL <.5 LSB

SNDR > 60 dB
 Pipeline ADC Architecture

• The proposed architecture is a 10-bit, 50 MS/s, 3-stage

pipeline ADC designed in 0.18um CMOS process
technology using Cadence tool.

• Each stage of the pipeline ADC consists of a Sample

and hold, 4-bit Flash ADC, 4-bit DAC and an amplifier to
provide the gain.
Block Diagram of proposed Pipeline ADC
Architecture
 Design Implementation
• The two major building blocks of this 3-stage pipeline ADC
are comparator(sub-ADC) and Operational Tran
conductance Amplifier(OTA).

• The sub-ADC is used to convert the incoming analog signal

to low resolution digital signal.

• An amplifier is used to provide the gain required for

subsequent stages of pipeline ADC.
 Comparator (sub-ADC)

• Comparator can be considered as a 1-bit analog to digital

converter and it is characterized based upon the low
offset voltage, less power dissipation and low delay

• Pre-amplifier based comparator has less offset voltage

and so it is mostly used for high resolution flash ADCs(n>3)
 Pre-amplifier based comparator

• There are three stages in a pre-amplifier based

comparator: pre-amplification, decision circuit and
output buffer.

• The decision circuit is heart of the comparator and can

discriminate mV level signals whereas output buffer
converts the decision circuit output into a logic signal.
Circuit Diagram

Fig. Comparator circuit diagram

 Design Analysis
tp=2nsec; Vsph=0v; CL=0.1pf(assumption)
tp = CL

ID1 = ID2 = ISS/2

Vsph = = (v+ - v-) for βΒ > βA

Here βΒ = βA and gm1= gm2

gm = √(2K(W/L)Id)

where βΒ = Kn(W/L)7 = Kn(W/L)10

Vin =
 Continued..
βA = Kn(W/L)8 = Kn(W/L)9

Here βA = βΒ

(W/L)7 = (W/L)10 = (W/L)8 = (W/L)9

∆vin =

Av = gm1/gm3 = gm2/gm4