Chapter 4

Combinational Logic

 原編者 : 嚴茂旭 副教授

 修改 : 盧晃瑩

Combinational Logic 4-1

4.1 Introduction

• Logic circuits for digital systems may be :

＊ combinational
＊ sequential

• Sequential circuits contain

» memory elements
» the outputs are a function of the current inputs and the st
ate of the memory elements

Combinational Logic 4-2

4.2 Combinational Circuits
• A combinational circuits
– 2n possible combinations of input values

– Specific functions
» Adders, subtractors, c omparators, decoders, encoders, and multiplex
ers
Combinational Logic 4 - 3
4-3 Analysis Procedure

• A combinational circuit

– make sure that it is combinational not sequential

» No feedback path
» No memory elements

– derive its Boolean functions (truth table)

– design verification

Combinational Logic 4-4

4-3 Analysis Procedure
￭ Truth table
F2 = AB+AC+BC

T1 = A+B+C

T2 = ABC

T3 = F2’T1

F1 = T3+T2

Combinational Logic 4-5

4-4 Design Procedure

• The design procedure of combinational circuits

– State the problem (system spec.)

» determine the inputs and outputs
» the input and output variables are assigned symbols
– derive the truth table
– derive the simplified Boolean functions
– draw the logic diagram and verify the correctness

Combinational Logic 4-6

4-4 Design Procedure (cont’s)
Example:
• BCD to excess-3 code BCD to W, X, Y, Z
A, B, C, D
0000 Excess-3
~
Sol: 1001

Combinational Logic 4-7

4-4 Design Procedure (cont’s)
Sol:

Combinational Logic 4-8

 4-4 Design Procedure (cont’s)
• Sol: The maps (cont’s)

Combinational Logic 4-9

4-4 Design Procedure (cont’s)
Sol: The maps (cont’s)
• The simplified functions
– z = D’ y = CD +C’D’
x = B’C + B’D+BC’D’ w = A+
BC+BD

• Another implementation
– z = D’ y = CD +C’D’ = CD +
(C+D)’ x = B’C + B’D+BC’D’ = B’(C+
D) +B(C+D)’ w = A+BC+BD

Combinational Logic 4 - 10
• Sol:  The logic diagram
z = D’
y = CD +C’D’ = CD + (C+D)’
x = B’C + B’D+BC’D’ = B’(C+D) +B(C+D)’
w = A+BC+BD

Combinational Logic 4 - 11
4-5 Binary Adder-Subtractor
1 1

1 0 1 (5)
+ 1 1 1 (7) .
1 1 0 0 (12)
FAFAHA
• HA: Half adder (add 2 bits) FA: Full adder (add 3 bits)

• Half adder (add 2 bits)

– 0 + 0 = 0 ; 0 + 1 = 1 ; 1 + 0 = 1 ; 1 + 1 = 10
– two input variables: x, y
– two output variables: C (carry), S (sum)
– truth table

Combinational Logic 4 - 12
4-5 Binary Adder-Subtractor (cont’s)

– S = x’y + xy’ C = xy

– the flexibility for implementation

– S = (x + y)(x’ + y’)

– S’ = xy + x’y’ S = (C + x’y’)’

– C = xy = (x’ + y’)’

Combinational Logic 4 - 13
4-5 Binary Adder-Subtractor (cont’s)

Combinational Logic 4 - 14
4-5 Binary Adder-Subtractor (cont’s)
• Full-Adder
– The arithmetic sum of 3 input bits

– 3 input bits
» x, y : two significant bits
» z : the carry bit from the previous lower significant bit

– Two output bits: C, S

Combinational Logic 4 - 15
4-5 Binary Adder-Subtractor (cont’s)

Combinational Logic 4 - 16
4-5 Binary Adder-Subtractor (cont’s)

Combinational Logic 4 - 17
4-5 Binary Adder-Subtractor (cont’s)
– S = x’y’z + x’yz’ + xy’z’ + xyz
= z Å (x Å y)
– C = xy + xz + yz
– C = x’yz + xy’z + xy
= z(xy’ + x’y) + xy = z(x Å y) + xy

Combinational Logic 4 - 18
4-5 Binary Adder-Subtractor (cont’s)
• 4 bit Binary adder

Combinational Logic 4 - 19
 C3 B3 A3 C2 B2 A2 C1 B1 A1 C0 B0 A0

C 4 S3 C3 S2 C2 S 1 C1 S0

Combinational Logic 4 - 20
4-5 Binary Adder-Subtractor (cont’s)
Delay in combinatinal logic circuits

Combinational Logic 4 - 21
4-5 Binary Adder-Subtractor (cont’s)
• Carry propagation
– when the correct outputs are available
– the critical path counts (the worst case)
– (A1, B1, C1) > C2 > C3 > C4 > (C5, S4)
– > 8 gate levels

Combinational Logic 4 - 22
4-5 Binary Adder-Subtractor (cont’s)
Carry look-ahead
• Reduce the carry propagation delay
– employ faster gates
– carry look-ahead (more complex mechanism, yet faster)
– carry propagate: Pi = Ai Å Bi
– carry generate: Gi = AiBi
– sum: Si = Pi Å Ci
– carry: Ci+1 = Gi + PiCi
– C1 = G0 + P0C0
– C2 = G1 + P1C1 = G1 + P1(G0 + P0C0) = G1 + P1G0 +
P1 P0 C 0
– C3 = G2 + P2C2 = G2 + P2G1 + P2P1G0 + P2P1P0C0

Combinational Logic 4 - 23
4-5 Binary Adder-Subtractor (cont’s)
– Logic diagram

Combinational Logic 4 - 24 24
• 4-bit carry-look ahead adder
– Reduce propagation delay

Combinational Logic 4 - 25
4-5 Binary Adder-Subtractor (cont’s)
Binary subtractor
• A-B = A+(2’s complement of B)
• 4-bit Adder-subtractor B Å0=B
– M=0, A+B; M=1, A+B’+1 B Å1=B’

Combinational Logic 4 - 26
4-5 Binary Adder-Subtractor (cont’s)
• Overflow
– The storage is limited
– Add two positive numbers and obtain a negative number
– Add two negative numbers and obtain a positive number
– V =Ci+1 Å Ci (for the addition of two signed binary numbers)
– V = 0, no overflow; V = 1, overflow

Example:
Storage: 8 BITS, +127 ~ -128
S = A + B,
A = +7010 = 0100_01102 B = +8010 = 0101_00002
A = -7010 = 1011_10102 B = -8010 = 1011_00002

Combinational Logic 4 - 27
4-6 Decimal Adder

• Add two BCD's

– 9 inputs: two BCD's and one carry-in
– 5 outputs: one BCD and one carry-out

• Design approaches
– A truth table with 29 entries, O.K. ?
– Use binary full Adders
» binary to BCD

Combinational Logic 4 - 28
4-6 Decimal Adder (cont’s)
• BCD Adder: The truth table

Combinational Logic 4 - 29
4-6 Decimal Adder (cont’s)
Modification: (10)d or +6

• C = K +Fsum>9(w, x, y, z)

• Fsum>9(Z8, Z4, Z2, Z1)

= S(10, 11, 12, 13, 14, 15)
= Z8Z4 + Z8Z2

C = K +Z8Z4 + Z8Z2

Combinational Logic 4 - 30
4-6 Decimal Adder (cont’s)
• Block diagram

Combinational Logic 4 - 31
4.7 Binary Multiplier
• Partial products
– AND operations

Combinational Logic 4 - 32
4.7 Binary Multiplier

￭ 4-bit ╳ 3-bit binary multiplier

B 3B2 B1B 0
X A2A1A0 .
P 3 P2 P1 P 0
P3P2P1P0
Q 3Q2 Q1Q 0
R3R2R1R0 .
C6C 5C 4C 3C2 C1 C0

Combinational Logic 4 - 33
4-8 Magnitude Comparator

• The comparison of two numbers

– outputs: A>B, A=B, A<B

– Design Approaches
» the truth table  too cumbersome for large n

– use inherent regularity of the problem

» reduce design efforts
» reduce human errors

Combinational Logic 4 - 34
4-8 Magnitude Comparator

• Algorithm -> logic

– A = A3A2A1A0 ; B = B3B2B1B0

– A=B if A3=B3, A2=B2, A1=B1and A1=B1

» equality: xi= AiBi + Ai’Bi’, for i = 0, 1, 2, 3
» (A=B) = x3x2x1x0

– (A>B) = A3B3’ + x3A2B2’ + x3x2A1B1’ + x3x2x1 A0B0’

– (A<B) = A3’B3 + x3A2’B2 + x3x2A1’B1 + x3x2x1 A0’B0

• Implementation
– xi = (AiBi’ + Ai’Bi)’
Combinational Logic 4 - 35
4-8 Magnitude Comparator (cont’s)

Combinational Logic 4 - 36
4-9 Decoders
• A n-to-m decoder
– n input variables; up to 2n output lines
– only one output can be active (high) at any time

Combinational Logic 4 - 37
4-9 Decoders (cont’s)
• An implementation

Combinational Logic 4 - 38
4-9 Decoders (cont’s)
– a decoder with an enable input  demultiplexor
– receive information on a single line and transmits it on one of 2n
possible output lines

Combinational Logic 4 - 39
4-9 Decoders (cont’s)
4-to-16 decoder
two 3-to-8 decoder  one 4-to-16 deocder

Combinational Logic 4 - 40
4-9 Decoders (cont’s)
Ex: 3-to-8 decoders 

5-to-32 decoder

Combinational Logic 4 - 41
 4-9 Decoders (cont’s)
Ex: 2-to-4 decoders 

4-to-16 decoder
Sometimes, an extra decoder is used to
enable other decoders

Combinational Logic 4 - 42
4-9 Decoders (cont’s)
Combination Logic Implementation
– each output = a minterm
– use a decoder and an external OR gate to implement any Boole
an function of n input variables
– A full-adder: (using a decoder to implement)
» S(x, y, z) = S(1, 2, 4, 7) S(3,
In general, C(x, y, z)a=practical
it is not
5, 6, 7) implementation

Combinational Logic 4 - 43
4-10 Encoders
• The inverse function of a decoder

z  D1  D3  D5  D7 The encoder can

be implemented
y  D2  D3  D6  D7 with three OR
gates. 44
 D4  D
x Logic
Combinational 4 5- 
44D6  D7
4-10 Encoders (cont’s)
Priority Encoder
– only one of the input is encoded

Inputs Outputs
D0 D1 D2 D3 x y V
0 0 0 0 X X 0
1 0 0 0 0 0 1
X 1 0 0 0 1 1
X X 1 0 1 0 1
X X X 1 1 1 1

– D3 has the highest priority

– D0 has the lowest priority
– X: don't-care conditions
– V: valid output indicator
Combinational Logic 4 - 45
 Inputs Outputs
■ The maps for simplifying D0 D1 D2 D3 x y V
outputs x and y 0 0 0 0 X X 0
1 0 0 0 0 0 1
X 1 0 0 0 1 1
X X 1 0 1 0 1
X X X 1 1 1 1

Combinational Logic 4 - 46
4-10 Encoders (cont’s)
■ Implementation of priority

x  D2  D3
y  D3  D1D2
V  D0  D1  D2  D3

Combinational Logic 4 - 47
4-11 Multiplexers
– select binary information from one of many input lin
es and direct it to a single output line

– 2n input lines, n selection lines and one output line

Combinational Logic 4 - 48
4-11 Multiplexers (cont’s)
– 4-to-1-line multiplexer

Combinational Logic 4 - 49
 4-11 Multiplexers (cont’s)
• Combination of multiplexer circuits
– n-to- 2n decoder
– add the 2n input lines to each AND gate
– OR(all AND gates)
– an enable input (an option)

Combinational Logic 4 - 50
4-11 Multiplexers (cont’s)
Boolean function implementation

– a better solution: implement any Boolean function of n+1 input vari

able
» n of these variables: the selection lines
» the remaining variable: the inputs

Combinational Logic 4 - 51
4-11 Multiplexers (cont’s)
Ex: 使用一個 4 對 1 多工器執行 F(x, y, z) = (0,2,3,5,7),
P.322

Combinational Logic 4 - 52
4-11 Multiplexers (cont’s)
Example: F(x, y, z) = (1, 2, 6, 7)

Combinational Logic 4 - 53
4-11 Multiplexers (cont’s)
Ex: P.365

Sol:

Combinational Logic 4 - 54
4-11 Multiplexers (cont’s)
Example: F(A, B, C, D) = (1, 3, 4, 11, 12, 13, 14, 15)

Combinational Logic 4 - 55
4-11 Multiplexers (cont’s)
Ex:

P.365
Sol:

Combinational Logic 4 - 56
4-11 Multiplexers (cont’s)
Ex:

P.365
Sol:

Combinational Logic 4 - 57
4-11 Multiplexers (cont’s)
Three-state gates:
– A multiplexer can be constructed with three-state gates
– Output state: 0, 1, and high-impedance (open ckts)

Combinational Logic 4 - 58
4-11 Multiplexers (cont’s)
Example: 4-to-1 line multiplexer

Combinational Logic 4 - 59