Engineering Science:

Sequential logic
Author: David Martínez Antón
Contact
Email: david.martinez@uneatlantico.es
 Sequential logic: introduction
Sequential logic can be described as a type of logic circuits whose outputs depends not only on the
present values of its inputs signals but also on the sequence of past outputs. This is in contrast to
combinational logic, whose outputs depends only on the present inputs. This means that sequential
logic has state (memory) while combinational does not:
Basic sequential
Basic combinational logic scheme
logic scheme
 S-R and R-S Latches:
Latches are a temporal storage device of two states that can remain in any of their two states thanks
to their “feedback”, due to the fact that each of their outputs are connected to their inputs. Flip-
flops and latches can be considered as the building blocks of computer memory.
SR and RS latches, can be thought of a “1 bit memory”. The circuits remember the state until it is
triggered by another input pulse or until the power is removed, this is why this type of circuits are
known as a bistable latch. In order to understand this type of devices we must first remember the
behavior of an or gate and an and gate and their truth tables:

Or gate truth And gate truth

table table
To consider:
A B Output A B Output
R-S stands for
0 0 0 0 0 0 “Reset-Set”
0 1 1 0 1 0
1 0 1 1 0 0
1 1 1 1 1 1
 S-R and R-S Latches (II):
If we add a negated logic gate to each of these two, we can swap the “0” in the output into ones
and vice versa. Remember that these combination of logic gates already exist, they have their own
name and their own truth table: NOR and NAND gates.

NOR gate truth NAND gate

table truth table
A B Output A B Output
0 0 1 0 0 1
0 1 0 0 1 1
1 0 0 1 0 1
1 1 0 1 1 0

To consider: the S-R and R-S latches

can be build using either NOR or
NAND gates
 R-S latch: how it works
An R-S latch can be built out of NOR gates. The output of each NOR gated is connected in such a
way that it is also the input of the other, which results in a positive feedback. The R-S latch has two
inputs, “R” and “S” and the output “Q”. The Output “” is going to be the opposite of the output “Q”.
The starting state here is that “R” and “S” are “0”, and “Q” is “1” so “” is “0”:
Starting state:
NOR gate truth
table
A B Output
0 0 1
0 1 0
1
1 0 0
1 1 0

To consider: because “Q”

Let’s consider an “starting is “1”, the latch is currently
state” like this one: “S” and “R” storing “1”
“0” and “Q” being “1”
 R-S latch: how it works (II), resetting the
latch
Now let’s consider that we apply a pulse to “R”. Since in the truth table of a “NOR” gate, the input
“1” implies that the output is going to forcibly be “0”. This “0” is feed back into the lower gate,
resulting in a “1” output for “”. The output of “” is feed back into the upper gate, but it does not
change the output, it is still “0”. The pulse that was applied to reset the “R-S latch” is now removed,
but the output of the top “NOR” gate remains the same, with the value “0”, but the output “Q” is
now “0” so the latch is now storing a “0”:

NOR gate truth

table
A B Output 2 3
0 0 1
0 1 0
1 0 0
1 1 0
 R-S latch: how it works (III), setting the latch
In order to set the output “Q” to the value “1” again, we must apply a pulse to the “S” input. Pay
attention at how the changes are propagated through the entire circuit. Remember that an input
“1” in a R-S latch built from “NOR” gates, is going to force the corresponding output to be a “0”. The
set pulse is now removed and as we can see the circuit is now latched into a set state, storing a “1”
again in the output “Q”:

Remember: “S” stands

for “Set” and “R” for
reset
4 5

To consider: to better understand

these propagations, check the
truth table of the “NOR” gate
 R-S latch: how it works (IV)
Notice that if another “Set” pulse is applied, it has no effect on the circuit, the outputs remain the
same. Applying a set pulse for “S” will always force the latch into a “set state” regardless of the
previous state of the latch. Similarly, applying a pulse for “R” will always force the latch into a “reset
state”. Notice that “R” and “S” are never left high at the same time. The latch is controlled by
pulses only. Then we have the following truth table: when both “S” and “R” are set to “0”, the
outputs may be “1” or may be “0”, depending on the previous state of the circuit. The “reset” pulse
is applied

7 8
6
 R-S latch: how it works (V)
Now the “Reset” pulse is removed, the latch is currently storing a “0” for “Q”, both “R” and “S” are
“0” again, and output “Q” remains in “0” and its inverse “” is “1”. A set pulse is applied, “S” is “1”
and “R” is “0”, the output “Q” becomes “1” and “” becomes “0”.

10
9 11
 R-S latch: how it works (VI), forbidden state
The set pulse is removed, “Q” is “1” and “” is “0”. The only circumstance that have not been
considered is when both inputs “R” and “S” are set to “1” at the same time. If this will to occur, we
will be telling the latch to set the value “1” and “0” simultaneously, but in reality “Q” will become
“0” and “” will also become “0”. This will sort itself out if one of the inputs fell to “0” before the
other, for example, if “R” fell to “0” first with “S” still “1” then “Q” will become “1”again. If however,
both inputs are at “1” and both fell to “0” at the same time, we have what it is known as a race
condition between the two gates, since they will be racing each other to feed back their new
output, being impossible to know which one will “win”.

Forbidden state for R-S latch

To consider:
S R Q if both inputs
0 1 are high, the
0 0 next state can’t be
1 0
determined. This
0 1 0 1
is a state that the
1 0 1 0 latch should never
1 1 0 0 be in
 R-S latch: how it works (VII) summary
To consider: so this type of R-S latch is known as an “active-high SR latch”, because the normal condition
for inputs “S” and “R” is low, and a high pulse at one of these inputs is required to change the
state of the latch:
NOR gate truth
“Active-high” SR latch table
S R Q
0 1 A B Output
0 0
1 0 0 0 1
0 1 0 1 0 1 0
1 0 1 0 1 0 0
1 1 0 0 1 1 0

Remember:
S=1 and R=1 To consider:
is the invalid state • Normal condition
for an R-S latch • Forbidden state
 S-R latch: how it works
The wiring of an S-R latch is the same as the R-S latch, but now it is build out of “NAND” gates and
the “S” input is located at the top while the “R” is at the bottom. Notice that the output truth table
now is different from the one in the “R-S latch”. In this type (“S-R latch”), “S” and “R” are kept high
most of the time.
NAND gate
“Active-low” SR latch truth table
A B Output S R Q

0 0 1 0 0 1 1

0 1 1 0 1 1 0

1 0 1 1 0 0 1
1 1 0 0 1
1 1
1 0

To consider: To consider: now the “prohibited

• Normal condition state” for this type of latch
• Forbidden state is when both inputs “S” and “R”
are 0
 S-R latch: how it works (II) setting the latch
Let’s consider a starting state where both inputs “S” and “R” are “1” and output “Q” is “0”. Now
when input “S” is made low momentarily, in other words, when it becomes “0”, the output “Q” is
forcibly going to be “1” (check the “NAND” gate truth table if you have doubts), so the latch is now
storing a “1” since the output “Q” is now storing a “1”. “S” now returns to its normal high state “1”
and the output “Q” and “” and the input “R” remain with the same value:
Starting state:

3
1 2
 S-R latch: how it works (III) resetting the
latch
When “R” is set low momentarily, the output “” is forcibly going to be a “1”, this is feed back into
the inputs of the top “NAND” gate, being the output “Q” “0”. “R” can then return to its normal high
value and the latch is now storing a “0” again

To consider: an “S-R latch”

built from “NAND” gates is
4 5 more explicitly known as
“active-low S-R latch”
 S-R latch: how it works (IV) forbidden state
An “S-R latch” also has a forbidden state, it occurs when both “S” and “R” are simultaneously “0”,
which will result in an illegal state in which both “Q” and its complement “” are “1”

To consider: Forbidden state for S-R latch

S-R and R-S latches are said
to be level-sensitive, which
means that it will respond S R Q
to a valid change in either 0 0 1 1
“S” or “R”, regardless of the
0 1 1 0
duration of the input pulse.
It is the level, high or low 1 0 0 1
that matters, not how long 0 1
it is applied for 1 1
1 0
 S-R latches: application, “switch-bounce
suppression”
When a mechanical switch is pressed, it may generate several electrical signals in a fraction of a
second, when only one signal is required. This effect is known as “switch-bounce” These produce
some signal voltage peaks that may be unacceptable on a digital system. An S-R latch can be used
to suppress this effect then. It can be used to allow a clean interfacing between for example a
mechanical switch and the digital circuit that is controlling:

2
1 To consider: then the S-R
latch will ignore any
further set signals after it
has already been set
To consider: when the switch connects
input “S” to earth, it will make it low
3
thereby changing the output “Q” of the
S-R latch from low to high
 S-R latch: chronogram exercise
Provided the following “time-chart” (chronogram), find the corresponding square wave of the
output “Q”. Consider the starting state of “Q” as “0”:

Q
 S-R latch: chronogram exercise solution
S-R latch circuit scheme

Since it is an “S-R latch”, it

is going to be build out of
NAND gate “NAND” gates
truth table
A B Output
0 0 1
0 1 1 S
1 0 1
1 1 0
R

Q
Gated R-S latch: introduction and application
A gated set-reset latch is an SR latch that can only change state while it is enabled. Application: an
application of the “gated SR latch” could be for example used in an air conditioning system in a
building, each room could have its own cooling unit controlled independently by its own SR latch,
coming from a temperature sensor the “Set” and “Reset” signals, or a humidity sensor in the room.
Since these are gated SR latches, a control panel could be used to enable or disable the switching
“on” and “off” of these units on a room-by-room basis:
To consider: the input
Abstraction symbol Gated R-S latch “E” can be used to enable
of a “gated S-R latch” or disable the latching
effect.

Remember: an “AND” gate

will only have a high output
if both inputs are high
 Gated S-R latch: introduction
By connecting an extra para of NAND gates to the circuit, we have created a third input “E”, and
now we have a new circuit in which the normal states of “S” and “R” are “0”, and high pulses are
required to set or reset the latch.

To consider: then our “NAND-based-latch”

has been changed from an “active-low-latch”
into an “active-high-latch”.
These additional gates on a basic SR latch
are sometimes referred to as “steering gates”

To consider: we are going to use a chronogram to show

the changes in inputs or outputs on a chart showing
changes in voltage against time. Remember that
everything occurs very quickly in an digital circuits (time
intervals in this chart have a duration of micro-second).
Low voltage (0 volts) represents binary value “0”, and
high voltage (5 volts) represents binary value “1”
 Gated S-R latch: chronogram examples
We are going to use a chronogram to describe the behavior of the latch. Remember that we are
going to used a “gated S-R latch”, which is fully build out of “NAND” gates
NAND gate
truth table

To consider: for the following A B Output

exercises, it does not take any time 0 0 1
from voltage to change from low
0 1 1
to high or for high to low. In reality
this transitions takes a few 1 0 1
nanoseconds. But for these examples, 1 1 0
we are going to consider that changing
from high to low and vice-versa is
instantaneous, which produces
a classic square wave
 Gated S-R latch: chronogram example (II)
The starting state for the output “Q” as we can check is low, being “S” and “R” both low but “E” is
high, so the latch is enabled. Actually, in this diagram, the latch is always enabled, so it is going to
behave exactly like a simple “S-R latch” without steering gates. Remember that since it is a latch,
when “S” goes low again, the output “Q” remains the same. Analyze the chronogram and try to
reproduce it step by step:

NAND gate
truth table
A B Output
0 0 1
0 1 1
1 0 1
1 1 0
 Gated S-R latch: chronogram example 2
Now let’s examine an example where input “E” varies. The starting state here is “0” for “Q”, and
because “E” is low, the latch is disabled, so as we can check, if “S” goes “high”, it has no effect on
the output “Q” since input “E” is disabled. Remember that input “S” and “R” are only going to
affect the latch if “E” is enabled, but being “E” enabled does not imply that “S” and “R” change the
output “Q”:

NAND gate
truth table
A B Output
0 0 1
0 1 1
1 0 1
1 1 0
 Gated S-R and gated R-S latches: summary
An R-S latch (the one built from “NOR” gates), can be turned into a “gated R-S latch” by adding a par
of “AND” gates to it. An S-R latch (the one built from “NAND” gates) can be turned into a “gated S-R
latch” by adding a pair of “NAND” gates to it. This changes the “S-R latch” from an “active-low S-R
latch” to an “active-high S-R latch”
Gated S-R latch
Gated R-S latch Logic symbol

Remember: a gated S-R/R-S latch has an extra

input “E” which must be high before the latch
responds to any changes in “S” or “R”
 Gated D latch: introduction
Gated D latch are a “1 bit memory device”, where “D” stands for data. They are also referred as just
“D latch”. D-latches can be build from a gated S-R latch. With this type of construction, we avoid a
problem that S-R latches have. Remember that a S-R latch can be constructed from NAND gates,
being as we know, an “active-high” S-R latch, which means that normally S and R are normally set at
low voltage (representing “0”), and a “positive pulse” (“1”) is required in order to set or reset the
latch. The problem that we have with this type of circuit (“gated S-R”) is that it exists the possibility
that “S” and “R” are made high simultaneously, and as we known, this is a forbidden state. But in
reality both “Q” and “” would become high.
Gated S-R latch
Logic symbol problematic
Remember: a gated S-R latch
has a third input, named “E”,
which when high, enables
the latch

Remember: if both “S” and

“R” fell to “0” at the same
time, the “raise condition
event” will occur, making the
nest state unpredictable
 Gated D latch: solving “gated S-R latch”
problematic
Since this kind of unpredictability in an electronic circuit is unacceptable, we can solve it by making
“S” and “R” the opposite just adding a single NOT gate, so the forbidden state where “S” and “R”
are both equal to “1” can never occur. We then rename the input “D” for data, having then a 1
input gated S-R latch.
Gated D latch Gated D latch renamed for simplicity
 Gated D latch: how it works
While the “enable input” “E”, if “D” is also high, then so is “Q”. While “E” is high, if “D” changes to
low, then so does “Q”. You can notice that while “E” is high, “Q” is always the same as “D”.
Remember that since we are using a NOT gate it is impossible for the latch to finish in the forbidden
state like an S-R latch might. As you can see, if “E” falls to “0”, output “Q” will retain its previous
value.

1 2

3 4
Gated D latch: how it works (II) and rewiring
the circuit
As you can see, the latch now will not respond to changes in input “D”, since input “E” is not
enabled, so it is locked in its current state.

5 6

D latch rewired

Now we can rewire the for NAND gates,

building a D latch in a different way, and these
circuits do exactly the same, but since
we are using less components, this version
is then more efficient and cheaper to make
 Gated D latch: NOT gate and rewired version
comparison
As we can see, the new version (the one in the bottom) is taking advantage that the output of the
top NAND gate is the inverse of the input “D”, as long as the latch is enabled, so the output is feed
back into the lower NAND gate. As we can see this new version behaves in the same way as the old
one (the one using the NOT gate) does. Let’s check an example considering the following starting
state:
Starting state:

Newer one 1

Old version 2
 Gated D latch rewired: how it works (I)
Let’s continue checking how the states evolves depending on the changes that we apply. Now “E”
goes low and the output “Q” remains with the same value, “0”. “E” is still low, “D” becomes high,
but there is no change in the output “Q” since the latch is still disabled. Now “E” becomes high
again, being “D” already high, so output “Q” goes high

4
3

Remember: since it is
a “gated” latch, input “E”
must be enabled so as to 5
the input “D” can affect
the circuit
 Gated D latch: chronogram example
Let’s try to analyze the following example of a chronogram for a gated D latch. Remember that since
“” is the opposite of the output “Q”, is not going to be consider in the chronogram:

Let’s consider “Q” = 0 as the starting state

D latch “abstraction NAND gate
symbol” truth table
A B Output
0 0 1
0 1 0
1 0 0
Remember: both of the
two types of “gated D latches” 1 1 0
behave exactly in the same way.
The one using the NOT gate, and
the “rewired one”. So the chronogram Remember: input “E” should be enabled
is exactly the same for both (“high”, value = 1) for the input “D” to
affect the circuit
 Gated D latch: chronogram exercise
Provided the following “time-chart” (chronogram), find the corresponding square wave of the
output “Q”. Consider the starting state of “Q” as “0”:
Gated D latch: chronogram exercise solution

NAND gate
truth table
A B Output
Remember: the D latch can be implemented either 0 0 1
with the “NOT gate” circuit or with the “rewired one” 0 1 0
1 0 0
1 1 0
 Gated D latch: summary and applications
“Gated D latches” or just “D latches” can be built from a “gated S-R latch”, either including a NOT
gate or by rewiring the existing NAND gates. Its behavior can be described as that the output “Q”
follows the input “D” while the latch is enabled, that is, while input “E” is high. If the latch is
disabled, it retains its current state. It can be used to store 1 bit of data, so it is a 1 bit memory
device:
D latch “abstraction
D latch using a “NOT” gate D latch rewired symbol”

To consider: an application of the D latches is using them to convert parallel

data into serial data. A group of D latches can hang on to several bits of data
while a multiplexer accesses them one at a time an places them onto a serial
transmission line. D latches are normally found in input/output ports
 Flip-flops: introduction to synchronous
sequential logic
Flip-flops are synchronous electronic devices of two states, they are also known as bistable
multivibrators. “Synchronous” implies that the output only changes with the signal of the clock, normally
named as “clk”. This clock signal is also normally referred as “control input”. To sum up, the changes in
the output occur synchronously with the clock signal. Flip-flops (from now on will be referred as just
“FF”), changes with the raising edge (when clock signal goes from low to high, that is, from “0” to “1”), or
it can also change with the falling edge (when the clock signal goes from high to low, that is, from “1” to
“0”). So we then have the following logic symbols abstraction for the principal types of FF that are used
in digital electronics: S-R flip-flops, D-flip-flops and J-K flip-flops:
J-K flip-flop To consider: we can
S-R flip-flop D flip-flop
distinguish vs the
raising edge set mode
and the falling edge
“raising-edge
mode by the different
mode”
symbols that we have
for the clock input.
The falling edge mode
has a small ball in the
“falling-edge clock input
mode”
 Flip-flops: implementation of the raising edge
So know, how can we implement the “raising edge detector” for our flip-flops so they are only
triggered and thus changing the output of “Q” only at the moment with the clock signal changes
from low to high?. Since depending on the frequency of the clock, the “enabling input” (“E”), might
be high for maybe as much as 50 microsecond which is a lot for a data latch to be opened for
changes in “D”, and for some applications, especially for those whose output is fed back to the
input, we can avoid this problem by limiting the amount of time during each clock cycle that the
latch can change state. Increasing the frequency of the clock is not a practical solution given that a
computer contains a mixture of fast and slow components
To consider: with
Problem: input “E” the raising edge,
enabled for a lot the input “E” is
of time only enabled during
a few nanoseconds.
1 ns = 10-9 s
Solution: “raising
edge”. Making the
input “E” affecting To consider:
“Q” only during the 50 µs = 0,00005 segs
raising edge
 Flip-flops: implementation of the raising edge
(II)
So we want to build a latch (for example a “D latch”) that only responds in changes in input “D”
during the raising edge thus being the next changing in “D” ignored until the next raising edge. We
can implement this “raising edge detector” with just adding a “NOT” gate and an “AND” together.
To consider: similarly when the input
Normal behavior 1 Normal behavior 2 changes from high to low, there is
another brief period when both the
NOT gate and the input are “0” at the
same time, but this does not affect
the raising edge because this does not
affect the output of the AND gate

To consider: since the NOT gate

does not inverse its input instantly.
So when the input changes from low
to high, there is a brief moment when
the output of the AND gate is the same as
its input To consider: so we have implemented then a device that detects
the very brief instant at which an input raises from low to high, then
implementing the “raising edge”
 Flip-flops: implementation of the raising edge
(III), effect on the chronogram

1 2

3
To consider: as we can see
this effect of the NOT
gate “lagging” can be used
to implement the
raising edge
 Flip-flops: implementation of the raising edge (IV),
adding it to the circuit and chronogram example
We can finally add our “raise detector device” to our circuit . Let’s check an example to see how
it works:
D Flip flop
“abstraction
symbol”
triggered by
Final implementation raising edge
in a “D latch”
 Flip-flops: raising edge problematic and
falling edge detector implementation
One of the problem with using this particular “raising edge detector device” is that the pulse that it
produces may not be wide enough to open the latch an let data in. This actually depends on
several factors including the operating characteristics of the electronic components and the specific
voltage levels being applied. However, we can increase the delay of our edge detector and
therefore the pulse by adding several NOT gates.
D Flip flop
“abstraction NOR gate truth
To consider:
symbol” table
we need an odd
triggered by
number of not gate A B Output
falling edge
to invert the signal
0 0 1
0 1 0
Falling edge implementation
1 0 0
To consider: we can build a “falling edge
detector” using a NOR gate instead. 1 1 0
When both are momentarily low at the
negative edge of the clock cycle, we will
get a high output
 S-R flip flops: how it works
Now that we have learned how to implement the raising edge detector and the falling edge
detector, let’s see how it works in a S-R flip-flop. Remember than in flip-flops the input data “S” and
“R” are only transferred to the output only with the clock pulse. Let’s summarize the behavior of a
“triggered raising edge flip-flop” with the following table:
INPUT OUTPUT NOR gate truth
COMMENTS table
S R CLK Q
Remember: 0 0 X No change A B Output
“clk” stands 0 0 1
0 1 0 1 RESET
for “clock pulse”
1 0 1 0 SET 0 1 1

1 1 ? ? Invalid condition 1 0 1
1 1 0
To consider:
we can see flip flops also build De Morgan’s Laws
with “negative-OR” gates instead of with
NAND gates, since their = *
behavior and therefore truth table is the NAND Negative - OR
same since we can apply the DeMorgan’s = +
theorems
 S-R flip flops: how it works (II)
So the electronic scheme for an S-R flip flop could be the following one. Remember that the
“negative-OR” gates are equivalent to the NAND ones:
To consider: “R-E-D”
S stands for “Raising Edge
Q Device” and “F-E-D” stands
for “Falling Edge Device”
CLK R-E-D/
F-E-D
Remember: a flip-flop cannot
𝑄 change state except during
R the raising edge or the falling
edge. This implies also that inputs
“S” and “R” can change while the
Steering gates Latch
clock input is high and there will
be no change in the output “Q”,
except during a small period of time
S-R Flip-Flop during the clock transitions from
low to high or high to low
 S-R flip flops: chronogram example
Provided the following “time-chart” (chronogram), find the corresponding square wave of the
output “Q”. Consider the starting state of “Q” as “0”:

Raising – edge triggered

S – R flip flop
S-R flip flops: chronogram example solution
To consider: Since the “abstraction symbol”
indicates that it is a raising-edge
triggered, changes in the output “Q” will
occur only in this event

INPUT OUTPUT
COMMENTS
S R CLK Q
0 0 X No change
0 1 0 1 RESET
1 0 1 0 SET
Invalid
1 1 ? ?
condition
 S-R flip flops: chronogram example 2
Provided the following “time-chart” (chronogram), find the corresponding square wave of the output “Q”.
Consider the starting state of “Q” as “0”:

Falling – edge triggered

S – R flip flop
S-R flip flops: chronogram example 2
solution
To consider: Since the “abstraction symbol”
indicates that it is a falling-edge
triggered, changes in the output “Q” will
occur only in this event

INPUT OUTPUT
COMMENTS
S R CLK Q
0 0 X No change
0 1 0 1 RESET
1 0 1 0 SET
Invalid
1 1 ? ?
condition
 D flip flops: how it works
D flip flops are useful when we need to store only a 1 bit memory (1 or 0). The implementation of
this flip flop is done by adding a NOT gate to a S-R flip flop. The behavior of this flip flop can be
summarized with the following table:
Implementing a D flip flop
To consider: we can add our “raising edge” using an S-R flip flop
detector or our “falling edge” detector
to each of the 3 flip flops that
we are going to learn: S-R flip flop, D flip flop
and J-K flip flop

Summarized behavior for

D flip flop raising edge trigger

INPUT OUTPUT
COMMENTS
D CLK Q
1 1 0 SET (stores a “1”)
0 0 1 RESET (stores a “0”)
 D flip flops: chronogram example
Provided the following “time-chart” (chronogram), find the corresponding square wave of the
output “Q”. Consider the starting state of “Q” as “0”:

Raising – edge triggered

D flip flop
 D flip flops: chronogram example solution
To consider: Since the “abstraction symbol”
indicates that it is a raising-edge
triggered, changes in the output “Q” will Solution: output “Q” follows the value
occur only in this event of input “D”

INPUT OUTPUT
COMMENTS
D CLK Q
1 1 0 SET (stores a “1”)
0 0 1 RESET (stores a “0”)
 J-K flip flops: how it works
It is one of the more used flip flops. Its behavior is really similar to the S-R flip flop for the SET and
RESET operation as well as for the “no change” case. The main difference between this type of flip
flop and S-R ones is that the J-K flip flop does not have “invalid conditions”. As we can see, its
circuit implementation is exactly the same as the S-R ff but now the outputs are feed back to the
inputs, so we are going to use two “3 inputs” NAND gates: NAND gate
truth table
Remember: “Negative-OR” gates behaves
exactly in the same way as “NAND” ones A B C Output

0 0 0 1
R-E-D/ 0 0 1 1
F-E-D 0 1 0 1
NAND Negative - OR
0 1 1 1
1 0 0 1
Remember: “R-E-D”
Steering gates Latch 1 0 1 1
stands for “Raising Edge
Device” and “F-E-D” stands 1 1 0 1
for “Falling Edge Device” J-K Flip-Flop 1 1 1 0
 J-K flip flops: how it works (II)
Let’s check the following table that summarizes the behavior of the J-K flip flop. Now, the non-valid
condition of a S-R ff just changes to the opposite state of the ff for the outputs. This is known as
“toggle state”. Let’s check the following truth table that summarizes the behavior of this ff:

Remember:
the main difference INPUT OUTPUT
between the S-R ff COMMENTS
J S CLK Q
and the J-K is that
in the J-K there a 0 0 No change
are no invalid states 0 1 0 1 RESET
1 0 1 0 SET
To consider: this type of 1 1 Toggle
flip-flop is widely used in
shift registers, ripple
counters, event detectors,
frequency dividers etc.
 J-K flip flops: chronogram example
Provided the following “time-chart” (chronogram), find the corresponding square wave of the
output “Q”. Consider the starting state of “Q” as “0”. Also indicate all of the states in the changes:

Falling – edge triggered

J-K flip flop
 J-K flip flops: chronogram example solution
Remember: the “toggle” event occurs when both “J” and “K”
are high at the same time converting then the output square-
wave into the opposite value

INPUT OUTPUT
COMMENTS
S R CLK Q
0 0 No change
0 1 0 1 RESET
1 0 1 0 SET
1 1 Toggle No
Toggle change Reset Set Set
Summary: synchronous vs asynchronous
sequential logic
Asynchronous
Asynchronous sequential circuits
are digital sequential circuits in
Definition which the feedback to the input for
next output generation is not
governed by clock signals.
The memory unit which is being get
Memory unit used for governance is clocked flip
flop.
The states of Synchronous
sequential circuits are always
predictable and thus reliable.
State
S-R and R-S latches, Gated S-R
Examples
latches, D latches
Synchronous
Synchronous sequential circuits are
digital sequential circuits in which
the feedback to the input for next
output generation is governed by
clock signals.
Unclocked flip flop or time delay is
used as memory element in case of
Asynchronous sequential circuits.
there are chances for the
Asynchronous circuits to enter into
a wrong state because of the time
difference between the arrivals of
inputs. This is called as race
condition.
S-R flip flops, D flipflops, J-K flip
flops
 Asynchronous counter: introduction
In digital logic and computing, a counter is a device which stores (and sometimes displays) the
number of times a particular event or process has occurred, often in relationship to a clock. A basic
asynchronous counter can be built using two flip flops which are going to be connected in the way
shown below. Let’s describe the behavior of a basic 2 bit asynchronous counter:
The first flip flop “FF0” (which is always the “LSB”) changes state at (in this case according to the
logical symbol) each of the raising edge of the clock pulse, whereas the second flip flop “FF1”
(which in this case is the MSB) is triggered by the output “” of the first flip-flop.
To consider: the 2 bit counter is connected basic 2 bit asynchronous counter logic
in an “asynchronous way”. This means that, symbol/circuit implementation with flip-flops
as we can see, the clock pulse is only HIGH
connected to the clock input of the first
flip-flop. Due to the inherent propagation
delay time through a flip-flop, a transition
of the input clock pulse “CLK” and of the
output “”, never occur exactly at the same
time, thus, the flip-flops are never triggered
at the same time, that’s why the counter
operation mode is “asynchronous”
 Asynchronous counter: introduction (II)
Let’s analyze the behavior of this 2-bit asynchronous counter by applying 4 clock pulses. The raising edge
of the first clock pulse “CLK1” triggers the first flip-flop “FF0”, making its output “” to go from low to high.
At the exact same time, the “negated output” “” goes from high to low. The raising edge of the second
clock pulse “CLK2” makes “” go from low to high, thus triggering the second flip-flop “FF1” and
consequently, making “” high since this flip-flop starts also in a “reset” state. For the third clock pulse
“CLK3”, “” goes high again, which implies that “” so it does not trigger the second flip flop “FF1”. The
raising edge of the last clock pulse “CLK4” makes “” to go low so “” goes high so it triggers the second
flip-flop “FF1”. After this last clock pulse, the counter is back in its original state:
To consider: the flip-flops
chronogram of a 2 bit asynchronous counter
are connected in a toggle Binary state sequence for a 2
state and are initially in a bit asynchronous counter
“reset” state. Check here Clock pulse
their truth table
Initially 0 0
Remember: is the 1 0 1
opposite signal of
2 1 0
Remember: here is the 3 1 1
explanation to distinguish
4 (new
“raising” vs “falling” edge 0 0
starting state (cyclical behavior) cycle)
 Asynchronous counter: 3 bit counter
The state sequence for a 3-bit asynchronous counter is shown in the next table. This type of counter is
going to work in the same way as the 2-bit counter does, except for its chronogram, which is going to has
as many as the double of clock pulses as the 2-bit counter has, hence the 3-bit asynchronous counter is
going to have 8 states. Let’s analyze the chronogram of the 3 bit counter and its circuit implementation:

To consider: HIGH Binary state sequence for a 3

bit asynchronous counter
adding more
flip-flops makes Clock pulse
the counter to Initially 0 0 0
increase its
number of 1 0 0 1
states. 2 0 1 0
3 0 1 1
Number of
states = 4 1 0 0
where “nf” is 5 1 0 1
“number of 6 1 1 0
flip-flops”
7 1 1 1
8 (new
starting state (cyclical behavior) 0 0 0
cycle)
 Asynchronous counter: delay propagation
Asynchronous counter are also called “ripple counters” because the clock signal is firstly “felt” by the first
flip-flop “FF0” and is output “” (that as we know it works as the clock pulse of the second flip-flop) does not
affect immediately to the second flip-flop “FF1” due to the propagation delay through “FF0”. This happens
also for the next flip-flops, it occurs a delay in the signal propagation through “FF1” also, affecting “FF2” too.
The clock pulse is propagated through the counter, taking some time to reach the last flip-flops due to
propagation delays. As we can see in the chronogram of this 3-bit asynchronous counter, all of the flip-flops
that compound the counter change state in the raising edge of the clock pulse “CLK4”, the changes don’t
really occur at the same time nonetheless. For example, the transition from low to high of “” takes a time
to occur (it can be named as “”). This delay is also going to happen for the clock ripple from “” to “” (named
as “”) and so on. So for the last flip-flop to be triggered (“FF2”) it is going to take 3 delays to occur (CLK to ,
to and finally to ):
To consider: this cumulative delay of the
asynchronous counters are one of their
biggest drawbacks for many applications
Propagation
since it limits the rate at which the counter
delays in a 3-bit
can be clocked and creates decoding
asynchronous
problems.
binary counter
The maximum cumulative delay in a
counter must be less than period of the
clock waveform.
 Asynchronous counter exercise:
Provided the following 4-bit asynchronous counter, each flip-flop has a propagation delay of 10
nanoseconds (ns). Draw the corresponding chronogram that shows the output “Q” of each flip-flop
and determine the total propagation delay from the triggering edge of a clock until it occurs in the
output of the last flip-flop (). Determine also the maximum clock frequency at which the counter
can operate:
Hint: all the clock pulses delays
affect the last output?

To consider: the counters can also be built using

falling edge (active-LOW triggers). In this way we
don’t have to use the negated output “”
 Asynchronous counter exercise: solution
The first thing to consider is that the delays that occur in each clock pulse of the chronogram, do
not affect the last output since it only matters the delays that occur in the eighth clock pulse.
Provided that we have 4 flip-flop, having each of them the same delay (10 ns), the total delay that
occurs in the eighth clock pulse (CLK8) is:
Remember:
total delay ()= number of ff * delay in each ff = 4*10ns = 40 ns flip-flops are
The maximum frequency of the clock cannot be higher than the total delay, so we have: sometimes
referred as
= = = 25 MHz “ff”

To consider:
To consider:
the delays in
The pulses
other clock
delays are not
pulses don’t
drawn for
affect the
simplicity
delay in the
other clock
pulses
 Asynchronous decade counters:
The modulus of a counter is the number of unique states the counter will pass through. The maximum
possible numbers of state of a counter is , where “n” is the number of flip-flops of the counter. It is possible
to design also a counter that have a number of states in their sequence which is less than the maximum “”,
this is called “truncated sequence”. One common modulus for counters with truncated sequences is ten
(called “MOD10”), this type of counters are called “decade counters”. For example, there are BCD decade
counters whose sequence goes from “0000” to “1001” (0 and 9 respectively in decimal). In order to obtain a
truncated sequence it is necessary to force the counter to restart a new cycle before going trough all of its
possible states. Let’s see how to implement a truncated decade synchronous counter that has an
asynchronous recycling: 10 decoder
To consider:
To consider: BCD the BCD
decade counters HIGH decade
are really useful counter has
in display to restart the
applications cycle in
where BCD codes “0000” after
are needed to reaching
convert to “1001”
decimal

To consider: a decade counter will need 4 flip-flops because with

only 3 we can only have 8 different states ( = 8)
 Asynchronous decade counters (II):
Now we’ll analyze how to implement a Binary/BCD
truncated sequence, we will use a 4-bit Decimal
asynchronous counter to illustrate how this
works. One of the ways if making the 0 0 0 0 0
counter to start a new cycle after reaching 1 0 0 0 1
a certain number, in this case for example , 2 0 0 1 0
() in BCD code, consists of decoding the
number ( in BCD) by using a NAND gate 3 0 0 1 1
for the clear inputs “” of the flip-flops. As 4 0 1 0 0
we can see, only the inputs and are 5 0 1 0 1
connected to the NAND gate inputs (this
logic gate is working as a decoder). This 6 0 1 1 0
arrangement is known as partial decoding 7 0 1 1 1
in which only with these inputs HIGH it is 8 1 0 0 0
sufficient to decode the count of ten
because none of the other states 9 1 0 0 1
(expressed in binary/BCD) have and 10 1 0 1 0
HIGH at the same time:
Remember: to “truncate” a counter implies making its
number of states inferior to “” (n= number of flip-flops)
 Asynchronous decade counters (III):
When the counter reaches the number (()) the output of the decoder gate (the NAND gate) changes to
LOW and asynchronously resets all of the flip-flops to “0”. There is a glitch in the on the waveform at
the clock pulse 10 “CLK10”. The reason for this glitch is that has to first go HIGH before the number (())
can be decoded. Since not until a few nanoseconds after that the counter reaches ten, the output of
the decoding gate goes LOW (gets triggered because both of the inputs and are HIGH at that
moment). This causes that the counter is in the state () for a few nanoseconds before it gets reset to 0
() producing the glitch in and at the line that resets the counter:

To consider: there is
no glitch in “”
Chronogram of a 10
because it is already
module asynchronous
HIGH when the
counter with active-LOW
decoding occurs
clear input
implementation
 Asynchronous decade counters exercise:
Implement the circuit and chronogram for an asynchronous counter with MOD12:

Hint: the clear input “” is

necessary for all the flip-flops?
Asynchronous decade counters exercise: solution
On condition that 3 flip-flops can generate a maximum of 8 states (from 0 to 7), we are going to need
another ff in order to produce any module higher than 8 and less than or equal to 16. When the
counter reaches the last state of 11 (), it has to start a new cycle going back to “” instead of continuing
to its normal state “”. It is not necessary to decode the inputs “” and “” since the “decoding state” and
the following values match the “recycle values” (the starting values of the binary/BCD code).
Binary/BCD
12 decoder Decim
al

HIGH 0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
… … … … …
11 1 0 1 1
12 1 1 0 0
Decoder not required for and due to the “matching digits” 13 1 1 0 1
14 1 1 1 0
 Asynchronous decade counters exercise:
solution (II)
As in previous counters, there is going to be a glitch, in this case it is going to take place in output “”
and obviously in the clear input “”. We are going to have the following chronogram for a 12 module
asynchronous counter:

To consider: it is
Remember:
also possible to
the duration
implement the
of the glitch is
partial decoding
going to be a
with AND gates
few
but in this case
nanoseconds
the active-HIGH
(ns)
logic is going to be
used instead
 Asynchronous counter: reducing the
frequency and exercise
Something important to notice is that the output of our decoding gate, the NAND gate, is going to
have a frequency that is going to be:
decoding frequency =
In this example, supposing that the clock has a frequency of 1KH:
decoding frequency = = = 100 hertz
Provided that, it is possible to reduce the frequency of each of the elements of an electronic
device to the one desired.

Exercise: having a frequency of 800 hertz it is required to lower it

to 10 hertz, build the corresponding asynchronous counter

To consider: this is useful because in an electronic device, the

different parts (microprocessors, mother board, graphic card…) have
different frequencies being possible to change them in this way
 Asynchronous counter: reducing the
frequency and exercise solution
On condition that the final frequency of our device must be 10 hertz and the initial 800 hertz, we
must create a counter with a truncated module of 80 (MOD80). () into binary is (), so 7 flip-flops
will be required. With 7 flip flops we are going to have a module of “MOD128” ( = 128 possibilities,
from () to ()):
FF output
64 4 2 1
Binary 1 0 1 0 0 0 0

Finally we have
implemented a
counter that
counts from ) to
()
 Getting the MOD from a counter exercise:
Provided the following asynchronous counter get their corresponding modules (MOD) and their
decoding frequency: Asynchronous counter 2
Clk frequency: 81 KH
Asynchronous counter 1

Clk frequency: 42 KH

What do you notice Asynchronous counter 3

about the last counter?
 Getting the MOD from a counter exercise
solution:
We have truncated asynchronous counters since they get a decoder sequence:
Asynchronous counter 1 Asynchronous counter 2

It is going to be a “MOD 8” at the most, It is going to be a “MOD 16” at the most, Asynchronous
being truncated at “” (MOD 7) therefore being truncated at “” (MOD 9) therefore counter 3
counting from counting from
FF output This asynchronous
FF output
counter can be
4 2 1 8 4 2 1
implemented with
Binary 1 1 1 Binary 1 0 0 1 only 3 flip-flops
instead of 4 since the
Decoding frequency: 81KH/MOD 9 = 9 KH truncated sequence
Decoding frequency: 42KH/MOD 7 = 6 KH
occurs at being this
number smaller that
the maximum mod of
a 3 asynchronous flip-
flop () (MOD 8)
 Synchronous counter: introduction
The term synchronous means that the events have an established direct relationship between
them, in other words, this implies for example that, in synchronous counters all of theirs flip flops
receive at the exact same moment the clock signal. Let’s compare then a 2 bit synchronous
counter with a 2 bits asynchronous counter:
2 bit synchronous counter
2 bit asynchronous counter
HIGH
HIGH

To consider: as we can see, the main difference between an asynchronous and a synchronous
counter is that for the second one the clock pulse is the same for all of the flip flops whereas in
the asynchronous one the output “ works as the clock for the second flip flop
 2 bit synchronous counter:
Let’s see how this basic counter works. We first assume that the counter is in the “0 binary state”,
which implies that both of the flip-flops are in the reset state. When the first positive edge of the first
clock pulse is applied, “FF0” will toggle and therefore “” will go HIGH. Since there is a propagation
delay, when the first clock pulse occurs, the output of the first flip-flop, that is “” is still low so it does
not trigger the second flip-flop “FF1” (1) (it is the output of the first one and the input of the second).
When the second clock pulse (CLK2) is applied, “” is still high so now it triggers the second flip-flop
“FF1” (2). This works in a very similar way for the clock pulse “CLK3” and “CLK4” (3), (4):

(1) (2)

(4)
(3)
 2 bit synchronous counter:
We finally get the following chronogram for a simple 2 bit synchronous counter. In this chronogram
the waveform transition appear coincident, which means that the propagation delays are not
indicated for simplicity.

Chronogram of a 2 bit synchronous counter omitting

the clock delays To consider: these
type of flip-flops
can be also
implemented with
XOR gates and D-
type flip-flops
 3 bit synchronous counter:
As usual, we are going to take a look at the state Circuit implementation of a 3-bit synchronous counter
sequence so as to give us a hint on how to
implement it. As we can see “” changes on each
clock pulse as the counter progresses from its
original state to its final one and then back to the
original. For the purpose of achieving this behavior,
“FF0” must be kept in toggle state, this is managed
by constantly applying HIGH pulses to both of the
inputs ( and ) of this first flip-flop. “” is going to the
opposite state each time “” is “1”. This happens in
the clock pulses “CLK2, CLK4, CLK6 and CLK8”. “” is
connected to the inputs of the second flip-flop “”
and “”. When “” is at “1” and a clock pulse occurs,
the second flip-flop “FF1” changes since it is
connected in toggle state, while the rest of the
times, “FF1” is in “no change” state, and keeps in
that state when the clock pulse occurs as it name
implies. If we pay attention to the binary sequence,
we can see that the third flip-flop changes states
Remember: the ripple/propagation delays are
when both “” and “” are HIGH at the same time.
not drawn in the chronogram for simplicity
This is implemented with an AND gate:
 3 bit synchronous counter (II):
Whenever “” and “”, the output of the AND gate makes the input of the last flip-flop “FF2” ( and ) to
go HIGH, consequently “FF2” toggles. At all the other times, “”, “” and FF2 are kept LOW, as well as
the output of the AND gate, so “FF2” does not change its state:

Binary state sequence for a 3 bit synchronous counter

Clock pulse Remember: both of
Initially 0 0 0 the times in the
1 0 0 1 cyclic sequence (the
2 0 1 0 8 states), changes 2
3 0 1 1 times, and each of
these 2 times it
4 1 0 0
changes and are
5 1 0 1 both high at the
6 1 1 0 same time.
7 1 1 1 Therefore, this can
8 (new cycle) 0 0 0 be implemented
with an AND gate
 3 bit synchronous counter: summary table
All of the behavior of the 3 bit synchronous counter is summarized in the following table:

Summary table of the 3 bit synchronous counter

Outputs J-K inputs At the next clock pulse
Clock pulse
FF2 FF1 FF0
To consider: Initially 0 0 0 0 0 0 0 1 1 NC NC Toggle
“NC” means
1 0 0 1 0 0 1 1 1 1 NC Toggle Toggle
“No change”
2 0 1 0 0 0 0 0 1 1 NC NC Toggle
3 0 1 1 1 1 1 1 1 1 Toggle Toggle Toggle
4 1 0 0 0 0 0 0 1 1 NC NC Toggle
5 1 0 1 0 0 1 1 1 1 NC Toggle Toggle
6 1 1 0 0 0 0 0 1 1 NC NC Toggle
7 1 1 1 1 1 1 1 1 1 Toggle Toggle Toggle
 4 bit synchronous counter:
Once we have understood the behavior Circuit implementation of a 4-bit synchronous counter
and circuit implementation of the previous
synchronous counters, the 4 bit one is
pretty intuitive. Again we just take a look at
its state sequence, which in this case is
going to have 16 different states (= 16),
and we can even create a law to
summarize the number of AND gates
required for the implementation provided
the number of bits of the counter:
AND gates required = nº bits – 2
As a result, this counter is going to have
the following circuit implementation and
chronogram:
< <
To consider: < <
• Blue rectangle: toggle condition due to
the delay of and
• Green rectangle: toggle condition due
to the delay of , and
 4-bit synchronous decade counter:
As we know, a decade BCD counter has a truncated sequence that goes from “0000” to “1001”.
Instead of going to the state “1010”, it recycles to the “0000” state. Let’s see how it is implemented
by looking at its state sequence. As we can see, the first flip-flop “FF0” toggles in each clock pulse,
so its inputs are going to be “” and “” = 1. This is implemented by connecting these inputs to a
constant HIGH level. For the second flip-flop, we can see that its output “” changes on the next
clock pulse each time that = 1 and = 0, so this can be implemented with the following equation:
= =
This is implemented by applying the AND operation to these outputs and and connecting the
output of the gate to the inputs of the second flip-flop “FF1”
The third flip-flop “FF2” changes its state each time that = 1 and = 1, so its logic equation is:
= =
Again this is implemented with an AND gate and connecting its output to the inputs “” and “”
For the last flip-flop “FF3”, it changes its state each time that = 1, = 1 and = 1, or when = 1 and =
1, therefore the equation which implements this is the following one:
= = +
This function is implemented with AND/OR logic connected to the inputs and
 4-bit synchronous decade counter (II):
Circuit implementation of a 4-bit synchronous BCD decade counter
States of a BCD decade counter
Clock
pulse
Initially 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10
0 0 0 0
(recycles)
 Registers: introduction
Registers and counters are similar to each other, both of them use a cascade of flip-flops in which
the output of one flip-flop is connected to the input of the next one. A register can be built out of
one or several flip-flops. The main use of registers is storing data, but they are also used in data
transfer. The main difference between a register and a counter is that a register does not have an
specific “status sequence”. To sum up, registers are used to store and transport data that an
“outside source” introduces on it, not having a concrete status sequence though. Let’s see an
example of a basic register using a single “D-type flip-flop”:
Procedure of storing a “1” Procedure of storing a “0”

A “1” is applied to the data It happens similarly when

entrance and a clock pulse
makes that it gets stored being
then the flip-flop in a “SET”
state. One the “1” is removed,
the FF remains in that “SET”
state, still storing a “1”
there is a “0” in “D”, the output
“Q” turns to “0” in the clock
pulse or it remains with the
value “0” if it was already in the
“RESET” state
 Registers: introduction (II)
The “storing capacity” of a register, is the total number of bits (1s or 0s) of a digital data that it can
contain. Each “stage” (or “Flip-Flop”) of a register, represents one single bit of data, therefore the
number of flip-flops of a register determines its “storing capacity”. The data (bits) inside a register,
can also move through it, from one flip-flop to the following one depending on the clock pulses
that are being applied. These are some of the different ways the data can move through a register:
Series input/output Series input/output Left
right shifting left shifting rotation

Data Data input

Data input Data output
output Data output
Parallel input
Series input parallel output Parallel input
parallel output series output Right
Data input
rotation
Data input
Data
input

Data output
Data output
Data output
 Registers: series input and output
This type of registers accept “series data”, which means that they are going to process one bit each
time by a single line. The way they are “outputting” the data is also in a “series way”. Let’s see an
example with explanation of how a data input works with a register of 4 bits. In the example we are
going to store “”. Since it is a series input/output with right shifting, we will start storing the LSB
(“0” in this case). First we are going to clear the register, thus deleting any data that the register
might be storing.
Serial in/serial out shift register
Remember: the number of
flip-flops a register has is going
to indicate its “storing capacity”.
For example, a 4 flip-flop
register can store 4 bits of
data at the most

To consider: it is frequently necessary to clear an internal register of a computer. For

example, a register may be cleared prior to an arithmetic or other operation. One way
that registers in a processor are cleared is using software to extract the contents of the
register from itself. For instance, a processor instruction that performs this operation is
SUB AL,AL. with this instruction, the register named AL is cleared
Series input and output register: how it works
For this example let’s consider a device made out of with 4 “D-type flip-flops”. They are obviously
going to be connected in series. Remember that this means that this device is going to receive one
bit each time by the “input line”. Provided that it is a 4 bit registers since it is made out of with 4
flip-flops, we are going to have “4 stages” that can store up to 4 bits. Let’s consider that we want to
store in our register, we are going to start storing these data starting with the “least significant bit”
(LSB), that means, with the bit at the very right position, a “0” in this case. So we start with a “0” in
the first flip-flop “FF0”. When the first clock pulse is applied, FF0 passes to the RESET state, storing
the “0”.

Data
To consider:
input
Initially, the register is Input data
going to be cleared currently is
before starting to “clear” state
store the data
 Series input and output register: how it
works(II)
Next, the second input data is applied, which in this case is a “1”, what makes that “D” in the first
flip-flop’s (FF0) output “” is now “1” and the output for the second flip-flop (FF1) “0” since the input
of FF1 is connected to the output “” of the first flip-flop. The same is going to be working for the
rest of the clock-pulses, moving the data (in this case “”) along the (in this case) four “D-type” flip-
flops:
To consider: First bit of data
As we can see, “0”
the numbers are After the first
moving as a block clock pulse
through the flip-flops “CLK1”

To consider: the Second bit of

same concept applies data “1”
After the first
to the second clock
clock pulse
pulse
“CLK2”
 Series input and output register: how it
works(III)
The third bit, which according to the data that we want to store , is so, going to be a “0”, which it is
introduced by the data input and a clock pulse is applied. The “0” is stored in the first flip-flop
“FF0”, being the “1” stored on it displaced to the next flip-flop “FF1”, and the “0” bit of data stored
before on “FF1” is displaced to the next flip-flop “FF2”. For the last bit, the logic that follows is the
same; this bit is a “1”, it is applied to the input data, and the next clock-pulse is applied. Now the
“1” enters the first flip-flop “FF0”, while the “0” stored is again displaced to “FF1”, the “1” stored
previously on “1” is displaced to “FF2” and so on:

To consider: Third bit of data

the interesting “0” After the
use about registers third clock
is that data can be pulse “CLK3”
stored indefinitely
as long as we
provide the FF’s Fourth bit of
with the corresponding data“1” After the fourth clock pulse
continuous current
“CLK4”. The 4 bit number
needed
“1010” is finally stored on
the register
Series input and output register: how it works
(IV)
In order to extract the data from the register, the bits must move in order (in series way) until they
reach the output . After the fourth clock pulse “CLK4”, the “LSB” bit (“0” in this case), is “located” in
the output “”. If a fifth clock pulse is applied (“CLK5”), the second bit will be placed on the output “”.
The sixth clock pulse “CLK6” moves the third bit to the output and the seventh clock pulse “CLK7”
moves the fourth bit to the output. Remember that after the 4 bits (provided that it is a register
compound of 4 “D-type flip-flops”) are displaced to the output, new bits of data can be introduced.
In this example, we consider that a 4 bits of data with the value of four zeros “0000” are introduced
to the register:

First bit of data

After the clock pulse “CLK4”,

the register contains “1010”
Series input and output register: how it works (V)
Second bit of data

After CLK5

Third bit of data

After CLK6

Fourth bit of data

After CLK7
 Series input and output register: “truth table”
summary
The behavior of a register when it processes some input data (data insert and data “expel”), can be
summarized with a “truth table”. In this initial example, we are processing “”:

Shifting a 4-bit code into a 4-bit serial in/serial out Shifting a 4-bit code out of a 4-bit serial in/serial
shift register out shift register
CLK FF0 () FF1 () FF2 () FF3 () CLK FF0 () FF1 () FF2 () FF3 ()
Initial 0 0 0 0 Initial 1 0 1 0
1 0 0 0 0 5 0 1 0 1
2 1 0 0 0 6 0 0 1 0
3 0 1 0 0 7 0 0 0 1
4 1 0 1 0 8 0 0 0 0
 Series input/output register exercise:
Obtain the states of the following 5 bit register. Consider that the register has been cleared (its
starting state is storing all zeros):

Hint: how does the data move

in serial in/serial out registers?
 Series input/output register exercise: solution
To consider:
The data to be
stored is “”. To consider:
So after fifth clock pulses, draw the circuit
the output of the last and write the
flip-flop is obviously transfer of the
going to store the first bit, bits step-by-step
which in this case is “1”, in order to
and the first one is going understand how
to be storing the last bit they move
to be inserted, which in through the
this case is “0” storing device

Remember: the bits of data are

going to be moving “as a block”.
 Serial In/Parallel Out Shift Registers:
In this type of register, the input bits are entered serially (least-significant bit first) similarly as the
were introduced in the serial in/serial out shift register. The difference lies in the way in which the
data bits are taken out of the register, in the parallel output register, the output of each stage is
available. Once the data is stored, each bit appears on its respective output line, being all bits
available simultaneously, rather than on a bit-by-bit basis as with the serial output. Let’s see its
diagram and logic symbol:

Logic diagram of a serial in/parallel out register

Logic symbol of a serial in/parallel out register

Simultaneous outputs
 Serial In/Parallel Out Shift Registers
exercise:
a) Show the states of the 4-bit register for the following data inputs and clock waveforms. The
register is initially storing all 1s
b) If the data input remains 0 after the fourth clock pulse, what is the state of the register after
three additional clock pulses?
c) The bit sequence “1101” is inserted in series (first the bit located at the right) in a 4-bit serial
in/parallel out register that has been initially cleared. What are the “Q” output after two clock
pulses?

Hint: remember the similarities

between this type of register
and the serial input/output one
 Serial In/Parallel Out Shift Registers
exercise: solution
a) After 4 clock pulses, the register state is storing “0110”

Remember: in this type of

register, the data is also
moving as a block, it does
not change its “input
behavior” with respect to
the serial in/out one

b) After the fourth clock pulse, if the input is kept in “0”, these “0s” are going to replace the
previous inputs, being the final output “0000”
c) We input the first two bits (the ones in orange) of “1101” in a 4-bit serial in/parallel out which
has been previously cleared. After 2 clock pulses, “01” are the outputs “” and “” being the ones
for the last two flip-flops “0”, provided that these were the bits of the outputs of the first two
flip-flops, and have been “pushed” along the register output
 Parallel in/serial out shift registers:
In this type of register, the bits are entered simultaneously into their respective stages on parallel lines rather
than on a bit-by-bit basis on one line as with serial data inputs. In the following logic diagram, we can see the
implementation of a 4-bit register with parallel input and serial output, and its logic symbol as well. There are 4
data-input lines: , , and and a “SHIFT/” input, which allows to load in parallel these four bits of data into the
register. When “SHIFT/” is LOW, gates from “” to “” are enabled, thus allowing each data bit to be applied to
the “D input” of its respective flip-flop. When a clock pulse is applied, the flip-flops with “D = 1” will be set an
those with “D=0” will be reset, thereby storing all four bits simultaneously. When “SHIFT/” is HIGH, gates from
to are disabled and gates from to are enabled, then allowing the data bits to shift right from one stage to
the next one. The OR gates allow either the normal shifting operation or the parallel data entry operation,
depending on which AND gates are enabled by the level on the SHIFT/ input.
Logic symbol
To consider: the serial
outputs is the same as
in serial in/serial out
shift registers, once the
data is completely
stored in the register.
Working state of the register
Logic diagram Input of a “1” Shift state
Input of a “0” Load state
 Parallel in/serial out shift registers: how it
works (load state)
As explained on the previous slide, we have a register which is going to load in a parallel way, and
these data will be output in a bit-a-bit basis at a single output
1 1 0 0 To consider: notice
0 1 1 1 that this register is
triggered on the
0 0 0 1 raising edge

Key:
The input data • Combinational circuit
for this example • State of the register
is “” () • Input data

To consider: an application
of this register is to
1 transmit the data through a
1 0 0 serial communication
channel. In every clock
pulse we are transmitting
one bit
 Parallel in/serial out shift registers: how it
works (shift state) (first clock pulse)
After the data has been input to the register, we change its state to “shift” by inputting a “1”
before the NOT logic gate. In the shifting state (after the loading state), a 0 is input by default.

1 0 0 0 0
To consider: this is the
1 1 1 first step out of 4 (four
1 1 0
In the shifting state, the bits to transfer since
logic gates “”, “”, “” and we are transmitting “”
“” are “closed” since now ())
we don’t want the data
to be loaded again.
0 1 1
0
Key:
• Input data 0 1 1 0
• Control input
 Parallel in/serial out shift registers: how it
works (shift state) (second clock pulse)
For the second clock pulse we are going to have the following state of the register considering that
we are inputting “0s” during the shift state:

1 0 0 0 0
1 1 1
0 1 1
In the shifting state, the
logic gates “”, “”, “” and
“” are “closed” since now
we don’t want the data
to be loaded again.
0 0 1 1
Key:
• Input data 0 0 1 1
• Control input
 Parallel in/serial out shift registers: how it
works (shift state) (third clock pulse)
For the third clock pulse we are going to have the following state of the register considering that we
are inputting “0s” during the shift state:

1 0 0 0 0
1 1 1
0 0 1
In the shifting state, the
logic gates “”, “”, “” and
“” are “closed” since now
we don’t want the data
to be loaded again.
0 0 0 1
Key:
• Input data 0 0 0 1
• Control input
 Parallel in/serial out shift registers: how it
works (shift state) (fourth clock pulse)
For the third clock pulse we are going to have the following state of the register considering that we
are inputting “0s” during the shift state:
1 0 0 0 0
1 1 1
0 0 0
In the shifting state, the
logic gates “”, “”, “” and
“” are “closed” since now
we don’t want the data
to be loaded again. 0 0 0 0

Key: 0 0 0 0
• Input data
• Control input
 Parallel in/serial out shift registers: exercise
Provided the following sets of input data, get the corresponding chronogram for the output of a
parallel in/serial out shift registers:

0 1 0 1
Parallel in/serial out shift registers: exercise
solution

0 1 0 1
 Bibliography:
• Floyd, T. L. (2000). Fundamentos de Sistemas Digitales, 9ª. Edición,
Capítulo, 2, 2-10.