VLSI 시스템

정정화
Design through Various Levels of
Abstraction
 Architecture level
 Behavior RAM ROM
ALU
 Area Estimates
PLA I/O

 Register Transfer
Level
 Functions
 Timing
 Logic Level
0 &
0

 Bits
 Timing

 Current Level
 Voltages
 Currents

Polysilicon
 Physical Level
Metal
(=Layout)
 Dimensions Diffusion

Contact
 Device Level Gate

 In Characteristic
Source Drain

 Technology Level Doping

Dopant A
 Impurity Profiles Dopant B

Depth
 Bebavioral Domain Structure Domain Physical Domain
System Performance specs. CPU`s Physical partitions
Level Memories
Switches
Controllers
Buses
Algorithm Algorithms Hardware modules Clusters
Level (manipulation of data Data structures
structure)

Microarchite Operations ALUs Floor plans

ctural Level Register transfers MUXs
State sequencing Registers
Microstore
Logic Level Boolean equations Gates Cells, module plan
FSM Flip-Flops
Cells

Circuit Level Transfer functions, Transistors Layout

timing Wires
Contacts
 Memory element input equations
JY 1  x
(1) Z
KY 1  x
J Y 0  Z  ( x  y1 ) y0 X
(2)
KY 0  ( x  y1 ) y0
Q
SET
J
JY1
 The next state equation for J-K Flip-Flop Y1 Y1
Q CLR
K

y v 1  J y v  K v y v (3)
Q
SET
J
JY0
Clock
Y0 Y0
 For the memory element y0, y1, Q CLR
K

the next state equation of (1), (2)

y1v 1  x v y1v  x v y1v  x v
(4)
y0v 1  [( x v  y1v ) y0v ] y0v  [( x v  y1v ) y0v ] y0v  ( x v  y1v ) y0v (5)
Transition table

y1v y0v y1v 1 , y0v 1 xv

y1 y2
xv 0 1 0 1 q1 state = 0 0
0 0 0 0 11 0 1 q2 state = 0 1
0 1 0 0 10 0 0
1 0 0 0 01 0 0
q3state = 1 1
1 1 0 1 11 1 1 q4 state = 1 0
 State table State diagram
X /Z
y y Present
v v
xv 0/0 1/1
1 0
states q1 q3
v Input
q 0 1 0/0
0 0 q1 0 1 0/0 1/0 1/1
1/0
0 1 q2 0 0 Output
q3 q2 q4
1 0 0 0 0/1

1 1 q4 1 1
q v 1 z v
 Memory
State element
diagram State input
assignment equation

Minimal
Functional State Transition
state Circuit
description table table
table

Analysis Process

Design Process

(Logic Synthesis)
Structure of Digital System

Data path
Logic circuit

Control Branch
signal information

Sequential control
Logic circuit
 T1 address bus  (PC)
T2 PC  (PC) + 1
1
T3 IR  (M)
T4 decode

T1 address bus  (PC)

2 T2 PC  (PC) + 1
T3 Z  (M)

T1 address bus  (PC)

3 T2 PC  (PC) + 1
T3 W  (M)

T1 address bus  (PC)

4 T2 --------
T3 Acc  (M)
Logic Design Flow &
Data, Instruction Format
• Logic Design Flow • Data Format
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

SPEC s MAG

S : Sign (+ if “0”, - if “1”)

Func. Design
MAG : Magnitude

Functional
• Data & Instruction Format
Simulation
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

op ADR
Collection of
Condions

OP : OP Code
Gate Level
Circuit Design
ADR : Address
Instruction Set
OP Code Operation
LOAD 000100 ACC (M(ADR))
STORE 001000 M(ADR) ACC
ADD 010000 ACC ACC+(M(ADR)
BRANCH 100000 BRANCH TO ADR
BRANCH-POSITIVE 100001 BRANCH TO ADR IF
(ACC)>=0
ACC : Accumulator
ADR : Address part in instruction
M(ADR) : Address No. of memory
State Diagram for instruction Cycle

ADS

ADS ; Address Set

IFT : Instruction Fetch
DEC : Decode IFT
LDA : Load
STA : Store
ADD : Add
BRA : Branch DEC
BPR: Branch-Positive

LDA STA ADD BRA BRP

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_components.all;
use WORK.MATH.all;

entity CPU is
port ( CLOCK : in std_logic;
RESET : in std_logic);
end CPU;
architecture BEHAVIORAL of CPU is
type STATE_TYPE is (ADS, IFT, DEC, LDA, STA, ADD, BRA, BRP);
type MEMORY is array(0 to 6) of std_logic_vector(15 downto 0);
signal CURRENT_STATE, NEXT_STATE : STATE_TYPE;
signal MEM : MEMORY := MEMORY'("0001000000000011",
"0100000000000100",
"0010000000000101",
"0000000000000111",
"0000000000001001",
"0000000000000000",
"0000000000000000"
);
signal ACC, IR : std_logic_vector(15 downto 0);
signal MAR, IAR : integer range 0 to 1023;
begin
-- process to hold combinational logic
COMBIN : process(CURRENT_STATE, RESET)
variable temp : std_logic_vector(15 downto 0);
begin
if RESET = '1' then
MAR <= '0';
IAR <= '0';
NEXT_STATE <= ADS;
else
case CURRENT_STATE is
when ADS =>
MAR <= IAR;
IAR <= IAR+1;
NEXT_STATE <= IFT;
when IFT =>
IR <= MEM(MAR);
NEXT_STATE <= DEC;
when DEC =>
MAR <= vector2int(IR(9 downto 0));
case IR(15 downto 10) is
when "000100" =>
NEXT_STATE <= LDA;
when "001000" =>
NEXT_STATE <= STA;
when "010000" =>
NEXT_STATE <= ADD;
when "100000" =>
NEXT_STATE <= BRA;
when "100001" =>
NEXT_STATE <= BRP;
when others =>
null;
end case;
 when LDA =>
ACC <= MEM(MAR);
NEXT_STATE <= ADS;
when STA =>
MEM(MAR) <= ACC;
NEXT_STATE <= ADS;
when ADD =>
temp := add_sub(ACC, MEM(MAR), TRUE);
ACC <= temp;
NEXT_STATE <= ADS;
when BRA =>
IAR <= MAR;
NEXT_STATE <= ADS;
when BRP =>
if ACC(15) = '0' then
IAR <= MAR;
end if;
end case;
end if;
end process;
-- process to hold syschronous elements (flip-flops)
SYSCH : process
begin
wait until CLOCK'event and CLOCK = '1';
CURRENT_STATE <= NEXT_STATE;
end process;
end BEHAVIORAL;
configuration CFG_CPU_BEHAVIORAL of CPU is
for BEHAVIORAL
end for;
end CFG_CPU_BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
package MATH is
function add_sub(L, R : std_logic_vector; ADD : BOOLEAN)
return std_logic_vector;
function vector2int(S : std_logic_vector(9 downto 0))
return INTEGER;
end MATH;
package body MATH is
function add_sub(L, R : std_logic_vector; ADD : BOOLEAN)
return std_logic_vector is
variable carry : std_logic;
variable A, B, sum : std_logic_vector(L'length-1 downto 0);
begin
if ADD then
-- prepare for an "add" operation
A := L;
B := R;
carry := '0';
else
-- prepare for a "subtract" operation
A := L;
B := not R;
carry := '1';
end if;
-- create a ripple-carry chain; sum up bits
for i in 0 to A'left loop
sum(i) := A(i) xor B(i) xor carry;
carry := (A(i) and B(i)) or (A(i) and carry) or (carry and B(i));
end loop;
return sum; -- result
end;
 function vector2int(S : std_logic_vector(9 downto 0))
return INTEGER is
variable result : INTEGER range 0 to 1023 := 0;
begin
for i in 9 downto 0 loop
result := result * 2;
if S(i) = '1' then
result := result + 1;
end if;
end loop;
return result;
end vector2int;
end MATH;
Time CLK <(10)>

<TIME> CLK <(10)>.

<AUTOMATION> CPU : CLK :
<STATES>
ADS : MAR <- IAR, IAR <- IAR+1, -> IFT
IFT : IR <- M(MAR), -> DEC.
DEC : MAR <- ADR,
?OP #4 -> LDA
#8 -> STA
#16 -> ADD
#32 -> BRA
#33 -> BPR.
LDA : ACC <- M(MAR), -> ADS.
STA : M(MDR) <- ACC, -> ADS.
ADD : AC <- ACC+M(MAR), -> ADS.
BRA : IAR <- ADR, -> ADS.
BRP : |* -ACC(0) *| IAR <- ADR, -> ADS.
<END>.
<END> CPU.
SCL (Simulation Control Language)

 Simulation Control Program by SCL

Program
0 LOAD 3
1 ADD 4
2 STORE 5
Data
3 7
4 9결과
5
Memor
y
Addres
s
 Slmulation Control program by SCL

INIT M(0) = X’ 1003’

Memory 초기 설정
INIT M(1) = X’ 4004’
INIT M(2) = X’ 2005’
INIT M(3) = X’ 0007’
INIT M(4) = X’ 0009’
CPU 상태 초기 설정
INIT CPU = ADS = B’ 0’ CPU
TRACEX AT 0 AT 1000 IAR, MAR, IR, ACC, M(5)
STRAT 120
인쇄형식 지정
Simulation 개시 및
종료시각의 지정
 Program Example & memory Initialization
 Simulation Execution Result
Circuit Design
 Terminal
HDL Description Circuit Symbol
----A
BUS a <Terminal> A, B, C ----B
----C

<Terminal> BUS(4) ----BUS(0)

BUS b ----BUS(1) --/--BUS
----BUS(2) 4
----BUS(3)
 Boolean
 Combination Logic
 Register
 Flip-Flop
Collection of Conditions
Transition Condition to Reg. & Memory
Circuit Design
• Data Path 회로
제어회로 설계
State ST(0) ST(1) St(2)

ADS 0 0 0
상태의 수 : 8 개
IFT 0 0 1
3 개의 F.F. 가
DCE 0 1 0 필요
LDA 0 1 1 ST(0)
STA 1 0 0 ST(1)
ADD 1 0 1 ST(2)
BRA 1 1 0

BRP 1 1 1
|* ㄱ ST(0)& ㄱ ST(1)& ㄱ ST(2)*|ST(2)<-1
|* ㄱ ST(0)& ㄱ ST(1)&ST(2)*|ST(1)<-1, ST(2)<-0.
|* ㄱ ST(0)&ST(1)& ㄱ ST(2)&(IR(0:5):=4)*|ST(2)<-1.
|* ㄱ ST(0)&ST(1)& ㄱ ST(2)&(IR(0:5):=8)*|ST(0)<-1,ST(1)<-1.
|* ㄱ ST(0)&ST(1)& ㄱ ST(2)&(IR(0:5):=16)*|ST(0)<-1,ST(1)<-1.ST(2)<-2
|* ㄱ ST(0)&ST(1)& ㄱ ST(2)&(IR(0:5):=32)*|ST(0)<-1.
|* ㄱ ST(0)&ST(1)& ㄱ ST(2)&(IR(0:5):=33)*|ST(2)<-1.ST(2)<-2
|* ㄱ ST(0)& ㄱ ST(1)&ST(2)*|ST(1)<-0, ST(2)<-0.
|*ST(0)& ㄱ ST(1)& ㄱ ST(2)*|ST(0)<-0.
|*ST(0)& ㄱ ST(1)&ST(2)*|ST(0)<-0, ST(2)<-0.
|*ST(0)&ST(1)& ㄱ ST(2)*|ST(0)<-0, ST(1)<-0.
|*ST(0)&ST(1)&ST(2)*|ST(0)<-0, ST(1)<-0ST(2)<-0.

ST(0) SET CONDITION

ㄱ ST(0)&ST(1)& ㄱ ST(2)&(IR(0:5):=8|IR(0:5):=16|IR(0:5):=32|IR(0:5):=33)
ST(0) RESET CONTROL
ST(0)
ST(1) SET CONDITION
ㄱ ST(0)&ST(1)& ㄱ ST(2)
ST(1) RESET CONDITION
ST(0)&ST(1)&ST(2)&(IR(0:5):=8)|(IR(0:5):=16)
ST(2) SET CONDITION
ㄱ ST(0)& ㄱ ST(2)( ㄱ ST(1)|IR(0:5):=4)|(IR(0:5):=16|IR(0:5):=33)
ST(2) RESET CONTROL
ST(2)
 Control Path
 Simplified Control Bus
Design of Adder
 Full Adder & Half Adder
 16 Bit Adder
Micro-Programmed CPU Design
 Empties represent 0
Control Rom
- 16 bit선두 10bit 는 제어신호로 할당
마지막 4bit 는 다음 read 번지 지정용
- 조건분기에 의해 add 가 변할 경우 10, 11 번째
SOP COND 를 “ 1” 로 하여 add 를 지정

0 번지 : SIAR alc LMAR 이 1 이므로 MAR  IAR

next 번지는 0001 번지
1 번지 : SIAR, LIAR, ONE 이 1 이므로 IAR  IAR+1
3 번지 : SIR, LMAR 이 1, IR 의 ADR 부를 MAR 에 넣는다
단 다음의 명령은 OP 부의 내용에 의한다 (SOP 를 1)
7 번지 : COND=1, ACC 의 선두 bit 이 0 이면 ROM ADR 은 1000 이 되고
ACC 의 선두 bit 이 1 이면 ROMADR 은 1001 이 된다 . 즉 ACC 의
선두가 (+),0 이면 8 번지 u- 명령이 실행되고 IAR 의 내용이 IR 의
ADD 부로 치환됨
ACC 가 (-) 이면 9 번지 명령수행  아무것도 하지 않고 0 번지로
<SYSTEM> MICRO:
<TIME> CLK<(10)>.
<STORAGE> M(1024,16), ROM(16,16).
<REGISTER> IR(16)=OP(6)||ADR(10).
ACC(16),IAR(10),MAR(10),ROMADR(4).
<TERMINAL> ABUS(16),BBUS(16),CBUS(16),RBUS(4),OPA(4),
CONTROL(16) =SIR||LIR||SACC||LACC||SIAR||LIAR||
LMAR||READ||WRITE||ONE||SOP||COND||NEXT(4).
<BOOLEAN>
ABUS=SIR & IR|SACC & ACC|SIAR & B’000000’||IAR,
BBUS=READ & M(MAR)|ONE & B’1(16)’,
CBUS=ABUS+BBUS,
CONTROL=ROM(ROMADR),
RBUS=SOP & OPA| ～ SO[P & NEXT|B’000’||(COND & ～ ACC(0),
? OP # B’000100’ OPA = B’0100’
# B’001000’ OPA = B’0101’
# B’010000’ OPA = B’0110’
# B’100000’ OPA = B’1000’
# B’100001’ OPA = B’0111’..
<AUTOMATION> CPU:CLK:
<LOGIC>|* LIR *| IR <- CBUS.,
|* LACC *| ACC <- CBUS.,
|* LIAR *| IAR <- CBUS(0:9).,
|* LMAR *| MAR <- CBUS(0:9).,
|* WRITE *| M(MAR) <- CBUS.,
ROMADR <- RBUS.
<END> CPU.
<END> MICRO.
• Partition
<SYSTEM> LSIS:
<TIME> CLK<(10)..
<STORAGE> M(1024,16), ROM(16,16).
<TERMINAL> ABUS(16), BBUS(16), CBUS(16), OPC(6), NEG, MAD(10), RAD(4), CONTROL(16)=SIR|
|LIR||SACC||LACC||SIAR||LMAR||READ||WRITE||ONE||SOP||COND||NEXT(4),ABUS1(16),ABU
S2(16),ABUS3(16).
<BOOLEAN> ABUS=ABUS1|ABUS2|ABUS3, CONTROL=ROM(RAD).
<AUTOMATION> LSI1: CLK:
<REGISTER> IR(16)=OP(6)||ADR(10).
<LOGIC> ABUS1=SIR&IR, IR 및 그 주변회로
OPC=OP,
|* LIR *| IR <- CBUS..
<END> LSI1.
<AUTOMATION> LSI2: CLK:
― μ program controles CPU 를 점선으로 나타냄 7 개의 LSI 로 나누어 설계 .
― 각 LSI 는 Automation 으로 description 되어 있음 .
<REGISTER> ACC(16).
<LOGIC> ABUS2 = SACC & ACC,
NEG = ～ ACC(0), ACC 및 그 주변회로
|* LACC *| ACC <- CBUS..
<END> LSI2.
<AUTOMATION> LSI3: CLK:
<REGISTER> IAR(10).
<LOGIC> ABUS3(0:9) = SIAR & IAR,
|* LIAR *| IAR <- CBUS..
<END> LSI3.
<AUTOMATION> LSI4: CLK:
<BOOLEAN> CBUS = S < (ABUS,BBUS) >.
<OPERATOR> S < (A,B) > (16)
<TERMINAL> A(16), B(16), C(16).
<BOOLEAN>
C = A & B|(A@B) & C(1:15)||B1’0,
S = A@B@C(1:15)||B’0’.
<END> S.
<END> LSI4.
<AUTOMATION> LSI5: CLK:
<REGISTER> MAR(10).
<LOGIC> MAD = MAR,
|* LMAR *| MAR <- CBUS(0:9)..
<END> LSI5.
<AUTOMATION> LSI6: CLK:
<BOOLEAN>
BBUS = READ & M(MAD)|ONE & B’1(16)’.
<END> LSI6.
<AUTOMATION> LSI7: CLK:
<REGISTER> ROMADR(4).
<TERMINAL> OPA(4), RBUS(4).
<LOGIC>
RBUS = SOP & OPA| ～ SOP & NEXT|B’000’||(NEG & COND),
RAD = ROMADR,
? OPC # B’000100’ OPA = B’0100’
# B’001000’ OPA = B’0101’
# B’010000’ OPA = B’0110’
# B’100000’ OPA = B’1000’
# B’100001’ OPA = B’0111’.,
ROMADR <- RBUS.
<END> LSI7.
<END> LSIS.
<AUTOMATION> LSI1 IR -- and its peripherals
<AUTOMATION> LSI2 ACC -- and its peripherals
<AUTOMATION> LSI3 IAR -- and its peripherals
<AUTOMATION> LSI4 ADDER
<AUTOMATION> LSI5 MAR --and its peripherals
<AUTOMATION> LSI6 BBUS -- and its peripherals
<AUTOMATION> LSI7 ROMADR, RBUS -- and its peripherals
<SYSTEM> TEST7:
<ENTERANCE> OPC(6), NEG.
<TIME> CLK <(10)>.
<STORAGE> ROM(16,16).
<TERMINAL> RAD(4),
CONTROL(16) = SIR||LISR||SACC||LACC||SIAR||LIAR||LMAR||
READ||WRITE||ONE||SOP||COND||NEXT||(4).
<BOOLEAN> CONTROL = ROM(RAD).
<AUTOMATION> LSI7: CLK:
<END> LSI7.
<END> TEST7.

< LSI7 부분을 ROM 과 함께 simulation 할 경우 >