Chapter 2 Fault Modeling: The Testing Problem

2 Fault Modeling
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Chapter 2 Fault Modeling

The Testing Problem Given a set of faults in the circuit under test (CUT), how do we obtain a certain (small) number of test patterns which guarantees a certain (high) fault coverage? What faults to test? (fault modeling) How are test patterns obtained? (test pattern generation) How is test quality (fault coverage) measured? (fault simulation) How are test vectors applied and results evaluated? (ATE/BIST)
Faults (Fault Models) Why should we model faults? B classical faults 6 single (line) stuck-at fault: The given line has a constant value (0/1) independent of other signal values in the circuit.
a b c s-a-0 or s/0 or simply /0
0 0 1 1 0 1 0 1 0 0 0 1 0 0 0 0 0 1 0 1
0 0 0 0
0 0 1 1
0 0 0 0
1 1 1 1
Always associated with lines (wires).

c Cheng-Wen Wu, Lab for Reliable Computing (LaRC), EE, NTHU
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Node stuck-at fault is less popular. Why? 6 multiple stuck fault: Several single stuck-at faults occur at the same time. For a circuit with lines, i.e., input signals and element inputs and outputs, there are single stuck faults, and multiple stuck faults. For large combinational circuits with multiple outputs, almost all multiple faults can be covered by test patterns derived for single faults. 6 bridging fault: Two or more normally distinct points (lines) are shorted together. x input bridging Can form wired logic or voting model. y feedback (input-to-output) bridging Can introduce feedback. Can cause oscillation or latching (additional memory).

MOS failure mechanism particle on mask failure mode shorted metal lines fault model bridging
B non-classical faults 6 pattern-sensitive fault: the presence of a faulty signal depends on signal values of nearby points (most common in DRAMs).
0 0 0 0 0 0
6 coupling fault: pattern sensitivity between a pair of cells. 6 crosspoint fault A PLA inherently has a device (diode or transistor) at every crosspoint in the (AND and OR) arrays, even if it may not be used.
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The connection of each diode is programmed to realize the desired logic. A crosspoint fault can be caused by an extra or a missing device.
, which cannot be modeled by any stuck-at fault. 6 transistor stuck-open fault: Transistor (switch) is always off, not controllable by gate input. Can turn the circuit into a sequential one. More difcult to test: need a sequence of at least 2 tests to detect a single fault. Unique to CMOS circuits. Why not for nMOS?
0 0 0
0 0 1 1
0 1 0 1
1 0 0 0
1 0
0 0
6 transistor stuck-on fault: Transistor (switch) is always on, not controllable by gate input. Caused by a permanently conducting transistor. Also occurs in a CMOS circuit. E.g., , but depends on the relative impedances of the pull-up & pull-down networks ( should monitor the current drawn by the circuit).
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6 (line) break (stuck-open) fault: An open wire. 6 (line stuck-)short fault: Bridging fault. 6 delay fault: Propagation (transition) delays along a path (gate) fall outside the desired limits. 00 10
11
Either path delay fault or gate delay fault. Stuck-open/stuck-on faults are switch-level (transistor-level) faults; stuckat/bridging/delay faults are gate-level faults; pattern-sensitivity/crosspoint faults are function-level faults. Functional faults are more useful for RAMs and PLAs. There are testing strategies that do not require fault models, e.g., exhaustive test and comparison test by random or functional patterns. Permanent faults include combinational faults (universal faults) and sequential faults.
More on Delay Fault B Gate delay fault (GDF): the delay defects are lumped at a faulty gate and can be detected by propagating the defect to observable outputs via any path(s). 6 Gross gate delay fault: assumes the defect is large such that we can detect it by propagating it through any path to a PO. 6 Transition fault: a special case of the gross gate delay fault model assumes the fault at a gate makes the delay exceed the clock period of the network.
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6 Small gate delay fault: observable only by propagating it through specic paths. B Path-delay fault (PDF): the excessive delay is distributed along the faulty path. Upper bound for number of paths is exponential with respect to gate count. In practice, only a small portion of the set of paths can be tested explicitly. How do we determine the set of paths to be tested explicitly? How do we determine the fault coverage? Two-pattern test ( ): and are called the initialization vector and propagation vector, respectively. Final Value Input Latches (initial values) Input Clock Combinational Circuit Output Latches Output Clock
1. Apply to the input latch at time
2. When the signals become stable, is appled at such that a desired transition is propagated (along the path under test) to the output. 3. Sample the outputs at
, where is the system clock interval.

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A delay failure may be masked by other delay failures, hazards, and glitchs. If a test ( ) is guaranteed to detect a fault , regardless of delays on other paths, it is a robust test (RT) of .
Test, Test Set, and Testing Denition 1 A test for a fault in a network N is an input combination for which the output(s) of N is different when is present than when it is not. A.k.a. test pattern, test vector, or experiment. Test can also mean a testing process, e.g., random test. x detects
Let be the function to be realized, and be a fault which changes to . An input = = a, , is a test for (i.e., it detects ) iff

Denition 2 A test set for a class of faults detects .
is a set of tests such that
The test set for a fault is
Denition 3 Fault detection: tells only whether a circuit is fault-free or not. Denition 4 Fault location (isolation): provides the location and the type of the detected fault and other related information.
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Denition 5 Fault diagnosis includes fault detection and fault location. The input x distinguishes a fault from another fault iff x distinguishes from
, i.e.,
Denition 6 Testing is a process which includes test pattern generation, test pattern application, and output evaluation. The quality of a test set depends on its fault coverage (FC) as well as its size. FC (typically 98%99% single stuck faults) can be determined by fault simulation (to be discussed in Chap. 4).
Fault Collapsing Denition 7 Two faults and in a logic network N are (functionally) equivalent iff the output function realized by N in the presence of is the same function realized by N in the presence of , i.e.,
.
. . (-input gate) .
If a set of faults are equivalent, any test which detects one of them will detect all of them, and no test will distinguish among them.
Six possible single stuck faults, but

. possible single stuck faults.
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AND gate all s/0 faults are equivalent. OR gate all s/1 faults are equivalent.
faults need to be consideredequivalence fault collapsing.

, i.e.,
. .
Denition 8 A fault dominates another fault in a logic network N iff
Any test which detects will also detect . OR gate dominates AND gate dominates
Need not consider .
Equivalence fault collapsing + dominance fault collapsing only faults on any -input gate need be considered.
one output stuck fault need not be considereddominance fault collapsing.

single stuck faults

0 1 1 1
1 0 1 1
1 1 0 1 0 0 0 1
Also detects , , and . Each also detects
.
Theorem 1 In a fanout free combinational circuit, any test set which detects all stuck faults on primary inputs will detect all stuck faults. Denition 9 The set of all primary inputs and all fanout branches are called the checkpoints of the circuit. Theorem 2 In a combinational circuit, any test set which detects all single (multiple) stuck faults on check points will detect all single (multiple) stuck faults.
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Collapsing by Fault Diagrams 1. Represent each line by a pair of circles: the upper circle stands for /1, and the lower circle for /0. 2. Two circles are connected by an edge if they are equivalent. Each net on the diagram represents a single fault equivalence class.
NAND
AND OR
NOR
NOT
a c e
b d f
b c
d f e
Six equivalent classes (6 tests)
3. Add directed arcs from the dominating faults toward the dominated faults.
AND OR NAND NOR
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4. For fanouts, view the stem and each branch as a separate line. Direction of dominance is opposite that of the gates.
equivalence network
Two tests.
a a bd ce f g c d h b e
16 single faults 10 equivalent classes 6 tests
Test Compaction Denition 10 Test compaction refers to the process of reducing the number of test patterns in a test set without reducing its fault coverage. Can equivalence fault collapsing and dominance fault collapsing be used to aid test compaction? Apart from equivalence and dominance relations, is there any other fault relation that can be used to aid test compaction?
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